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msvc_compa
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5866acf565
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1
.gitignore
vendored
1
.gitignore
vendored
@ -31,3 +31,4 @@ language.settings.xml
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/*.out
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/dump.json
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/src-gen/
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/*.yaml
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Submodule gen_input/CoreDSL-Instruction-Set-Description updated: 8d9a0fb149...9e3119a806
14
gen_input/TGC_B.core_desc
Normal file
14
gen_input/TGC_B.core_desc
Normal file
@ -0,0 +1,14 @@
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import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGC_B provides RV32I {
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architectural_state {
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XLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000000000100000000;
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unsigned MARCHID_VAL = 0x80000002;
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}
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}
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13
gen_input/TGC_C.core_desc
Normal file
13
gen_input/TGC_C.core_desc
Normal file
@ -0,0 +1,13 @@
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import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGC_C provides RV32I, RV32M, RV32IC {
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architectural_state {
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XLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000001000100000100;
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unsigned MARCHID_VAL = 0x80000003;
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}
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}
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13
gen_input/TGC_D.core_desc
Normal file
13
gen_input/TGC_D.core_desc
Normal file
@ -0,0 +1,13 @@
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import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGC_D provides RV32I, RV32M, RV32IC {
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architectural_state {
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XLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000001000100000100;
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unsigned MARCHID_VAL = 0x80000004;
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}
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}
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73
gen_input/TGC_D_XRB_MAC.core_desc
Normal file
73
gen_input/TGC_D_XRB_MAC.core_desc
Normal file
@ -0,0 +1,73 @@
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import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
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import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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InstructionSet X_RB_MAC extends RISCVBase {
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architectural_state {
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register unsigned<64> ACC;
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}
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instructions {
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RESET_ACC { // v-- funct7 v-- funct3
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encoding: 7'd0 :: 10'b0 :: 3'd0 :: 5'b0 :: 7'b0001011;
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behavior: ACC = 0;
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}
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GET_ACC_LO {
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encoding: 7'd1 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
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behavior: if (rd != 0) X[rd] = ACC[31:0];
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}
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GET_ACC_HI {
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encoding: 7'd2 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
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behavior: if (rd != 0) X[rd] = ACC[63:32];
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}
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MACU_32 {
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encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
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behavior: {
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unsigned<64> mul = X[rs1] * X[rs2];
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unsigned<33> add = mul[31:0] + ACC[31:0];
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ACC = add[31:0];
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}
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}
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MACS_32 {
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encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
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behavior: {
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signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
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signed<33> add = ((signed) mul[31:0]) + ((signed) ACC[31:0]);
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ACC = add[31:0]; // bit range always yields unsigned type
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}
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}
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MACU_64 {
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encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
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behavior: {
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unsigned<64> mul = X[rs1] * X[rs2];
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unsigned<65> add = mul + ACC;
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ACC = add[63:0];
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}
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}
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MACS_64 {
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encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
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behavior: {
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signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
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signed<65> add = mul + ((signed) ACC);
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ACC = add[63:0];
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}
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}
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}
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}
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Core TGC_D_XRB_MAC provides RV32I, RV32M, RV32IC, X_RB_MAC {
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architectural_state {
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XLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000001000100000100;
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unsigned MARCHID_VAL = 0x80000004;
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}
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}
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@ -1,37 +0,0 @@
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import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
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import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
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Core TGC_B provides RV32I {
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architectural_state {
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unsigned XLEN=32;
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unsigned PCLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000000000100000000;
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unsigned PGSIZE = 0x1000; //1 << 12;
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unsigned PGMASK = 0xfff; //PGSIZE-1
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}
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}
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Core TGC_C provides RV32I, RV32M, RV32IC {
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architectural_state {
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unsigned XLEN=32;
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unsigned PCLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000001000100000100;
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unsigned PGSIZE = 0x1000; //1 << 12;
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unsigned PGMASK = 0xfff; //PGSIZE-1
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}
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}
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Core TGC_D provides RV32I, RV32M, RV32IC {
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architectural_state {
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unsigned XLEN=32;
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unsigned PCLEN=32;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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unsigned MISA_VAL = 0b01000000000000000001000100000100;
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}
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}
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16
gen_input/templates/CORENAME_instr.yaml.gtl
Normal file
16
gen_input/templates/CORENAME_instr.yaml.gtl
Normal file
@ -0,0 +1,16 @@
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<% def getInstructionGroups() {
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def instrGroups = [:]
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instructions.each {
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def groupName = it['instruction'].eContainer().name
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if(!instrGroups.containsKey(groupName)) {
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instrGroups[groupName]=[]
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}
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instrGroups[groupName]+=it;
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}
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instrGroups
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}%><%getInstructionGroups().each{name, instrList -> %>
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${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
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- ${it.instruction.name}
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encoding: ${it.encoding}
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mask: ${it.mask}<%}}%>
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@ -64,7 +64,7 @@ public:
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using addr_t = typename super::addr_t;
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using reg_t = typename traits::reg_t;
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using mem_type_e = typename traits::mem_type_e;
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vm_impl();
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vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
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@ -324,6 +324,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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if (is_jump_to_self_enabled(cond) &&
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(insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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auto f = decode_inst(insn);
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auto old_pc = pc.val;
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pc = (this->*f)(pc, insn);
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}
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}
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@ -307,7 +307,7 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
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// reset values
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csr[misa] = traits<BASE>::MISA_VAL;
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csr[mvendorid] = 0x669;
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csr[marchid] = 0x80000003;
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csr[marchid] = traits<BASE>::MARCHID_VAL;
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csr[mimpid] = 1;
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uart_buf.str("");
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@ -362,8 +362,8 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
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csr_rd_cb[mie] = &this_class::read_ie;
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csr_wr_cb[mie] = &this_class::write_ie;
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csr_rd_cb[mhartid] = &this_class::read_hartid;
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csr_rd_cb[mcounteren] = &this_class::read_null;
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csr_wr_cb[mcounteren] = &this_class::write_null;
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// csr_rd_cb[mcounteren] = &this_class::read_null;
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// csr_wr_cb[mcounteren] = &this_class::write_null;
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csr_wr_cb[misa] = &this_class::write_null;
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csr_wr_cb[mvendorid] = &this_class::write_null;
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csr_wr_cb[marchid] = &this_class::write_null;
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@ -920,7 +920,16 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
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if (trap_id == 0) { // exception
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// store ret addr in xepc register
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csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
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csr[mtval] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data;
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switch(cause){
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case 0:
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csr[mtval] = addr;
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break;
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case 2:
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csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
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break;
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default:
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csr[mtval] = fault_data;
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}
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fault_data = 0;
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} else {
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csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
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@ -145,7 +145,7 @@ public:
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mstatus_t mstatus;
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static const reg_t mstatus_reset_val = 0;
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static const reg_t mstatus_reset_val = 0x1800;
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void write_mstatus(T val, unsigned priv_lvl) {
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auto mask = get_mask(priv_lvl);
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@ -398,7 +398,7 @@ private:
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iss::status read_ip(unsigned addr, reg_t &val);
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iss::status write_ip(unsigned addr, reg_t val);
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iss::status read_hartid(unsigned addr, reg_t &val);
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iss::status write_mepc(unsigned addr, reg_t val);
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iss::status write_epc(unsigned addr, reg_t val);
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iss::status read_satp(unsigned addr, reg_t &val);
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iss::status write_satp(unsigned addr, reg_t val);
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iss::status read_fcsr(unsigned addr, reg_t &val);
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@ -419,7 +419,7 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
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// reset values
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csr[misa] = traits<BASE>::MISA_VAL;
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csr[mvendorid] = 0x669;
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csr[marchid] = 0x80000003;
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csr[marchid] = traits<BASE>::MARCHID_VAL;
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csr[mimpid] = 1;
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uart_buf.str("");
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@ -954,8 +954,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ip(unsigned
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_epc(unsigned addr, reg_t val) {
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csr[addr] = val & get_pc_mask();
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template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_epc(unsigned addr, reg_t val) {
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csr[addr] = val & get_pc_mask();
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return iss::Ok;
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}
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@ -146,7 +146,7 @@ public:
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mstatus_t mstatus;
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static const reg_t mstatus_reset_val = 0;
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static const reg_t mstatus_reset_val = 0x1800; // MPP set to 1
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void write_mstatus(T val, unsigned priv_lvl) {
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auto mask = get_mask(priv_lvl);
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@ -349,7 +349,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
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// reset values
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csr[misa] = traits<BASE>::MISA_VAL;
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csr[mvendorid] = 0x669;
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csr[marchid] = 0x80000004;
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csr[marchid] = traits<BASE>::MARCHID_VAL;
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csr[mimpid] = 1;
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csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file
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@ -543,25 +543,27 @@ template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_
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constexpr auto PMP_NA4 =0x2U;
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constexpr auto PMP_NAPOT =0x3U;
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reg_t base = 0;
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auto any_active = false;
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for (size_t i = 0; i < 16; i++) {
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reg_t tor = csr[pmpaddr0+i] << PMP_SHIFT;
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uint8_t cfg = csr[pmpcfg0+(i/4)]>>(i%4);
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if (cfg & PMP_A) {
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any_active=true;
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auto pmp_a = (cfg & PMP_A) >> 3;
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bool is_tor = pmp_a == PMP_TOR;
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bool is_na4 = pmp_a == PMP_NA4;
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auto is_tor = pmp_a == PMP_TOR;
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auto is_na4 = pmp_a == PMP_NA4;
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reg_t mask = (csr[pmpaddr0+i] << 1) | (!is_na4);
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mask = ~(mask & ~(mask + 1)) << PMP_SHIFT;
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// Check each 4-byte sector of the access
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bool any_match = false;
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bool all_match = true;
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auto any_match = false;
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auto all_match = true;
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for (reg_t offset = 0; offset < len; offset += 1 << PMP_SHIFT) {
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reg_t cur_addr = addr + offset;
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bool napot_match = ((cur_addr ^ tor) & mask) == 0;
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bool tor_match = base <= cur_addr && cur_addr < tor;
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bool match = is_tor ? tor_match : napot_match;
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auto napot_match = ((cur_addr ^ tor) & mask) == 0;
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auto tor_match = base <= cur_addr && cur_addr < tor;
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auto match = is_tor ? tor_match : napot_match;
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any_match |= match;
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all_match &= match;
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}
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@ -577,7 +579,7 @@ template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_
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}
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base = tor;
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}
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return this->reg.PRIV == PRIV_M;
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return !any_active || this->reg.PRIV == PRIV_M;
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}
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@ -926,8 +928,6 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
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template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
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auto mask = get_irq_wrmask((addr >> 8) & 0x3);
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if(this->reg.PRIV==0)
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mask&= ~(0xff<<4); // STIE and UTIE are read only in user and supervisor mode
|
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csr[mie] = (csr[mie] & ~mask) | (val & mask);
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check_interrupt();
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return iss::Ok;
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@ -1256,27 +1256,33 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
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template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::leave_trap(uint64_t flags) {
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auto cur_priv = this->reg.PRIV;
|
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auto inst_priv = (flags & 0x3)? 3:0;
|
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auto status = state.mstatus;
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// pop the relevant lower-privilege interrupt enable and privilege mode stack
|
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// clear respective yIE
|
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switch (inst_priv) {
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case PRIV_M:
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this->reg.PRIV = state.mstatus.MPP;
|
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state.mstatus.MPP = 0; // clear mpp to U mode
|
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state.mstatus.MIE = state.mstatus.MPIE;
|
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state.mstatus.MPIE = 1;
|
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break;
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case PRIV_U:
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this->reg.PRIV = 0;
|
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state.mstatus.UIE = state.mstatus.UPIE;
|
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state.mstatus.UPIE = 1;
|
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break;
|
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if(inst_priv>cur_priv){
|
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auto trap_val = 0x80ULL << 24 | (2 << 16); // illegal instruction
|
||||
this->reg.trap_state = trap_val;
|
||||
this->reg.NEXT_PC = std::numeric_limits<uint32_t>::max();
|
||||
} else {
|
||||
auto status = state.mstatus;
|
||||
// pop the relevant lower-privilege interrupt enable and privilege mode stack
|
||||
// clear respective yIE
|
||||
switch (inst_priv) {
|
||||
case PRIV_M:
|
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this->reg.PRIV = state.mstatus.MPP;
|
||||
state.mstatus.MPP = 0; // clear mpp to U mode
|
||||
state.mstatus.MIE = state.mstatus.MPIE;
|
||||
state.mstatus.MPIE = 1;
|
||||
break;
|
||||
case PRIV_U:
|
||||
this->reg.PRIV = 0;
|
||||
state.mstatus.UIE = state.mstatus.UPIE;
|
||||
state.mstatus.UPIE = 1;
|
||||
break;
|
||||
}
|
||||
// sets the pc to the value stored in the x epc register.
|
||||
this->reg.NEXT_PC = csr[uepc | inst_priv << 8];
|
||||
CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to "
|
||||
<< lvl[this->reg.PRIV];
|
||||
check_interrupt();
|
||||
}
|
||||
// sets the pc to the value stored in the x epc register.
|
||||
this->reg.NEXT_PC = csr[uepc | inst_priv << 8];
|
||||
CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to "
|
||||
<< lvl[this->reg.PRIV];
|
||||
check_interrupt();
|
||||
return this->reg.NEXT_PC;
|
||||
}
|
||||
|
||||
|
@ -51,9 +51,9 @@ template <> struct traits<tgc_c> {
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
|
||||
|
||||
static constexpr std::array<const char*, 35> reg_aliases{
|
||||
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
|
||||
{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV"}};
|
||||
|
||||
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
|
||||
enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
|
||||
|
||||
constexpr static unsigned FP_REGS_SIZE = 0;
|
||||
|
||||
|
11
src/main.cpp
11
src/main.cpp
@ -49,6 +49,11 @@ using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
|
||||
#include "iss/arch/tgc_d.h"
|
||||
using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_D_XRB_MAC
|
||||
#include "iss/arch/riscv_hart_mu_p.h"
|
||||
#include "iss/arch/tgc_d_xrb_mac.h"
|
||||
using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
|
||||
#endif
|
||||
#ifdef WITH_LLVM
|
||||
#include <iss/llvm/jit_helper.h>
|
||||
#endif
|
||||
@ -138,6 +143,12 @@ int main(int argc, char *argv[]) {
|
||||
std::tie(cpu, vm) =
|
||||
iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
|
||||
} else
|
||||
#endif
|
||||
#ifdef CORE_TGC_D_XRB_MAC
|
||||
if (isa_opt == "tgc_d_xrb_mac") {
|
||||
std::tie(cpu, vm) =
|
||||
iss::create_cpu<tgc_d_xrb_mac_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
|
||||
|
@ -44,6 +44,11 @@ using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
|
||||
#include "iss/arch/tgc_d.h"
|
||||
using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
|
||||
#endif
|
||||
#ifdef CORE_TGC_D_XRB_MAC
|
||||
#include "iss/arch/riscv_hart_mu_p.h"
|
||||
#include "iss/arch/tgc_d_xrb_mac.h"
|
||||
using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, iss::arch::FEAT_PMP>;
|
||||
#endif
|
||||
#include "iss/debugger/encoderdecoder.h"
|
||||
#include "iss/debugger/gdb_session.h"
|
||||
#include "iss/debugger/server.h"
|
||||
@ -285,6 +290,9 @@ public:
|
||||
#endif
|
||||
#ifdef CORE_TGC_D
|
||||
CREATE_CORE(tgc_d)
|
||||
#endif
|
||||
#ifdef CORE_TGC_D_XRB_MACD
|
||||
CREATE_CORE(tgc_d_xrb_mac)
|
||||
#endif
|
||||
{
|
||||
LOG(ERROR) << "Illegal argument value for core type: " << type << std::endl;
|
||||
|
@ -64,7 +64,7 @@ public:
|
||||
using addr_t = typename super::addr_t;
|
||||
using reg_t = typename traits::reg_t;
|
||||
using mem_type_e = typename traits::mem_type_e;
|
||||
|
||||
|
||||
vm_impl();
|
||||
|
||||
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
||||
@ -463,8 +463,13 @@ private:
|
||||
// execute instruction
|
||||
try {
|
||||
{
|
||||
if(rd != 0) *(X+rd) = *PC + 4;
|
||||
pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
|
||||
if(imm % traits::INSTR_ALIGNMENT) {
|
||||
raise(0, 0);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) *(X+rd) = *PC + 4;
|
||||
pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
|
||||
}
|
||||
}
|
||||
} catch(...){}
|
||||
// post execution stuff
|
||||
@ -507,9 +512,14 @@ private:
|
||||
// execute instruction
|
||||
try {
|
||||
{
|
||||
int32_t new_pc = *(X+rs1) + (int16_t)sext<12>(imm);
|
||||
if(rd != 0) *(X+rd) = *PC + 4;
|
||||
pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
|
||||
int32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 1;
|
||||
if(new_pc % traits::INSTR_ALIGNMENT) {
|
||||
raise(0, 0);
|
||||
}
|
||||
else {
|
||||
if(rd != 0) *(X+rd) = *PC + 4;
|
||||
pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
|
||||
}
|
||||
}
|
||||
} catch(...){}
|
||||
// post execution stuff
|
||||
@ -551,7 +561,12 @@ private:
|
||||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(*(X+rs1) == *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
{
|
||||
if(*(X+rs1) == *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
|
||||
raise(0, 0);
|
||||
}
|
||||
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
}
|
||||
} catch(...){}
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 4);
|
||||
@ -592,7 +607,12 @@ private:
|
||||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(*(X+rs1) != *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
{
|
||||
if(*(X+rs1) != *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
|
||||
raise(0, 0);
|
||||
}
|
||||
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
}
|
||||
} catch(...){}
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 5);
|
||||
@ -633,7 +653,12 @@ private:
|
||||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
{
|
||||
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
|
||||
raise(0, 0);
|
||||
}
|
||||
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
}
|
||||
} catch(...){}
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6);
|
||||
@ -674,7 +699,12 @@ private:
|
||||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
{
|
||||
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
|
||||
raise(0, 0);
|
||||
}
|
||||
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
}
|
||||
} catch(...){}
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7);
|
||||
@ -715,7 +745,12 @@ private:
|
||||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
{
|
||||
if(*(X+rs1) < *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
|
||||
raise(0, 0);
|
||||
}
|
||||
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
}
|
||||
} catch(...){}
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 8);
|
||||
@ -756,7 +791,12 @@ private:
|
||||
*NEXT_PC = *PC + 4;
|
||||
// execute instruction
|
||||
try {
|
||||
if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
{
|
||||
if(*(X+rs1) >= *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
|
||||
raise(0, 0);
|
||||
}
|
||||
else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
|
||||
}
|
||||
} catch(...){}
|
||||
// post execution stuff
|
||||
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 9);
|
||||
@ -4138,9 +4178,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
||||
this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
|
||||
pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
|
||||
} else {
|
||||
if (is_jump_to_self_enabled(cond) && (insn == 0x0000006f || (insn&0xffff)==0xa001))
|
||||
throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
if (is_jump_to_self_enabled(cond) &&
|
||||
(insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||
auto f = decode_inst(insn);
|
||||
auto old_pc = pc.val;
|
||||
pc = (this->*f)(pc, insn);
|
||||
}
|
||||
}
|
||||
|
Reference in New Issue
Block a user