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base: DBT-RISE:0996d15bd406d3a73f4860d57b9d468444043843
Branches Tags
DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
..
compare: DBT-RISE:feature/eve_checkin
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

19 Commits
0996d15bd4 ... feature/ev

Author SHA1 Message Date
Eyck-Alexander Jentzsch
7ea3a6261d checkin from eve 2024-12-27 19:17:37 +00:00
Eyck Jentzsch
a6a6f51f0b adds clang-format fixes 2024-12-06 15:50:50 +01:00
Eyck-Alexander Jentzsch
21e1f791ad corrects sysc integration template and corresponding file 2024-12-06 09:49:02 +01:00
Eyck-Alexander Jentzsch
be6f5791fa adds update to cyclecount after each instr for asmjit 2024-11-26 20:26:18 +01:00
Eyck-Alexander Jentzsch
ac818f304d increases verbosity incase elf loading goes wrong 2024-10-21 16:42:58 +02:00
Eyck-Alexander Jentzsch
ad60449073 updates generated cores 2024-09-27 20:04:58 +02:00
Eyck-Alexander Jentzsch
b45b3589fa updates templates to immediately trap when gen_trap is called 2024-09-27 20:03:51 +02:00
Eyck-Alexander Jentzsch
1fb7e8fcea improves logging output 2024-09-24 08:39:34 +02:00
Eyck-Alexander Jentzsch
5f9d0beafb corrects softfloat to comply with RVD ACT 2024-09-23 22:22:57 +02:00
Eyck-Alexander Jentzsch
4c0d1c75aa adds addr formatting to logging 2024-09-23 12:21:43 +02:00
Eyck-Alexander Jentzsch
2f3abf2f76 adds namespaces for ELFIO 2024-09-23 11:55:18 +02:00
Eyck Jentzsch
62768bf81e applies clang format 2024-09-23 10:05:33 +02:00
Eyck Jentzsch
f6be8ec006 adds elfio test utility 2024-09-23 09:29:08 +02:00
Eyck Jentzsch
a8f56b6e27 removes code dupication by unifying elf file read 2024-09-23 09:28:27 +02:00
Eyck-Alexander Jentzsch
76ea0db25d adds newest generated vm_impl 2024-08-17 23:19:51 +02:00
Eyck Jentzsch
ec1b820c18 fixes target xml generation 2024-08-17 19:36:53 +02:00
Eyck Jentzsch
64329cf0f6 fixes use of icount vs. cycle 2024-08-17 19:36:40 +02:00
Eyck Jentzsch
9de0aed84d expands some error message 2024-08-17 16:55:49 +02:00
Eyck Jentzsch
bb4e2766d1 applies clang-format 2024-08-17 16:12:57 +02:00
24 changed files with 4606 additions and 4655 deletions
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21
CMakeLists.txt
View File

@ -109,15 +109,14 @@ if(TARGET yaml-cpp::yaml-cpp)
target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
endif()
if(WITH_LLVM)
find_package(LLVM)
target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
# if(WITH_LLVM)
# target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
# target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
if(BUILD_SHARED_LIBS)
target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
endif()
endif()
# if(BUILD_SHARED_LIBS)
# target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
# endif()
# endif()
set_target_properties(${PROJECT_NAME} PROPERTIES
VERSION ${PROJECT_VERSION}
@ -262,3 +261,9 @@ if(TARGET scc-sysc)
INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
)
endif()
project(elfio-test)
find_package(Boost COMPONENTS program_options thread REQUIRED)
add_executable(${PROJECT_NAME} src/elfio.cpp)
target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)

4
gen_input/templates/CORENAME.h.gtl
View File

@ -131,8 +131,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
uint8_t* get_regs_base_ptr() override;
inline uint64_t get_icount() { return reg.icount; }
inline bool should_stop() { return interrupt_sim; }
inline uint64_t stop_code() { return interrupt_sim; }
@ -141,8 +139,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
#pragma pack(push, 1)
struct ${coreDef.name}_regs {<%

24
gen_input/templates/CORENAME_sysc.cpp.gtl
View File

@ -45,17 +45,17 @@ namespace interp {
using namespace sysc;
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
}),
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%}%>
@ -66,17 +66,17 @@ namespace llvm {
using namespace sysc;
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
}),
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%}%>
@ -88,17 +88,17 @@ namespace tcc {
using namespace sysc;
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
}),
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%}%>
@ -110,17 +110,17 @@ namespace asmjit {
using namespace sysc;
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
}),
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
})<%}%>

2
gen_input/templates/asmjit/CORENAME.cpp.gtl
View File

@ -263,6 +263,7 @@ void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
cmp(cc, current_trap_state, 0);
cc.jne(jh.trap_entry);
cc.inc(get_ptr_for(jh, traits::ICOUNT));
cc.inc(get_ptr_for(jh, traits::CYCLE));
}
template <typename ARCH>
void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
@ -308,6 +309,7 @@ inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t
auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
cc.jmp(jh.trap_entry);
}
template <typename ARCH>
template <typename T, typename>

5
gen_input/templates/llvm/CORENAME.cpp.gtl
View File

@ -204,7 +204,7 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
get_reg_ptr(traits::PC), true);
this->builder.CreateStore(
@ -279,6 +279,7 @@ template <typename ARCH>
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
this->builder.CreateBr(this->trap_blk);
}
template <typename ARCH>
@ -381,4 +382,4 @@ volatile std::array<bool, 2> dummy = {
};
}
}
// clang-format on
// clang-format on

21
gen_input/templates/tcc/CORENAME.cpp.gtl
View File

@ -83,21 +83,21 @@ protected:
using vm_base<ARCH>::get_reg_ptr;
using this_class = vm_impl<ARCH>;
using compile_ret_t = std::tuple<continuation_e>;
using compile_ret_t = continuation_e;
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
<%
if(fcsr != null) {%>
inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}
void add_prologue(tu_builder& tu) override;
<%}%>
void add_prologue(tu_builder& tu) override;
void setup_module(std::string m) override {
super::setup_module(m);
}
compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
compile_ret_t gen_single_inst_behavior(virt_addr_t &, tu_builder&) override;
void gen_trap_behavior(tu_builder& tu) override;
@ -225,8 +225,8 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
}()) {}
template <typename ARCH>
std::tuple<continuation_e>
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
continuation_e
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, tu_builder& tu) {
// we fetch at max 4 byte, alignment is 2
enum {TRAP_ID=1<<16};
code_word_t instr = 0;
@ -238,7 +238,6 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
return ILLEGAL_FETCH;
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
return JUMP_TO_SELF;
++inst_cnt;
uint32_t inst_index = instr_decoder.decode_instr(instr);
compile_func f = nullptr;
if(inst_index < instr_descr.size())
@ -274,9 +273,12 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
tu("return *next_pc;");
}
<%
if(fcsr != null) {%>
template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
std::ostringstream os;
os << add_reg_ptr("trap_state", arch::traits<ARCH>::TRAP_STATE);
os << add_reg_ptr("pending_trap", arch::traits<ARCH>::PENDING_TRAP);
if(fcsr != null) {%>
os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
@ -303,9 +305,10 @@ template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
os << "uint64_t (*fcvt_32_64)(uint32_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_32_64 << ";\\n";
os << "uint32_t (*fcvt_64_32)(uint64_t v1, uint32_t op, uint8_t mode)=" << (uintptr_t)&fcvt_64_32 << ";\\n";
os << "uint32_t (*unbox_s)(uint64_t v)=" << (uintptr_t)&unbox_s << ";\\n";
<%}%>
tu.add_prologue(os.str());
}
<%}%>
} // namespace ${coreDef.name.toLowerCase()}

35
src/elfio.cpp Normal file
View File

@ -0,0 +1,35 @@
#ifdef _MSC_VER
#define _SCL_SECURE_NO_WARNINGS
#define ELFIO_NO_INTTYPES
#endif
#include <elfio/elfio_dump.hpp>
#include <iostream>
using namespace ELFIO;
int main(int argc, char** argv) {
if(argc != 2) {
printf("Usage: elfdump <file_name>\n");
return 1;
}
elfio reader;
if(!reader.load(argv[1])) {
printf("File %s is not found or it is not an ELF file\n", argv[1]);
return 1;
}
dump::header(std::cout, reader);
dump::section_headers(std::cout, reader);
dump::segment_headers(std::cout, reader);
dump::symbol_tables(std::cout, reader);
dump::notes(std::cout, reader);
dump::modinfo(std::cout, reader);
dump::dynamic_tags(std::cout, reader);
dump::section_datas(std::cout, reader);
dump::segment_datas(std::cout, reader);
return 0;
}

99
src/iss/arch/riscv_hart_common.h
View File

@ -35,6 +35,7 @@
#ifndef _RISCV_HART_COMMON
#define _RISCV_HART_COMMON
#include "iss/vm_types.h"
#include <cstdint>
#include <elfio/elfio.hpp>
#include <fmt/format.h>
@ -314,55 +315,67 @@ struct riscv_hart_common {
riscv_hart_common(){};
~riscv_hart_common(){};
std::unordered_map<std::string, uint64_t> symbol_table;
uint64_t entry_address{0};
uint64_t tohost = tohost_dflt;
uint64_t fromhost = fromhost_dflt;
std::unordered_map<std::string, uint64_t> get_sym_table(std::string name) {
if(!symbol_table.empty())
return symbol_table;
FILE* fp = fopen(name.c_str(), "r");
if(fp) {
std::array<char, 5> buf;
auto n = fread(buf.data(), 1, 4, fp);
fclose(fp);
if(n != 4)
throw std::runtime_error("input file has insufficient size");
buf[4] = 0;
if(strcmp(buf.data() + 1, "ELF") == 0) {
// Create elfio reader
ELFIO::elfio reader;
// Load ELF data
if(!reader.load(name))
throw std::runtime_error("could not process elf file");
// check elf properties
if(reader.get_type() != ET_EXEC)
throw std::runtime_error("wrong elf type in file");
if(reader.get_machine() != EM_RISCV)
throw std::runtime_error("wrong elf machine in file");
const auto sym_sec = reader.sections[".symtab"];
if(SHT_SYMTAB == sym_sec->get_type() || SHT_DYNSYM == sym_sec->get_type()) {
ELFIO::symbol_section_accessor symbols(reader, sym_sec);
auto sym_no = symbols.get_symbols_num();
std::string name;
ELFIO::Elf64_Addr value = 0;
ELFIO::Elf_Xword size = 0;
unsigned char bind = 0;
unsigned char type = 0;
ELFIO::Elf_Half section = 0;
unsigned char other = 0;
for(auto i = 0U; i < sym_no; ++i) {
symbols.get_symbol(i, name, value, size, bind, type, section, other);
if(name != "") {
this->symbol_table[name] = value;
bool read_elf_file(std::string name, uint8_t expected_elf_class,
std::function<iss::status(uint64_t, uint64_t, const uint8_t* const)> cb) {
// Create elfio reader
ELFIO::elfio reader;
// Load ELF data
if(reader.load(name)) {
// check elf properties
if(reader.get_class() != expected_elf_class)
return false;
if(reader.get_type() != ELFIO::ET_EXEC)
return false;
if(reader.get_machine() != ELFIO::EM_RISCV)
return false;
entry_address = reader.get_entry();
for(const auto& pseg : reader.segments) {
const auto fsize = pseg->get_file_size(); // 0x42c/0x0
const auto seg_data = pseg->get_data();
const auto type = pseg->get_type();
if(type == 1 && fsize > 0) {
auto res = cb(pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
if(res != iss::Ok)
CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
}
}
const auto sym_sec = reader.sections[".symtab"];
if(ELFIO::SHT_SYMTAB == sym_sec->get_type() || ELFIO::SHT_DYNSYM == sym_sec->get_type()) {
ELFIO::symbol_section_accessor symbols(reader, sym_sec);
auto sym_no = symbols.get_symbols_num();
std::string name;
ELFIO::Elf64_Addr value = 0;
ELFIO::Elf_Xword size = 0;
unsigned char bind = 0;
unsigned char type = 0;
ELFIO::Elf_Half section = 0;
unsigned char other = 0;
for(auto i = 0U; i < sym_no; ++i) {
symbols.get_symbol(i, name, value, size, bind, type, section, other);
if(name != "") {
this->symbol_table[name] = value;
#ifndef NDEBUG
CPPLOG(DEBUG) << "Found Symbol " << name;
CPPLOG(DEBUG) << "Found Symbol " << name;
#endif
}
}
}
return symbol_table;
try {
tohost = symbol_table.at("tohost");
try {
fromhost = symbol_table.at("fromhost");
} catch(std::out_of_range& e) {
fromhost = tohost + 0x40;
}
} catch(std::out_of_range& e) {
}
}
throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
} else
throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
return true;
}
return false;
};
};

76
src/iss/arch/riscv_hart_m_p.h
View File

@ -41,6 +41,7 @@
#include "iss/vm_if.h"
#include "iss/vm_types.h"
#include "riscv_hart_common.h"
#include <elfio/elf_types.hpp>
#include <stdexcept>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
@ -278,7 +279,7 @@ public:
void disass_output(uint64_t pc, const std::string instr) override {
NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]", pc, instr, (reg_t)state.mstatus,
this->reg.icount + cycle_offset);
this->reg.cycle + cycle_offset);
};
iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; }
@ -311,7 +312,7 @@ protected:
uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
@ -321,7 +322,7 @@ protected:
unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
std::unordered_map<std::string, uint64_t> get_symbol_table(std::string name) override { return arch.get_sym_table(name); }
std::unordered_map<std::string, uint64_t> const& get_symbol_table(std::string name) override { return arch.symbol_table; }
riscv_hart_m_p<BASE, FEAT, LOGCAT>& arch;
};
@ -343,8 +344,6 @@ protected:
int64_t instret_offset{0};
uint64_t minstret_csr{0};
reg_t fault_data;
uint64_t tohost = tohost_dflt;
uint64_t fromhost = fromhost_dflt;
bool tohost_lower_written = false;
riscv_instrumentation_if instr_if;
@ -573,57 +572,14 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
template <typename BASE, features_e FEAT, typename LOGCAT>
std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT, LOGCAT>::load_file(std::string name, int type) {
get_sym_table(name);
try {
tohost = symbol_table.at("tohost");
fromhost = symbol_table.at("fromhost");
} catch(std::out_of_range& e) {
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
data);
})) {
return std::make_pair(entry_address, true);
}
FILE* fp = fopen(name.c_str(), "r");
if(fp) {
std::array<char, 5> buf;
auto n = fread(buf.data(), 1, 4, fp);
fclose(fp);
if(n != 4)
throw std::runtime_error("input file has insufficient size");
buf[4] = 0;
if(strcmp(buf.data() + 1, "ELF") == 0) {
// Create elfio reader
ELFIO::elfio reader;
// Load ELF data
if(!reader.load(name))
throw std::runtime_error("could not process elf file");
// check elf properties
if(reader.get_class() != ELFCLASS32)
if(sizeof(reg_t) == 4)
throw std::runtime_error("wrong elf class in file");
if(reader.get_type() != ET_EXEC)
throw std::runtime_error("wrong elf type in file");
if(reader.get_machine() != EM_RISCV)
throw std::runtime_error("wrong elf machine in file");
auto entry = reader.get_entry();
for(const auto pseg : reader.segments) {
const auto fsize = pseg->get_file_size(); // 0x42c/0x0
const auto seg_data = pseg->get_data();
const auto type = pseg->get_type();
if(type == 1 && fsize > 0) {
auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
if(res != iss::Ok)
CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
}
}
for(const auto& sec : reader.sections) {
if(sec->get_name() == ".tohost") {
tohost = sec->get_address();
fromhost = tohost + 0x40;
}
}
return std::make_pair(entry, true);
}
throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
}
throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
return std::make_pair(entry_address, false);
}
template <typename BASE, features_e FEAT, typename LOGCAT>
@ -689,7 +645,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
}
return res;
} catch(trap_access& ta) {
if( (access & access_type::DEBUG) == 0) {
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
@ -750,7 +706,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
<< std::hex << addr;
break;
default:
CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr 0x" << std::hex << addr;
}
#endif
try {
@ -908,7 +864,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_plain(unsigned addr, reg_t
template <typename BASE, features_e FEAT, typename LOGCAT>
iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_cycle(unsigned addr, reg_t& val) {
auto cycle_val = this->reg.icount + cycle_offset;
auto cycle_val = this->reg.cycle + cycle_offset;
if(addr == mcycle) {
val = static_cast<reg_t>(cycle_val);
} else if(addr == mcycleh) {
@ -928,7 +884,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_cycle(unsigned addr, reg_t
mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
}
}
cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around
cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
return iss::Ok;
}
@ -959,7 +915,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_instret(unsigned addr, reg
template <typename BASE, features_e FEAT, typename LOGCAT>
iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_time(unsigned addr, reg_t& val) {
uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
if(addr == time) {
val = static_cast<reg_t>(time_val);
} else if(addr == timeh) {

103
src/iss/arch/riscv_hart_msu_vp.h
View File

@ -328,7 +328,7 @@ public:
void disass_output(uint64_t pc, const std::string instr) override {
CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus,
this->reg.icount + cycle_offset);
this->reg.cycle + cycle_offset);
};
iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; }
@ -361,7 +361,7 @@ protected:
uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
@ -371,7 +371,7 @@ protected:
unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
std::unordered_map<std::string, uint64_t> get_symbol_table(std::string name) override { return arch.get_sym_table(name); }
std::unordered_map<std::string, uint64_t> const& get_symbol_table(std::string name) override { return arch.symbol_table; }
riscv_hart_msu_vp<BASE>& arch;
};
@ -393,8 +393,6 @@ protected:
uint64_t minstret_csr{0};
reg_t fault_data;
std::array<vm_info, 2> vm;
uint64_t tohost = tohost_dflt;
uint64_t fromhost = fromhost_dflt;
bool tohost_lower_written = false;
riscv_instrumentation_if instr_if;
@ -557,71 +555,14 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
}
template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
FILE* fp = fopen(name.c_str(), "r");
if(fp) {
std::array<char, 5> buf;
auto n = fread(buf.data(), 1, 4, fp);
fclose(fp);
if(n != 4)
throw std::runtime_error("input file has insufficient size");
buf[4] = 0;
if(strcmp(buf.data() + 1, "ELF") == 0) {
// Create elfio reader
ELFIO::elfio reader;
// Load ELF data
if(!reader.load(name))
throw std::runtime_error("could not process elf file");
// check elf properties
if(reader.get_class() != ELFCLASS32)
if(sizeof(reg_t) == 4)
throw std::runtime_error("wrong elf class in file");
if(reader.get_type() != ET_EXEC)
throw std::runtime_error("wrong elf type in file");
if(reader.get_machine() != EM_RISCV)
throw std::runtime_error("wrong elf machine in file");
auto entry = reader.get_entry();
for(const auto pseg : reader.segments) {
const auto fsize = pseg->get_file_size(); // 0x42c/0x0
const auto seg_data = pseg->get_data();
const auto type = pseg->get_type();
if(type == 1 && fsize > 0) {
auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
if(res != iss::Ok)
CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
}
}
for(const auto sec : reader.sections) {
if(sec->get_name() == ".symtab") {
if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) {
ELFIO::symbol_section_accessor symbols(reader, sec);
auto sym_no = symbols.get_symbols_num();
std::string name;
ELFIO::Elf64_Addr value = 0;
ELFIO::Elf_Xword size = 0;
unsigned char bind = 0;
unsigned char type = 0;
ELFIO::Elf_Half section = 0;
unsigned char other = 0;
for(auto i = 0U; i < sym_no; ++i) {
symbols.get_symbol(i, name, value, size, bind, type, section, other);
if(name == "tohost") {
tohost = value;
} else if(name == "fromhost") {
fromhost = value;
}
}
}
} else if(sec->get_name() == ".tohost") {
tohost = sec->get_address();
fromhost = tohost + 0x40;
}
}
return std::make_pair(entry, true);
}
throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
data);
})) {
return std::make_pair(entry_address, true);
}
throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
return std::make_pair(entry_address, false);
}
template <typename BASE>
@ -671,8 +612,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
}
return res;
} catch(trap_access& ta) {
this->reg.trap_state = (1 << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
} break;
@ -710,8 +653,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
}
return iss::Ok;
} catch(trap_access& ta) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
}
@ -841,8 +786,10 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
}
return iss::Ok;
} catch(trap_access& ta) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
}
@ -889,7 +836,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_reg(unsigned
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t& val) {
auto cycle_val = this->reg.icount + cycle_offset;
auto cycle_val = this->reg.cycle + cycle_offset;
if(addr == mcycle) {
val = static_cast<reg_t>(cycle_val);
} else if(addr == mcycleh) {
@ -910,7 +857,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cycle(unsign
mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
}
}
cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around
cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
return iss::Ok;
}
@ -938,7 +885,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_instret(unsi
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t& val) {
uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
if(addr == time) {
val = static_cast<reg_t>(time_val);
} else if(addr == timeh) {

103
src/iss/arch/riscv_hart_mu_p.h
View File

@ -305,7 +305,7 @@ public:
void disass_output(uint64_t pc, const std::string instr) override {
NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus,
this->reg.icount + cycle_offset);
this->reg.cycle + cycle_offset);
};
iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; }
@ -338,7 +338,7 @@ protected:
uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
uint64_t get_total_cycles() override { return arch.reg.cycle + arch.cycle_offset; }
void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }
@ -348,7 +348,7 @@ protected:
unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
std::unordered_map<std::string, uint64_t> get_symbol_table(std::string name) override { return arch.get_sym_table(name); }
std::unordered_map<std::string, uint64_t> const& get_symbol_table(std::string name) override { return arch.symbol_table; }
riscv_hart_mu_p<BASE, FEAT, LOGCAT>& arch;
};
@ -370,8 +370,6 @@ protected:
int64_t instret_offset{0};
uint64_t minstret_csr{0};
reg_t fault_data;
uint64_t tohost = tohost_dflt;
uint64_t fromhost = fromhost_dflt;
bool tohost_lower_written = false;
riscv_instrumentation_if instr_if;
@ -651,71 +649,14 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
template <typename BASE, features_e FEAT, typename LOGCAT>
std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT, LOGCAT>::load_file(std::string name, int type) {
FILE* fp = fopen(name.c_str(), "r");
if(fp) {
std::array<char, 5> buf;
auto n = fread(buf.data(), 1, 4, fp);
fclose(fp);
if(n != 4)
throw std::runtime_error("input file has insufficient size");
buf[4] = 0;
if(strcmp(buf.data() + 1, "ELF") == 0) {
// Create elfio reader
ELFIO::elfio reader;
// Load ELF data
if(!reader.load(name))
throw std::runtime_error("could not process elf file");
// check elf properties
if(reader.get_class() != ELFCLASS32)
if(sizeof(reg_t) == 4)
throw std::runtime_error("wrong elf class in file");
if(reader.get_type() != ET_EXEC)
throw std::runtime_error("wrong elf type in file");
if(reader.get_machine() != EM_RISCV)
throw std::runtime_error("wrong elf machine in file");
auto entry = reader.get_entry();
for(const auto pseg : reader.segments) {
const auto fsize = pseg->get_file_size(); // 0x42c/0x0
const auto seg_data = pseg->get_data();
const auto type = pseg->get_type();
if(type == 1 && fsize > 0) {
auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
if(res != iss::Ok)
CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
}
}
for(const auto sec : reader.sections) {
if(sec->get_name() == ".symtab") {
if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) {
ELFIO::symbol_section_accessor symbols(reader, sec);
auto sym_no = symbols.get_symbols_num();
std::string name;
ELFIO::Elf64_Addr value = 0;
ELFIO::Elf_Xword size = 0;
unsigned char bind = 0;
unsigned char type = 0;
ELFIO::Elf_Half section = 0;
unsigned char other = 0;
for(auto i = 0U; i < sym_no; ++i) {
symbols.get_symbol(i, name, value, size, bind, type, section, other);
if(name == "tohost") {
tohost = value;
} else if(name == "fromhost") {
fromhost = value;
}
}
}
} else if(sec->get_name() == ".tohost") {
tohost = sec->get_address();
fromhost = tohost + 0x40;
}
}
return std::make_pair(entry, true);
}
throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
if(read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64,
[this](uint64_t addr, uint64_t size, const uint8_t* const data) -> iss::status {
return this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, addr, size,
data);
})) {
return std::make_pair(entry_address, true);
}
throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
return std::make_pair(entry_address, false);
}
template <typename BASE, features_e FEAT, typename LOGCAT>
@ -877,8 +818,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, c
}
return res;
} catch(trap_access& ta) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
} break;
@ -905,8 +848,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, c
}
return iss::Ok;
} catch(trap_access& ta) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
}
@ -1045,8 +990,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
}
return iss::Ok;
} catch(trap_access& ta) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
if((access & access_type::DEBUG) == 0) {
this->reg.trap_state = (1UL << 31) | ta.id;
fault_data = ta.addr;
}
return iss::Err;
}
}
@ -1099,7 +1046,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_plain(unsigned addr, reg_
template <typename BASE, features_e FEAT, typename LOGCAT>
iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_cycle(unsigned addr, reg_t& val) {
auto cycle_val = this->reg.icount + cycle_offset;
auto cycle_val = this->reg.cycle + cycle_offset;
if(addr == mcycle) {
val = static_cast<reg_t>(cycle_val);
} else if(addr == mcycleh) {
@ -1119,7 +1066,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_cycle(unsigned addr, reg_
mcycle_csr = (static_cast<uint64_t>(val) << 32) + (mcycle_csr & 0xffffffff);
}
}
cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around
cycle_offset = mcycle_csr - this->reg.cycle; // TODO: relying on wrap-around
return iss::Ok;
}
@ -1150,7 +1097,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_instret(unsigned addr, re
template <typename BASE, features_e FEAT, typename LOGCAT>
iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_time(unsigned addr, reg_t& val) {
uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
uint64_t time_val = this->reg.cycle / (100000000 / 32768 - 1); //-> ~3052;
if(addr == time) {
val = static_cast<reg_t>(time_val);
} else if(addr == timeh) {

4
src/iss/arch/tgc5c.h
View File

@ -189,7 +189,7 @@ struct tgc5c: public arch_if {
uint8_t* get_regs_base_ptr() override;
inline uint64_t get_icount() { return reg.icount; }
inline uint64_t get_icount() { return reg.icount; } //This should not be accessible, only through the instrumentation_if
inline bool should_stop() { return interrupt_sim; }
@ -199,7 +199,7 @@ struct tgc5c: public arch_if {
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; }
inline uint32_t get_last_branch() { return reg.last_branch; } //This should also only be accessible through the instrumentation_if
#pragma pack(push, 1)

8196
src/iss/debugger/csr_names.cpp
View File

File diff suppressed because it is too large Load Diff

55
src/iss/debugger/riscv_target_adapter.h
View File

@ -39,8 +39,6 @@
#include <iss/iss.h>
#include <array>
#include <iostream>
#include <fstream>
#include <memory>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
@ -109,7 +107,7 @@ public:
status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num,
bool& done) override;
bool& done) override;
status current_thread_query(rp_thread_ref& thread) override;
@ -140,15 +138,11 @@ protected:
rp_thread_ref thread_idx;
};
template <typename ARCH>
typename std::enable_if<iss::arch::traits<ARCH>::FLEN!=0, unsigned>::type get_f0_offset() {
template <typename ARCH> typename std::enable_if<iss::arch::traits<ARCH>::FLEN != 0, unsigned>::type get_f0_offset() {
return iss::arch::traits<ARCH>::F0;
}
template <typename ARCH>
typename std::enable_if<iss::arch::traits<ARCH>::FLEN==0, unsigned>::type get_f0_offset() {
return 0;
}
template <typename ARCH> typename std::enable_if<iss::arch::traits<ARCH>::FLEN == 0, unsigned>::type get_f0_offset() { return 0; }
template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
thread_idx = thread;
@ -197,14 +191,14 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::
auto start_reg = arch::traits<ARCH>::X0;
for(size_t i = 0; i < 33; ++i) {
if(i < arch::traits<ARCH>::RFS || i == arch::traits<ARCH>::PC) {
auto reg_no = i<32? start_reg + i: arch::traits<ARCH>::PC;
auto reg_no = i < 32 ? start_reg + i : arch::traits<ARCH>::PC;
unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
for(size_t j = 0; j < arch::traits<ARCH>::XLEN/8; ++j) {
for(size_t j = 0; j < arch::traits<ARCH>::XLEN / 8; ++j) {
data.push_back(*(reg_base + offset + j));
avail.push_back(0xff);
}
} else {
for(size_t j = 0; j < arch::traits<ARCH>::XLEN/8; ++j) {
for(size_t j = 0; j < arch::traits<ARCH>::XLEN / 8; ++j) {
data.push_back(0);
avail.push_back(0);
}
@ -229,15 +223,15 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
auto start_reg = arch::traits<ARCH>::X0;
auto* reg_base = core->get_regs_base_ptr();
auto iter = data.data();
auto iter_end = data.data()+data.size();
auto iter_end = data.data() + data.size();
for(size_t i = 0; i < 33 && iter < iter_end; ++i) {
auto reg_width = arch::traits<ARCH>::XLEN / 8;
if(i < arch::traits<ARCH>::RFS) {
auto offset = traits<ARCH>::reg_byte_offsets[start_reg + i];
std::copy(iter, iter + reg_width, reg_base+offset);
std::copy(iter, iter + reg_width, reg_base + offset);
} else if(i == 32) {
auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
std::copy(iter, iter + reg_width, reg_base+offset);
std::copy(iter, iter + reg_width, reg_base + offset);
}
iter += reg_width;
}
@ -246,7 +240,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
auto reg_width = arch::traits<ARCH>::FLEN / 8;
for(size_t i = 0; i < 32 && iter < iter_end; ++i) {
unsigned offset = traits<ARCH>::reg_byte_offsets[fstart_reg + i];
std::copy(iter, iter + reg_width, reg_base+offset);
std::copy(iter, iter + reg_width, reg_base + offset);
iter += reg_width;
}
}
@ -255,7 +249,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
template <typename ARCH>
status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
if(reg_no <csr_offset) {
if(reg_no < csr_offset) {
// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
// arch::traits<ARCH>::reg_e>(reg_no))/8;
auto* reg_base = core->get_regs_base_ptr();
@ -349,7 +343,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type
auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
<< std::dec;
<< std::dec;
CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Ok;
}
@ -379,7 +373,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_t
template <typename ARCH>
status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
std::function<void(unsigned)> stop_callback) {
std::function<void(unsigned)> stop_callback) {
auto* reg_base = core->get_regs_base_ptr();
auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
@ -398,17 +392,20 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std
oss << " <architectureriscv:rv64</architecture>\n";
oss << " <feature name=\"org.gnu.gdb.riscv.cpu\">\n";
auto reg_base_num = iss::arch::traits<ARCH>::X0;
for(auto i = 0U; i<iss::arch::traits<ARCH>::RFS; ++i) {
oss << " <reg name=\"x" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i] << "\" type=\"int\" regnum=\"" << i << "\"/>\n";
for(auto i = 0U; i < iss::arch::traits<ARCH>::RFS; ++i) {
oss << " <reg name=\"x" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i]
<< "\" type=\"int\" regnum=\"" << i << "\"/>\n";
}
oss << " <reg name=\"pc\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[iss::arch::traits<ARCH>::PC] << "\" type=\"code_ptr\" regnum=\"" << 32U << "\"/>\n";
oss << " <reg name=\"pc\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[iss::arch::traits<ARCH>::PC]
<< "\" type=\"code_ptr\" regnum=\"" << 32U << "\"/>\n";
oss << " </feature>\n";
if(iss::arch::traits<ARCH>::FLEN > 0) {
oss << " <feature name=\"org.gnu.gdb.riscv.fpu\">\n";
auto reg_base_num = get_f0_offset<ARCH>();
auto type = iss::arch::traits<ARCH>::FLEN==32?"ieee_single":"riscv_double";
for(auto i = 0U; i<32; ++i) {
oss << " <reg name=\"f" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i] << "\" type=\""<<type<<"\" regnum=\"" << i+33 << "\"/>\n";
auto reg_base_num = get_f0_offset<ARCH>();
auto type = iss::arch::traits<ARCH>::FLEN == 32 ? "ieee_single" : "riscv_double";
for(auto i = 0U; i < 32; ++i) {
oss << " <reg name=\"f" << i << "\" bitsize=\"" << iss::arch::traits<ARCH>::reg_bit_widths[reg_base_num + i]
<< "\" type=\"" << type << "\" regnum=\"" << i + 33 << "\"/>\n";
}
oss << " <reg name=\"fcsr\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"103\" type int/>\n";
oss << " <reg name=\"fflags\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" regnum=\"101\" type int/>\n";
@ -420,16 +417,18 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std
std::vector<uint8_t> avail;
data.resize(sizeof(typename traits<ARCH>::reg_t));
avail.resize(sizeof(typename traits<ARCH>::reg_t));
for(auto i = 0U; i<4096; ++i) {
for(auto i = 0U; i < 4096; ++i) {
typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, i);
std::fill(avail.begin(), avail.end(), 0xff);
auto res = core->read(a, data.size(), data.data());
if(res == iss::Ok) {
oss << " <reg name=\"" << get_csr_name(i) << "\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN << "\" type=\"int\" regnum=\"" << (i + csr_offset) << "\"/>\n";
oss << " <reg name=\"" << get_csr_name(i) << "\" bitsize=\"" << iss::arch::traits<ARCH>::XLEN
<< "\" type=\"int\" regnum=\"" << (i + csr_offset) << "\"/>\n";
}
}
oss << " </feature>\n";
oss << "</target>\n";
csr_xml = oss.str();
}
out_buf = csr_xml;
return Ok;

17
src/main.cpp
View File

@ -141,7 +141,10 @@ int main(int argc, char* argv[]) {
std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as<unsigned>(), &semihosting_cb);
}
if(!cpu) {
CPPLOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
auto list = f.get_names();
std::sort(std::begin(list), std::end(list));
CPPLOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << "\n"
<< "Available implementations (core|platform|backend):\n - " << util::join(list, "\n - ") << std::endl;
return 127;
}
if(!vm) {
@ -203,13 +206,21 @@ int main(int argc, char* argv[]) {
if(clim.count("elf"))
for(std::string input : clim["elf"].as<std::vector<std::string>>()) {
auto start_addr = vm->get_arch()->load_file(input);
if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
if(start_addr.second)
start_address = start_addr.first;
else {
LOG(ERR) << "Error occured while loading file " << input << std::endl;
return 1;
}
}
for(std::string input : args) {
auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
if(start_addr.second)
start_address = start_addr.first;
else {
LOG(ERR) << "Error occured while loading file " << input << std::endl;
return 1;
}
}
if(clim.count("reset")) {
auto str = clim["reset"].as<std::string>();

55
src/sysc/core_complex.cpp
View File

@ -42,7 +42,6 @@
#include <iss/plugin/loader.h>
#endif
#include "sc_core_adapter_if.h"
#include <iss/arch/tgc_mapper.h>
#include <scc/report.h>
#include <util/ities.h>
#include <iostream>
@ -208,8 +207,7 @@ core_complex<BUSWIDTH>::core_complex(sc_module_name const& name)
}
#endif
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::init() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::init() {
trc = new core_trace();
ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
auto lut_entry = fetch_lut.getEntry(start);
@ -254,19 +252,16 @@ void core_complex<BUSWIDTH>::init() {
#endif
}
template <unsigned int BUSWIDTH>
core_complex<BUSWIDTH>::~core_complex() {
template <unsigned int BUSWIDTH> core_complex<BUSWIDTH>::~core_complex() {
delete cpu;
delete trc;
for(auto* p : plugin_list)
delete p;
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::trace(sc_trace_file* trf) const {}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::before_end_of_elaboration() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::before_end_of_elaboration() {
SCCDEBUG(SCMOD) << "instantiating iss::arch::tgf with " << GET_PROP_VALUE(backend) << " backend";
// cpu = scc::make_unique<core_wrapper>(this);
cpu = new core_wrapper(this);
@ -307,8 +302,7 @@ void core_complex<BUSWIDTH>::before_end_of_elaboration() {
}
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::start_of_simulation() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::start_of_simulation() {
// quantum_keeper.reset();
if(GET_PROP_VALUE(elf_file).size() > 0) {
istringstream is(GET_PROP_VALUE(elf_file));
@ -331,8 +325,7 @@ void core_complex<BUSWIDTH>::start_of_simulation() {
}
}
template <unsigned int BUSWIDTH>
bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_str) {
if(trc->m_db == nullptr)
return false;
if(trc->tr_handle.is_active())
@ -346,8 +339,7 @@ bool core_complex<BUSWIDTH>::disass_output(uint64_t pc, const std::string instr_
return true;
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::forward() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::forward() {
#ifndef CWR_SYSTEMC
set_clock_period(clk_i.read());
#else
@ -356,30 +348,24 @@ void core_complex<BUSWIDTH>::forward() {
#endif
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::set_clock_period(sc_core::sc_time period) {
curr_clk = period;
if(period == SC_ZERO_TIME)
cpu->set_interrupt_execution(true);
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::rst_cb() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::rst_cb() {
if(rst_i.read())
cpu->set_interrupt_execution(true);
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::local_irq_cb() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::local_irq_cb() {
for(auto i = 0U; i < local_irq_i.size(); ++i) {
if(local_irq_i[i].event()) {
cpu->local_irq(16 + i, local_irq_i[i].read());
@ -387,8 +373,7 @@ void core_complex<BUSWIDTH>::local_irq_cb() {
}
}
template <unsigned int BUSWIDTH>
void core_complex<BUSWIDTH>::run() {
template <unsigned int BUSWIDTH> void core_complex<BUSWIDTH>::run() {
wait(SC_ZERO_TIME); // separate from elaboration phase
do {
wait(SC_ZERO_TIME);
@ -406,8 +391,7 @@ void core_complex<BUSWIDTH>::run() {
sc_stop();
}
template <unsigned int BUSWIDTH>
bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) {
auto& dmi_lut = is_fetch ? fetch_lut : read_lut;
auto lut_entry = dmi_lut.getEntry(addr);
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
@ -465,8 +449,7 @@ bool core_complex<BUSWIDTH>::read_mem(uint64_t addr, unsigned length, uint8_t* c
}
}
template <unsigned int BUSWIDTH>
bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uint8_t* const data) {
auto lut_entry = write_lut.getEntry(addr);
if(lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
auto offset = addr - lut_entry.get_start_address();
@ -514,8 +497,7 @@ bool core_complex<BUSWIDTH>::write_mem(uint64_t addr, unsigned length, const uin
}
}
template <unsigned int BUSWIDTH>
bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) {
tlm::tlm_generic_payload gp;
gp.set_command(tlm::TLM_READ_COMMAND);
gp.set_address(addr);
@ -525,8 +507,7 @@ bool core_complex<BUSWIDTH>::read_mem_dbg(uint64_t addr, unsigned length, uint8_
return dbus->transport_dbg(gp) == length;
}
template <unsigned int BUSWIDTH>
bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
template <unsigned int BUSWIDTH> bool core_complex<BUSWIDTH>::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) {
write_buf.resize(length);
std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
tlm::tlm_generic_payload gp;

23
src/sysc/core_complex.h
View File

@ -33,10 +33,10 @@
#ifndef _SYSC_CORE_COMPLEX_H_
#define _SYSC_CORE_COMPLEX_H_
#include <scc/signal_opt_ports.h>
#include <scc/tick2time.h>
#include <scc/traceable.h>
#include <scc/utilities.h>
#include <scc/signal_opt_ports.h>
#include <tlm/scc/initiator_mixin.h>
#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
#ifdef CWR_SYSTEMC
@ -71,28 +71,27 @@ struct core_complex_if {
virtual ~core_complex_if() = default;
virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) =0;
virtual bool read_mem(uint64_t addr, unsigned length, uint8_t* const data, bool is_fetch) = 0;
virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) =0;
virtual bool write_mem(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) =0;
virtual bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t* const data) = 0;
virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) =0;
virtual bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t* const data) = 0;
virtual bool disass_output(uint64_t pc, const std::string instr) =0;
virtual bool disass_output(uint64_t pc, const std::string instr) = 0;
virtual unsigned get_last_bus_cycles() =0;
virtual unsigned get_last_bus_cycles() = 0;
//! Allow quantum keeper handling
virtual void sync(uint64_t) =0;
virtual void sync(uint64_t) = 0;
virtual char const* hier_name() = 0;
scc::sc_in_opt<uint64_t> mtime_i{"mtime_i"};
};
template <unsigned int BUSWIDTH = scc::LT>
class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
template <unsigned int BUSWIDTH = scc::LT> class core_complex : public sc_core::sc_module, public scc::traceable, public core_complex_if {
public:
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<BUSWIDTH>> ibus{"ibus"};
@ -208,9 +207,7 @@ public:
void set_clock_period(sc_core::sc_time period);
char const* hier_name() override {
return name();
}
char const* hier_name() override { return name(); }
protected:
void before_end_of_elaboration() override;

4
src/sysc/register_tgc_c.cpp
View File

@ -62,12 +62,12 @@ using namespace sysc;
volatile std::array<bool, 2> tgc_init = {
iss_factory::instance().register_creator("tgc5c|m_p|llvm",
[](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
}),
iss_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
})};

6
src/sysc/sc_core_adapter.h
View File

@ -55,8 +55,8 @@ public:
s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2)
<< (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount + this->cycle_offset << "]";
SCCDEBUG(owner->hier_name()) << "disass: "
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
<< std::setfill(' ') << std::left << instr << s.str();
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t"
<< std::setw(40) << std::setfill(' ') << std::left << instr << s.str();
}
};
@ -113,7 +113,7 @@ public:
iss::status read_csr(unsigned addr, reg_t& val) override {
if((addr == iss::arch::time || addr == iss::arch::timeh)) {
uint64_t time_val = owner->mtime_i.get_interface()? owner->mtime_i.read():0;
uint64_t time_val = owner->mtime_i.get_interface() ? owner->mtime_i.read() : 0;
if(addr == iss::arch::time) {
val = static_cast<reg_t>(time_val);
} else if(addr == iss::arch::timeh) {

96
src/vm/asmjit/vm_tgc5c.cpp
View File

@ -1421,23 +1421,21 @@ private:
}
else{
if(rd!=0){
{
auto label_then = cc.newLabel();
auto label_merge = cc.newLabel();
auto tmp_reg = get_reg_for(cc, 1);
auto label_then11 = cc.newLabel();
auto label_merge11 = cc.newLabel();
auto tmp_reg11 = get_reg(cc, 8, false);
cmp(cc, gen_ext(cc,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (int16_t)sext<12>(imm));
cc.jl(label_then);
mov(cc, tmp_reg,0);
cc.jmp(label_merge);
cc.bind(label_then);
mov(cc, tmp_reg,1);
cc.bind(label_merge);
cc.jl(label_then11);
mov(cc, tmp_reg11,0);
cc.jmp(label_merge11);
cc.bind(label_then11);
mov(cc, tmp_reg11, 1);
cc.bind(label_merge11);
mov(cc, get_ptr_for(jh, traits::X0+ rd),
gen_ext(cc, tmp_reg
gen_ext(cc, tmp_reg11
, 32, false)
);
}
}
}
auto returnValue = CONT;
@ -1484,22 +1482,20 @@ private:
}
else{
if(rd!=0){
{
auto label_then = cc.newLabel();
auto label_merge = cc.newLabel();
auto tmp_reg = get_reg_for(cc, 1);
auto label_then12 = cc.newLabel();
auto label_merge12 = cc.newLabel();
auto tmp_reg12 = get_reg(cc, 8, false);
cmp(cc, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)));
cc.jb(label_then);
mov(cc, tmp_reg,0);
cc.jmp(label_merge);
cc.bind(label_then);
mov(cc, tmp_reg,1);
cc.bind(label_merge);
cc.jb(label_then12);
mov(cc, tmp_reg12,0);
cc.jmp(label_merge12);
cc.bind(label_then12);
mov(cc, tmp_reg12, 1);
cc.bind(label_merge12);
mov(cc, get_ptr_for(jh, traits::X0+ rd),
gen_ext(cc, tmp_reg
gen_ext(cc, tmp_reg12
, 32, false)
);
}
}
}
auto returnValue = CONT;
@ -1992,24 +1988,22 @@ private:
}
else{
if(rd!=0){
{
auto label_then = cc.newLabel();
auto label_merge = cc.newLabel();
auto tmp_reg = get_reg_for(cc, 1);
auto label_then13 = cc.newLabel();
auto label_merge13 = cc.newLabel();
auto tmp_reg13 = get_reg(cc, 8, false);
cmp(cc, gen_ext(cc,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(cc,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true));
cc.jl(label_then);
mov(cc, tmp_reg,0);
cc.jmp(label_merge);
cc.bind(label_then);
mov(cc, tmp_reg,1);
cc.bind(label_merge);
cc.jl(label_then13);
mov(cc, tmp_reg13,0);
cc.jmp(label_merge13);
cc.bind(label_then13);
mov(cc, tmp_reg13, 1);
cc.bind(label_merge13);
mov(cc, get_ptr_for(jh, traits::X0+ rd),
gen_ext(cc, tmp_reg
gen_ext(cc, tmp_reg13
, 32, false)
);
}
}
}
auto returnValue = CONT;
@ -2056,22 +2050,20 @@ private:
}
else{
if(rd!=0){
{
auto label_then = cc.newLabel();
auto label_merge = cc.newLabel();
auto tmp_reg = get_reg_for(cc, 1);
auto label_then14 = cc.newLabel();
auto label_merge14 = cc.newLabel();
auto tmp_reg14 = get_reg(cc, 8, false);
cmp(cc, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2));
cc.jb(label_then);
mov(cc, tmp_reg,0);
cc.jmp(label_merge);
cc.bind(label_then);
mov(cc, tmp_reg,1);
cc.bind(label_merge);
cc.jb(label_then14);
mov(cc, tmp_reg14,0);
cc.jmp(label_merge14);
cc.bind(label_then14);
mov(cc, tmp_reg14, 1);
cc.bind(label_merge14);
mov(cc, get_ptr_for(jh, traits::X0+ rd),
gen_ext(cc, tmp_reg
gen_ext(cc, tmp_reg14
, 32, false)
);
}
}
}
auto returnValue = CONT;
@ -2511,10 +2503,10 @@ private:
gen_instr_prologue(jh);
cc.comment("//behavior:");
/*generate behavior*/
InvokeNode* call_wait;
InvokeNode* call_wait_15;
jh.cc.comment("//call_wait");
jh.cc.invoke(&call_wait, &wait, FuncSignature::build<void, int32_t>());
setArg(call_wait, 0, 1);
jh.cc.invoke(&call_wait_15, &wait, FuncSignature::build<void, int32_t>());
setArg(call_wait_15, 0, 1);
auto returnValue = CONT;
gen_sync(jh, POST_SYNC, 41);
@ -4830,6 +4822,7 @@ void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
cmp(cc, current_trap_state, 0);
cc.jne(jh.trap_entry);
cc.inc(get_ptr_for(jh, traits::ICOUNT));
cc.inc(get_ptr_for(jh, traits::CYCLE));
}
template <typename ARCH>
void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
@ -4875,6 +4868,7 @@ inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t
auto tmp1 = get_reg_for(cc, traits::TRAP_STATE);
mov(cc, tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
mov(cc, get_ptr_for(jh, traits::TRAP_STATE), tmp1);
cc.jmp(jh.trap_entry);
}
template <typename ARCH>
template <typename T, typename>

51
src/vm/fp_functions.cpp
View File

@ -203,8 +203,8 @@ uint32_t fclass_s(uint32_t v1) {
uA.f = a;
uiA = uA.ui;
uint_fast16_t infOrNaN = expF32UI(uiA) == 0xFF;
uint_fast16_t subnormalOrZero = expF32UI(uiA) == 0;
bool infOrNaN = expF32UI(uiA) == 0xFF;
bool subnormalOrZero = expF32UI(uiA) == 0;
bool sign = signF32UI(uiA);
bool fracZero = fracF32UI(uiA) == 0;
bool isNaN = isNaNF32UI(uiA);
@ -217,9 +217,13 @@ uint32_t fclass_s(uint32_t v1) {
}
uint32_t fconv_d2f(uint64_t v1, uint8_t mode) {
bool isNan = isNaNF64UI(v1);
bool isSNaN = softfloat_isSigNaNF64UI(v1);
softfloat_roundingMode = rmm_map.at(mode);
bool nan = (v1 & defaultNaNF64UI) == defaultNaNF64UI;
if(nan) {
softfloat_exceptionFlags = 0;
if(isNan) {
if(isSNaN)
softfloat_raiseFlags(softfloat_flag_invalid);
return defaultNaNF32UI;
} else {
float32_t res = f64_to_f32(float64_t{v1});
@ -228,11 +232,11 @@ uint32_t fconv_d2f(uint64_t v1, uint8_t mode) {
}
uint64_t fconv_f2d(uint32_t v1, uint8_t mode) {
bool nan = (v1 & defaultNaNF32UI) == defaultNaNF32UI;
if(nan) {
bool infOrNaN = expF32UI(v1) == 0xFF;
bool subnormalOrZero = expF32UI(v1) == 0;
if(infOrNaN || subnormalOrZero) {
return defaultNaNF64UI;
} else {
softfloat_roundingMode = rmm_map.at(mode);
float64_t res = f32_to_f64(float32_t{v1});
return res.v;
}
@ -312,22 +316,23 @@ uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) {
}
uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
float64_t v1f{v1};
softfloat_exceptionFlags = 0;
float64_t r;
switch(op) {
case 0: { // l->d, fp to int32
case 0: { // l from d
int64_t res = f64_to_i64(v1f, rmm_map.at(mode), true);
return (uint64_t)res;
}
case 1: { // lu->s
case 1: { // lu from d
uint64_t res = f64_to_ui64(v1f, rmm_map.at(mode), true);
return res;
}
case 2: // s->l
case 2: // d from l
r = i64_to_f64(v1);
return r.v;
case 3: // s->lu
case 3: // d from lu
r = ui64_to_f64(v1);
return r.v;
}
@ -335,12 +340,24 @@ uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
}
uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode) {
// op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
uint64_t F64_SIGN = 1ULL << 63;
switch(op) {
case 0: // FMADD_D
break;
case 1: // FMSUB_D
v3 ^= F64_SIGN;
break;
case 2: // FNMADD_D
v1 ^= F64_SIGN;
v3 ^= F64_SIGN;
break;
case 3: // FNMSUB_D
v1 ^= F64_SIGN;
break;
}
softfloat_roundingMode = rmm_map.at(mode);
softfloat_exceptionFlags = 0;
float64_t res = softfloat_mulAddF64(v1, v2, v3, op & 0x1);
if(op > 1)
res.v ^= 1ULL << 63;
float64_t res = softfloat_mulAddF64(v1, v2, v3, 0);
return res.v;
}
@ -376,8 +393,8 @@ uint64_t fclass_d(uint64_t v1) {
uA.f = a;
uiA = uA.ui;
uint_fast16_t infOrNaN = expF64UI(uiA) == 0x7FF;
uint_fast16_t subnormalOrZero = expF64UI(uiA) == 0;
bool infOrNaN = expF64UI(uiA) == 0x7FF;
bool subnormalOrZero = expF64UI(uiA) == 0;
bool sign = signF64UI(uiA);
bool fracZero = fracF64UI(uiA) == 0;
bool isNaN = isNaNF64UI(uiA);

3
src/vm/interp/vm_tgc5c.cpp
View File

@ -275,9 +275,6 @@ template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
volatile CODE_WORD x = insn;
insn = 2 * x;
}
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
// according to
// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
#ifdef __GCC__

22
src/vm/llvm/vm_tgc5c.cpp
View File

@ -1490,7 +1490,7 @@ private:
),
this->gen_const(8,1),
this->gen_const(8,0),
1), 32),
8), 32),
get_reg_ptr(rd + traits::X0), false);
}
}
@ -1543,7 +1543,7 @@ private:
),
this->gen_const(8,1),
this->gen_const(8,0),
1), 32),
8), 32),
get_reg_ptr(rd + traits::X0), false);
}
}
@ -2057,7 +2057,7 @@ private:
,
this->gen_const(8,1),
this->gen_const(8,0),
1), 32),
8), 32),
get_reg_ptr(rd + traits::X0), false);
}
}
@ -2110,7 +2110,7 @@ private:
,
this->gen_const(8,1),
this->gen_const(8,0),
1), 32),
8), 32),
get_reg_ptr(rd + traits::X0), false);
}
}
@ -2553,11 +2553,10 @@ private:
this->gen_instr_prologue();
/*generate behavior*/
auto wait_arg0 = this->gen_const(8,1);
std::vector<Value*> wait_args{
wait_arg0
std::vector<Value*> wait_231_args{
this->gen_ext(this->gen_const(8,1), 32)
};
this->builder.CreateCall(this->mod->getFunction("wait"), wait_args);
this->builder.CreateCall(this->mod->getFunction("wait"), wait_231_args);
bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
auto returnValue = std::make_tuple(CONT,bb);
@ -2719,7 +2718,7 @@ private:
csr,
this->builder.CreateAnd(
xrd,
this->builder.CreateNeg(xrs1))
this->builder.CreateNot(xrs1))
);
}
if(rd!=0) {
@ -4898,7 +4897,7 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
get_reg_ptr(traits::PC), true);
this->builder.CreateStore(
@ -4973,6 +4972,7 @@ template <typename ARCH>
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
this->builder.CreateBr(this->trap_blk);
}
template <typename ARCH>
@ -5075,4 +5075,4 @@ volatile std::array<bool, 2> dummy = {
};
}
}
// clang-format on
// clang-format on

236
src/vm/tcc/vm_tgc5c.cpp
View File

@ -81,16 +81,18 @@ protected:
using vm_base<ARCH>::get_reg_ptr;
using this_class = vm_impl<ARCH>;
using compile_ret_t = std::tuple<continuation_e>;
using compile_ret_t = continuation_e;
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
inline const char *name(size_t index){return traits::reg_aliases.at(index);}
void add_prologue(tu_builder& tu) override;
void setup_module(std::string m) override {
super::setup_module(m);
}
compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
compile_ret_t gen_single_inst_behavior(virt_addr_t &,tu_builder&) override;
void gen_trap_behavior(tu_builder& tu) override;
@ -352,7 +354,7 @@ private:
tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)imm),32));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,0);
@ -387,7 +389,7 @@ private:
tu.store(rd + traits::X0, tu.constant((uint32_t)(PC+(int32_t)imm),32));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,1);
@ -432,7 +434,7 @@ private:
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
}
}
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,2);
@ -474,18 +476,22 @@ private:
tu.open_if(tu.urem(
new_pc,
tu.constant(static_cast<uint32_t>(traits:: INSTR_ALIGNMENT),32)));
{
this->gen_set_tval(tu, new_pc);
this->gen_raise_trap(tu, 0, 0);
}
tu.open_else();
{
if(rd!=0) {
tu.store(rd + traits::X0, tu.constant((uint32_t)(PC+4),32));
}
auto PC_val_v = tu.assignment("PC_val", new_pc,32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 2));
}
tu.close_scope();
}
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,3);
@ -521,6 +527,7 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_EQ,
tu.load(rs1 + traits::X0, 0),
tu.load(rs2 + traits::X0, 0)));
{
auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
this->gen_raise_trap(tu, 0, 0);
@ -530,9 +537,10 @@ private:
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
}
}
tu.close_scope();
}
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,4);
@ -568,6 +576,7 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
tu.load(rs1 + traits::X0, 0),
tu.load(rs2 + traits::X0, 0)));
{
auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
this->gen_raise_trap(tu, 0, 0);
@ -577,9 +586,10 @@ private:
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
}
}
tu.close_scope();
}
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,5);
@ -615,6 +625,7 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_SLT,
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
tu.ext(tu.load(rs2 + traits::X0, 0),32,true)));
{
auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
this->gen_raise_trap(tu, 0, 0);
@ -624,9 +635,10 @@ private:
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
}
}
tu.close_scope();
}
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,6);
@ -662,6 +674,7 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_SGE,
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
tu.ext(tu.load(rs2 + traits::X0, 0),32,true)));
{
auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
this->gen_raise_trap(tu, 0, 0);
@ -671,9 +684,10 @@ private:
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
}
}
tu.close_scope();
}
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,7);
@ -709,6 +723,7 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_ULT,
tu.load(rs1 + traits::X0, 0),
tu.load(rs2 + traits::X0, 0)));
{
auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
this->gen_raise_trap(tu, 0, 0);
@ -718,9 +733,10 @@ private:
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
}
}
tu.close_scope();
}
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,8);
@ -756,6 +772,7 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_UGE,
tu.load(rs1 + traits::X0, 0),
tu.load(rs2 + traits::X0, 0)));
{
auto new_pc = (uint32_t)(PC+(int16_t)sext<13>(imm));
if(new_pc%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_set_tval(tu, new_pc);
this->gen_raise_trap(tu, 0, 0);
@ -765,9 +782,10 @@ private:
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
}
}
tu.close_scope();
}
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,9);
@ -807,7 +825,7 @@ private:
tu.store(rd + traits::X0, tu.ext(res,32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,10);
@ -847,7 +865,7 @@ private:
tu.store(rd + traits::X0, tu.ext(res,32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,11);
@ -887,7 +905,7 @@ private:
tu.store(rd + traits::X0, tu.ext(res,32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,12);
@ -927,7 +945,7 @@ private:
tu.store(rd + traits::X0, tu.ext(res,32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,13);
@ -967,7 +985,7 @@ private:
tu.store(rd + traits::X0, tu.ext(res,32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,14);
@ -1004,7 +1022,7 @@ private:
tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0),8,false));
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,15);
@ -1041,7 +1059,7 @@ private:
tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0),16,false));
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,16);
@ -1078,7 +1096,7 @@ private:
tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0),32,false));
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,17);
@ -1116,7 +1134,7 @@ private:
tu.constant((int16_t)sext<12>(imm),16))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,18);
@ -1154,7 +1172,7 @@ private:
tu.constant((int16_t)sext<12>(imm),16))), tu.constant(1,8),tu.constant(0,8)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,19);
@ -1192,7 +1210,7 @@ private:
tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))), tu.constant(1,8),tu.constant(0,8)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,20);
@ -1230,7 +1248,7 @@ private:
tu.constant((uint32_t)((int16_t)sext<12>(imm)),32)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,21);
@ -1268,7 +1286,7 @@ private:
tu.constant((uint32_t)((int16_t)sext<12>(imm)),32)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,22);
@ -1306,7 +1324,7 @@ private:
tu.constant((uint32_t)((int16_t)sext<12>(imm)),32)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,23);
@ -1344,7 +1362,7 @@ private:
tu.constant(shamt,8)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,24);
@ -1382,7 +1400,7 @@ private:
tu.constant(shamt,8)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,25);
@ -1420,7 +1438,7 @@ private:
tu.constant(shamt,8))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,26);
@ -1458,7 +1476,7 @@ private:
tu.load(rs2 + traits::X0, 0))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,27);
@ -1496,7 +1514,7 @@ private:
tu.load(rs2 + traits::X0, 0))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,28);
@ -1536,7 +1554,7 @@ private:
tu.constant((static_cast<uint32_t>(traits:: XLEN)-1),64)))));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,29);
@ -1574,7 +1592,7 @@ private:
tu.ext(tu.load(rs2 + traits::X0, 0),32,true)), tu.constant(1,8),tu.constant(0,8)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,30);
@ -1612,7 +1630,7 @@ private:
tu.load(rs2 + traits::X0, 0)), tu.constant(1,8),tu.constant(0,8)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,31);
@ -1650,7 +1668,7 @@ private:
tu.load(rs2 + traits::X0, 0)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,32);
@ -1690,7 +1708,7 @@ private:
tu.constant((static_cast<uint32_t>(traits:: XLEN)-1),64)))));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,33);
@ -1730,7 +1748,7 @@ private:
tu.constant((static_cast<uint32_t>(traits:: XLEN)-1),64))))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,34);
@ -1768,7 +1786,7 @@ private:
tu.load(rs2 + traits::X0, 0)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,35);
@ -1806,7 +1824,7 @@ private:
tu.load(rs2 + traits::X0, 0)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,36);
@ -1837,7 +1855,7 @@ private:
tu.open_scope();
this->gen_set_tval(tu, instr);
tu.write_mem(traits::FENCE, static_cast<uint32_t>(traits:: fence), tu.constant((uint8_t)pred<<4|succ,8));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,37);
@ -1863,7 +1881,7 @@ private:
this->gen_set_tval(tu, instr);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
this->gen_raise_trap(tu, 0, 11);
auto returnValue = std::make_tuple(TRAP);
auto returnValue = TRAP;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,38);
@ -1889,7 +1907,7 @@ private:
this->gen_set_tval(tu, instr);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
this->gen_raise_trap(tu, 0, 3);
auto returnValue = std::make_tuple(TRAP);
auto returnValue = TRAP;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,39);
@ -1915,7 +1933,7 @@ private:
this->gen_set_tval(tu, instr);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(NO_JUMP),32));
this->gen_leave_trap(tu, 3);
auto returnValue = std::make_tuple(TRAP);
auto returnValue = TRAP;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,40);
@ -1940,7 +1958,7 @@ private:
tu.open_scope();
this->gen_set_tval(tu, instr);
tu.callf("wait", tu.constant(1,8));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,41);
@ -1981,7 +1999,7 @@ private:
tu.write_mem(traits::CSR, csr, xrs1);
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,42);
@ -2024,7 +2042,7 @@ private:
tu.store(rd + traits::X0, xrd);
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,43);
@ -2067,7 +2085,7 @@ private:
tu.store(rd + traits::X0, xrd);
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,44);
@ -2105,7 +2123,7 @@ private:
tu.store(rd + traits::X0, xrd);
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,45);
@ -2147,7 +2165,7 @@ private:
tu.store(rd + traits::X0, xrd);
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,46);
@ -2189,7 +2207,7 @@ private:
tu.store(rd + traits::X0, xrd);
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,47);
@ -2218,7 +2236,7 @@ private:
tu.open_scope();
this->gen_set_tval(tu, instr);
tu.write_mem(traits::FENCE, static_cast<uint32_t>(traits:: fencei), tu.constant(imm,16));
auto returnValue = std::make_tuple(FLUSH);
auto returnValue = FLUSH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,48);
@ -2257,7 +2275,7 @@ private:
tu.store(rd + traits::X0, tu.ext(res,32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,49);
@ -2298,7 +2316,7 @@ private:
tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,50);
@ -2339,7 +2357,7 @@ private:
tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,51);
@ -2380,7 +2398,7 @@ private:
tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,52);
@ -2417,6 +2435,7 @@ private:
if(rd!=0){ tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
divisor,
tu.constant(0,8)));
{
auto MMIN = ((uint32_t)1)<<(static_cast<uint32_t>(traits:: XLEN)-1);
tu.open_if(tu.logical_and(
tu.icmp(ICmpInst::ICMP_EQ,
@ -2425,18 +2444,25 @@ private:
tu.icmp(ICmpInst::ICMP_EQ,
divisor,
tu.constant(- 1,8))));
{
tu.store(rd + traits::X0, tu.constant(MMIN,32));
}
tu.open_else();
{
tu.store(rd + traits::X0, tu.ext((tu.sdiv(
dividend,
divisor)),32,false));
}
tu.close_scope();
}
tu.open_else();
{
tu.store(rd + traits::X0, tu.constant((uint32_t)- 1,32));
}
tu.close_scope();
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,53);
@ -2471,18 +2497,22 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
tu.load(rs2 + traits::X0, 0),
tu.constant(0,8)));
{
if(rd!=0) {
tu.store(rd + traits::X0, tu.udiv(
tu.load(rs1 + traits::X0, 0),
tu.load(rs2 + traits::X0, 0)));
}
}
tu.open_else();
{
if(rd!=0) {
tu.store(rd + traits::X0, tu.constant((uint32_t)- 1,32));
}
}
tu.close_scope();
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,54);
@ -2517,6 +2547,7 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
tu.load(rs2 + traits::X0, 0),
tu.constant(0,8)));
{
auto MMIN = (uint32_t)1<<(static_cast<uint32_t>(traits:: XLEN)-1);
tu.open_if(tu.logical_and(
tu.icmp(ICmpInst::ICMP_EQ,
@ -2525,23 +2556,30 @@ private:
tu.icmp(ICmpInst::ICMP_EQ,
tu.ext(tu.load(rs2 + traits::X0, 0),32,true),
tu.constant(- 1,8))));
{
if(rd!=0) {
tu.store(rd + traits::X0, tu.constant(0,8));
}
}
tu.open_else();
{
if(rd!=0) {
tu.store(rd + traits::X0, tu.ext((tu.srem(
tu.ext(tu.load(rs1 + traits::X0, 0),32,true),
tu.ext(tu.load(rs2 + traits::X0, 0),32,true))),32,false));
}
}
tu.close_scope();
}
tu.open_else();
{
if(rd!=0) {
tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0));
}
}
tu.close_scope();
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,55);
@ -2576,18 +2614,22 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
tu.load(rs2 + traits::X0, 0),
tu.constant(0,8)));
{
if(rd!=0) {
tu.store(rd + traits::X0, tu.urem(
tu.load(rs1 + traits::X0, 0),
tu.load(rs2 + traits::X0, 0)));
}
}
tu.open_else();
{
if(rd!=0) {
tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0));
}
}
tu.close_scope();
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,56);
@ -2622,7 +2664,7 @@ private:
else{
this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,57);
@ -2654,7 +2696,7 @@ private:
tu.load(rs1+8 + traits::X0, 0),
tu.constant(uimm,8))),32,false),32);
tu.store(rd+8 + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,58);
@ -2686,7 +2728,7 @@ private:
tu.load(rs1+8 + traits::X0, 0),
tu.constant(uimm,8))),32,false),32);
tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2+8 + traits::X0, 0),32,false));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,59);
@ -2723,7 +2765,7 @@ private:
tu.constant((int8_t)sext<6>(imm),8))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,60);
@ -2748,7 +2790,7 @@ private:
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();
this->gen_set_tval(tu, instr);
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,61);
@ -2779,7 +2821,7 @@ private:
auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<12>(imm)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,62);
@ -2814,7 +2856,7 @@ private:
tu.store(rd + traits::X0, tu.constant((uint32_t)((int8_t)sext<6>(imm)),32));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,63);
@ -2847,7 +2889,7 @@ private:
if(rd!=0) {
tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)sext<18>(imm)),32));
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,64);
@ -2881,7 +2923,7 @@ private:
else{
this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,65);
@ -2907,7 +2949,7 @@ private:
tu.open_scope();
this->gen_set_tval(tu, instr);
this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,66);
@ -2937,7 +2979,7 @@ private:
tu.store(rs1+8 + traits::X0, tu.lshr(
tu.load(rs1+8 + traits::X0, 0),
tu.constant(shamt,8)));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,67);
@ -2974,7 +3016,7 @@ private:
tu.constant(64,8))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,68);
@ -3004,7 +3046,7 @@ private:
tu.store(rs1+8 + traits::X0, tu.ext((tu.bitwise_and(
tu.load(rs1+8 + traits::X0, 0),
tu.constant((int8_t)sext<6>(imm),8))),32,false));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,69);
@ -3034,7 +3076,7 @@ private:
tu.store(rd+8 + traits::X0, tu.ext((tu.sub(
tu.load(rd+8 + traits::X0, 0),
tu.load(rs2+8 + traits::X0, 0))),32,false));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,70);
@ -3064,7 +3106,7 @@ private:
tu.store(rd+8 + traits::X0, tu.bitwise_xor(
tu.load(rd+8 + traits::X0, 0),
tu.load(rs2+8 + traits::X0, 0)));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,71);
@ -3094,7 +3136,7 @@ private:
tu.store(rd+8 + traits::X0, tu.bitwise_or(
tu.load(rd+8 + traits::X0, 0),
tu.load(rs2+8 + traits::X0, 0)));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,72);
@ -3124,7 +3166,7 @@ private:
tu.store(rd+8 + traits::X0, tu.bitwise_and(
tu.load(rd+8 + traits::X0, 0),
tu.load(rs2+8 + traits::X0, 0)));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,73);
@ -3154,7 +3196,7 @@ private:
auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<12>(imm)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,74);
@ -3185,11 +3227,13 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_EQ,
tu.load(rs1+8 + traits::X0, 0),
tu.constant(0,8)));
{
auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
}
tu.close_scope();
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,75);
@ -3220,11 +3264,13 @@ private:
tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
tu.load(rs1+8 + traits::X0, 0),
tu.constant(0,8)));
{
auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(KNOWN_JUMP), 2));
}
tu.close_scope();
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,76);
@ -3261,7 +3307,7 @@ private:
tu.constant(nzuimm,8)));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,77);
@ -3297,7 +3343,7 @@ private:
tu.constant(uimm,8))),32,false),32);
tu.store(rd + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false));
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,78);
@ -3332,7 +3378,7 @@ private:
tu.store(rd + traits::X0, tu.load(rs2 + traits::X0, 0));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,79);
@ -3369,7 +3415,7 @@ private:
else{
this->gen_raise_trap(tu, 0, 2);
}
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,80);
@ -3394,7 +3440,7 @@ private:
tu.open_scope();
this->gen_set_tval(tu, instr);
this->gen_raise_trap(tu, 0, 2);
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,81);
@ -3431,7 +3477,7 @@ private:
tu.load(rs2 + traits::X0, 0))),32,false));
}
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,82);
@ -3471,7 +3517,7 @@ private:
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(static_cast<int>(UNKNOWN_JUMP), 2));
}
auto returnValue = std::make_tuple(BRANCH);
auto returnValue = BRANCH;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,83);
@ -3496,7 +3542,7 @@ private:
tu.open_scope();
this->gen_set_tval(tu, instr);
this->gen_raise_trap(tu, 0, 3);
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,84);
@ -3532,7 +3578,7 @@ private:
tu.constant(uimm,8))),32,false),32);
tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2 + traits::X0, 0),32,false));
}
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,85);
@ -3557,7 +3603,7 @@ private:
tu.open_scope();
this->gen_set_tval(tu, instr);
this->gen_raise_trap(tu, 0, static_cast<int32_t>(traits:: RV_CAUSE_ILLEGAL_INSTRUCTION));
auto returnValue = std::make_tuple(CONT);
auto returnValue = CONT;
tu.close_scope();
vm_base<ARCH>::gen_sync(tu, POST_SYNC,86);
@ -3604,8 +3650,8 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
}()) {}
template <typename ARCH>
std::tuple<continuation_e>
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
continuation_e
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, tu_builder& tu) {
// we fetch at max 4 byte, alignment is 2
enum {TRAP_ID=1<<16};
code_word_t instr = 0;
@ -3617,7 +3663,6 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
return ILLEGAL_FETCH;
if (instr == 0x0000006f || (instr&0xffff)==0xa001)
return JUMP_TO_SELF;
++inst_cnt;
uint32_t inst_index = instr_decoder.decode_instr(instr);
compile_func f = nullptr;
if(inst_index < instr_descr.size())
@ -3653,7 +3698,12 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
tu("return *next_pc;");
}
template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
std::ostringstream os;
os << tu.add_reg_ptr("trap_state", arch::traits<ARCH>::TRAP_STATE, this->regs_base_ptr);
os << tu.add_reg_ptr("pending_trap", arch::traits<ARCH>::PENDING_TRAP, this->regs_base_ptr);
tu.add_prologue(os.str());
}
} // namespace tgc5c
template <>