 Eyck Jentzsch
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32e4aa83b8
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use extracted variables
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2021-03-27 09:36:52 +00:00 |
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Eyck Jentzsch
|
78c7064295
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update groovy template to extract used registers
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2021-03-26 08:24:45 +00:00 |
|
Eyck Jentzsch
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b0bcb7febb
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small fixes for robustness and readability
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2021-03-22 22:47:30 +00:00 |
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Eyck Jentzsch
|
4e0f20eba0
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rework abort conditions
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2021-03-17 19:32:57 +00:00 |
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Eyck Jentzsch
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ff3fa19208
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fix RVM description bugs
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2021-03-13 10:46:41 +00:00 |
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Eyck Jentzsch
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80057eef32
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fix RVC description bugs, remove paged fetch
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2021-03-13 10:46:41 +00:00 |
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Eyck Jentzsch
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f4ec21007b
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fix signedness issues
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2021-03-11 16:12:28 +00:00 |
|
Eyck Jentzsch
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768716b064
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fix another missing XLEN
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2021-03-09 11:07:56 +00:00 |
|
Eyck Jentzsch
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bea0dcc387
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update missing XLEN
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2021-03-09 11:03:37 +00:00 |
|
Eyck Jentzsch
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a6691bcd3c
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update generated code with correct sign extension
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2021-03-09 10:21:36 +00:00 |
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Eyck Jentzsch
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c251fe15d5
|
fix desscriptions to conform to ISA spec version 20191213 and TGF-C
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2021-03-07 10:51:00 +00:00 |
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Eyck Jentzsch
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dae8acb8a3
|
checkpoint before refactor
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2021-03-06 07:17:42 +00:00 |
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Eyck Jentzsch
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be0e7db185
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fix templates to comply with CoreDSL2
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2021-03-01 21:07:20 +00:00 |
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Eyck Jentzsch
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9534d58d01
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regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
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2021-03-01 06:26:33 +00:00 |
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Eyck Jentzsch
|
1668df0531
|
regenerated sources and and add opcode enum to headers
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2021-02-23 08:29:31 +00:00 |
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Eyck Jentzsch
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72b09472d5
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update RISC-V descriptions
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2021-02-15 18:01:33 +00:00 |
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Eyck Jentzsch
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34bb8e62ae
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generate working ISS from CoreDSL 2.0
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2021-02-06 14:47:06 +00:00 |
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Eyck Jentzsch
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ab554539e3
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first version of tgf_c based on CoreDSL 2.0
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2020-12-29 08:48:22 +00:00 |
 Stanislaw Kaushanski
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43488676dd
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Update TGF naming convention
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2020-09-11 10:45:44 +02:00 |