DBT-RISE
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DBT-RISE-TGC
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358 Commits

Author SHA1 Message Date
Eyck Jentzsch 83f54b5074 fixes CLICCFG settings 2023-03-11 08:48:03 +01:00
Eyck Jentzsch a83928fd8c fixes CSR/CLIC implementation 2023-03-10 20:40:21 +01:00
Eyck Jentzsch ec55efd322 adds generator changed files 2023-02-17 06:36:34 +01:00
Eyck Jentzsch 8c3709f92a adds generator changed files 2023-02-17 06:29:27 +01:00
Eyck Jentzsch 62c118e501 fixes CSR to match latest fast interrupts spec 2023-01-20 16:21:04 +01:00
Eyck Jentzsch 65dca13b42 fixes WFI miss of interrupt 2023-01-14 17:40:21 +01:00
Eyck Jentzsch 8c701d55c1 adapt to latest changes in SCC 2022-12-05 09:15:48 +01:00
Eyck Jentzsch f585489ff5 fixes pin naming 2022-10-26 17:21:44 +02:00
Eyck Jentzsch 7113683ee0 moves pending interrupt check before handling trap thus saving 1 cycle 2022-10-15 10:47:35 +02:00
Eyck Jentzsch 1a0fc4bd5d fixes wrong mcounteren in M-mode only priv wrapper 2022-10-10 08:59:27 +02:00
Eyck Jentzsch 40d1966e9a fixes pending irq within irq hander behavior 2022-10-08 11:20:52 +02:00
Eyck Jentzsch a977200284 cleans up priv wrappers 2022-10-05 08:58:57 +02:00
Eyck Jentzsch 6ba7c82f80 fixes wrapper definitions for hwl cores 2022-09-26 13:31:46 +02:00
Eyck Jentzsch ad7bb28b4c fixes write mask of clic memory mapped registers 2022-09-17 12:15:19 +02:00
Eyck Jentzsch fa7eda0889 fixes wrong check for exception 2022-08-31 11:45:53 +02:00
Eyck Jentzsch 00e02bf565 adds support for different branch types in tracing 2022-08-08 06:30:37 +02:00
Eyck Jentzsch 1ad66a71d8 extends supported break point types 2022-08-06 09:53:24 +02:00
Eyck Jentzsch e60fa3d5e6 adaptes to changes in dbt-rise-core 2022-08-06 09:49:32 +02:00
Eyck Jentzsch 8407f6287f replaces core_complex socket 2022-07-24 20:52:28 +02:00
Eyck Jentzsch 57347ae4d9 fixes cppcheck flagged issues 2022-07-23 13:49:10 +02:00
Eyck Jentzsch 4876f18ba9 adds windows compatibility fixes 2022-07-18 11:43:42 +02:00
Eyck Jentzsch a53ee42e13 updates TGC_C according to CoreDSL description update 2022-07-12 22:34:22 +02:00
Eyck Jentzsch 12ccfc055a updates generate tgc_c definition 2022-07-11 22:58:10 +02:00
Eyck Jentzsch feaa49d367 removes decoder again as there is some issue 2022-06-20 00:39:11 +02:00
Eyck Jentzsch f096b15dbd factors decoder into separate component 2022-06-19 13:17:31 +02:00
Eyck Jentzsch 076b5a39ad fix class naming 2022-06-02 08:30:49 +02:00
Eyck Jentzsch f40ab41899 fix left-over from layout refactoring 2022-06-02 08:30:02 +02:00
Eyck Jentzsch 31fb51de95 update tgc_c generated code 2022-05-30 22:15:44 +02:00
Eyck Jentzsch 1c90fe765d Merge remote-tracking branch 'origin/Trace_enhancement' into develop 2022-05-30 14:18:09 +02:00
Eyck Jentzsch 52ed8b81a6 fixed template to work with previous code generator 2022-05-30 14:08:02 +02:00
Eyck Jentzsch 0703a0a845 update tgc-mapper 2022-05-30 07:45:32 +02:00
Eyck Jentzsch 0c542d42aa separate generated sources 2022-05-21 12:48:28 +02:00
Eyck Jentzsch 966d1616c5 change source code to unified layout 2022-05-21 11:55:24 +02:00
Eyck-Alexander Jentzsch 1720bd4aaa adds support for compressed instructions 2022-05-20 15:17:58 +02:00
Eyck Jentzsch df16378605 update template for changed code generator 2022-05-18 19:10:34 +02:00
Eyck Jentzsch 1438f0f373 add backannotation to pc trace plugin 2022-05-17 15:29:04 +02:00
Eyck Jentzsch 766f3ba9ee fix assertion in compressed pctrace writer 2022-05-13 12:38:12 +02:00
Eyck Jentzsch e382217e04 update vm_tgc_c due reworked CoreDSL generator 2022-05-11 18:52:15 +02:00
Eyck Jentzsch 9db4e3fd87 fix assertion 2022-05-10 16:13:21 +02:00
Eyck-Alexander Jentzsch bb658be3b4 Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2022-05-08 15:25:56 +02:00
Eyck-Alexander Jentzsch 6579780dc9 add call column in output 2022-05-08 15:24:26 +02:00
Eyck Jentzsch e56bc12788 fix non-lz4 build of plugin 2022-05-07 17:27:11 +02:00
Eyck Jentzsch e88f309ea2 add lz4 compression to pctrace 2022-05-07 17:22:06 +02:00
Eyck Jentzsch 03bec27376 implement extended instrumentation interface 2022-04-26 17:14:33 +02:00
Eyck Jentzsch 9d9008a3a2 fix pointer mess 2022-04-26 15:35:17 +02:00
Stanislaw Kaushanski 5f6d462973 check that no interrupts are pending before entering the wfi wait 2022-04-26 13:58:20 +02:00
Eyck Jentzsch a92b84bef4 add code word access for ISS plugins 2022-04-25 14:18:19 +02:00
Eyck Jentzsch c054d75717 update to latest coredsl description 2022-04-10 18:55:44 +02:00
Eyck Jentzsch 8e4e702cb9 Merge remote-tracking branch 'origin/feature/reduced_output' into develop 2022-03-28 14:09:06 +02:00
Eyck-Alexander Jentzsch 58311b37db Merge branch 'feature/reduced_output' of 
https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git into
feature/reduced_output
 2022-03-28 11:16:09 +02:00
Eyck Jentzsch b0cb997009 add TGC_X with DMR 2022-03-26 10:48:21 +01:00
Eyck Jentzsch 30ae743361 add pctrace plugin to iss 2022-03-20 17:41:54 +01:00
Eyck Jentzsch d91f5f9df4 fix compiler warning for reduced number of registers 2022-03-14 15:38:05 +01:00
Eyck Jentzsch 2e670c4d03 change interpreter structure 2022-03-06 15:11:38 +01:00
Eyck Jentzsch 521f40a3d6 refactored interpreter backend structure 2022-03-05 20:59:17 +01:00
Eyck-Alexander Jentzsch 2bba5645c3 adds functionality to reduce the output 2022-02-16 10:13:29 +01:00
Eyck-Alexander Jentzsch 4c363f4073 adds additional functionality by fetching delay information 2022-02-11 11:28:00 +01:00
Eyck Jentzsch ac86f14a54 add tgc_c_xrb_nn to tgc-sim 2022-02-02 21:33:42 +01:00
Eyck Jentzsch 09b0f0d0c8 fix cycle estimation plugin 2022-02-01 21:14:50 +01:00
Eyck Jentzsch 98b418ff43 fix JSON reading 2022-02-01 19:28:11 +01:00
Eyck Jentzsch 059bd0d371 rework cycle estimation 2022-02-01 19:03:45 +01:00
Eyck-Alexander Jentzsch 7578906310 adds coverage plugin 2022-01-31 21:38:18 +01:00
Eyck Jentzsch afe8905ac9 fix else-ambiguity in CoreDSL description 2022-01-31 20:30:46 +01:00
Eyck-Alexander Jentzsch ecc6091d1e cleans up source code to remove clang compiler warnings 2022-01-19 08:01:15 +01:00
Eyck Jentzsch 07d5af1dde fix stand-alone ISS compilation to include all generated cores 2021-11-26 17:56:40 +01:00
Eyck Jentzsch 6f8595759e make tgc-sim include all available ISS 2021-11-25 20:00:27 +01:00
Eyck Jentzsch f90c48e881 adapt to changed define names 2021-11-11 08:33:35 +01:00
Eyck Jentzsch c42e336509 fix proper debug mode handling (#267 & #268) 2021-11-07 17:48:44 +01:00
Stanislaw Kaushanski a89f00da19 fix plugins parameter utilization 2021-11-02 11:03:17 +01:00
Eyck Jentzsch 1616f0ac90 remove deprecated functions 2021-10-30 12:57:08 +02:00
Eyck Jentzsch 334d3fb296 adapt to SCC changes 2021-10-21 22:53:16 +02:00
Eyck Jentzsch eb2ca33e5a remove unused sources 2021-10-12 15:17:56 +02:00
Eyck Jentzsch 0ea4cba1ca add dynamic plugin loading 2021-10-12 14:24:55 +02:00
Eyck Jentzsch 1d13c8196e fix wrong PGMASK usage 2021-10-11 10:40:01 +02:00
Eyck Jentzsch ee6e1d4092 Merge remote-tracking branch 'origin/msvc_compat' into develop 
Conflicts:
	src/sysc/core_complex.cpp
 2021-10-11 09:42:40 +02:00
Eyck Jentzsch c8679fca85 remove MSVC warning 2021-10-10 19:56:33 +02:00
Eyck Jentzsch f0ada1ba8c add MSVC 16 compatibility 2021-10-10 19:06:41 +02:00
Eyck Jentzsch 2f15d9676e fix unaligned instr fetch behavior 2021-09-30 19:27:46 +02:00
Eyck Jentzsch 17ee7b138d update generated TGC-C VM 2021-09-29 00:44:17 +02:00
Eyck Jentzsch 438e598a4a remove clutter from core descriptions, added instr alignment setting 2021-09-29 00:03:11 +02:00
Eyck Jentzsch 174259155d add support for non-compressed ISA 2021-09-23 21:09:52 +02:00
Eyck Jentzsch 65b4db5eca remove mcounteren in M-mode only platform 2021-09-18 11:40:00 +02:00
Eyck Jentzsch 0fd82f1f3c add tgc_d_xrb_mac to SC and C++ ISS 2021-09-04 13:04:34 +02:00
Eyck Jentzsch 09b01af3fa fix find_package use and debug access alignment check 2021-08-26 22:10:27 +02:00
Eyck Jentzsch 2f05083cf0 fix elf loader and pmp check for debug accesses 2021-08-19 10:50:25 +02:00
Eyck Jentzsch e934049dd4 fix inconsistency due to PA adaptation 2021-08-16 17:55:14 +02:00
Eyck Jentzsch 94f796ebdb add install target and PA compatibility 2021-08-16 17:02:31 +02:00
Eyck Jentzsch c8681096be update vm_tgfs_c to match CoreDSL 2021-08-14 10:57:36 +02:00
Eyck Jentzsch 15f46a87db adapt core_complex to use scv-tr (scc commit id a3cde47) 2021-07-27 09:38:05 +02:00
Eyck Jentzsch e68918c2e8 fix instruction decode 2021-07-09 07:37:12 +02:00
Eyck Jentzsch 2f4b5bd9b2 fix detailed behavior of TGC_C 2021-07-06 21:19:36 +02:00
Eyck Jentzsch 23b9741adf refine and fix TGC_C iss to becoem compliant 2021-06-29 11:51:30 +02:00
Eyck Jentzsch 5d8da08ce5 fix linker issue 
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
 2021-06-26 14:30:36 +02:00
Stanislaw Kaushanski a249aea703 getting rid of the error: reference to 'wait' is ambiguous 2021-06-25 13:35:42 +02:00
Eyck Jentzsch e432dd8208 fix handling of exceptions while accessing address spaces 2021-06-07 22:22:36 +02:00
Eyck Jentzsch 8c385647dd remove redundant code from checked in generated sources 2021-05-26 23:06:31 +02:00
Eyck Jentzsch aaceecd5dc fix mu_p platform features and CSRs 2021-05-17 09:20:09 +02:00
Eyck Jentzsch 4b3f5a6b0c add missing change 2021-05-16 16:44:30 +02:00
Eyck Jentzsch d41e1d816a add factory for ISS and use it in main.cpp 2021-05-16 16:44:14 +02:00
Eyck Jentzsch a35974c9f5 make cpu type in core_complex configurable 2021-05-16 15:06:42 +02:00
Eyck Jentzsch 9c456ba8f2 initial version of MU hart 2021-05-14 13:29:39 +02:00
Eyck Jentzsch c57884caee small fix 2021-05-13 16:01:04 +02:00
Eyck Jentzsch cf7b62a3f9 update names 2021-05-13 15:54:48 +02:00
Stanislaw Kaushanski 2f4cfb68dc update to latest SCC 2021-04-07 18:56:46 +02:00
Stanislaw Kaushanski 7009943106 fix wait for interrupt. Adapt for new SCC structure 2021-04-07 17:42:08 +02:00
Eyck Jentzsch 32e4aa83b8 use extracted variables 2021-03-27 09:36:52 +00:00
Eyck Jentzsch 78c7064295 update groovy template to extract used registers 2021-03-26 08:24:45 +00:00
Stanislaw Kaushanski ea3ff3c0cd build with SCV lib 2021-03-23 11:57:47 +01:00
Eyck Jentzsch b0bcb7febb small fixes for robustness and readability 2021-03-22 22:47:30 +00:00
Eyck Jentzsch 51fbc34fb3 change namespace of core complex 2021-03-22 11:57:40 +00:00
Eyck Jentzsch 4e0f20eba0 rework abort conditions 2021-03-17 19:32:57 +00:00
Eyck Jentzsch ff3fa19208 fix RVM description bugs 2021-03-13 10:46:41 +00:00
Eyck Jentzsch 80057eef32 fix RVC description bugs, remove paged fetch 2021-03-13 10:46:41 +00:00
Stanislaw Kaushanski a5186ff88d optional dependency to TGF_B_src target 2021-03-12 11:16:24 +01:00
Eyck Jentzsch f4ec21007b fix signedness issues 2021-03-11 16:12:28 +00:00
Eyck Jentzsch 768716b064 fix another missing XLEN 2021-03-09 11:07:56 +00:00
Eyck Jentzsch bea0dcc387 update missing XLEN 2021-03-09 11:03:37 +00:00
Eyck Jentzsch a6691bcd3c update generated code with correct sign extension 2021-03-09 10:21:36 +00:00
Eyck Jentzsch 40db74ce02 remove tgf_b code generation 2021-03-07 16:26:14 +00:00
Eyck Jentzsch c251fe15d5 fix desscriptions to conform to ISA spec version 20191213 and TGF-C 2021-03-07 10:51:00 +00:00
Eyck Jentzsch dae8acb8a3 checkpoint before refactor 2021-03-06 07:17:42 +00:00
Eyck Jentzsch f7cec99fa6 adapt to changes in SCC 2021-03-01 21:08:18 +00:00
Eyck Jentzsch be0e7db185 fix templates to comply with CoreDSL2 2021-03-01 21:07:20 +00:00
Eyck Jentzsch 9534d58d01 regenerated sources and and add opcode enum to headers 
Conflicts:
	gen_input/CoreDSL-Instruction-Set-Description
 2021-03-01 06:26:33 +00:00
Eyck Jentzsch 1668df0531 regenerated sources and and add opcode enum to headers 2021-02-23 08:29:31 +00:00
Eyck Jentzsch 337f1634c0 add mssing change 2021-02-15 18:01:46 +00:00
Eyck Jentzsch 72b09472d5 update RISC-V descriptions 2021-02-15 18:01:33 +00:00
Eyck Jentzsch 34bb8e62ae generate working ISS from CoreDSL 2.0 2021-02-06 14:47:06 +00:00
Eyck Jentzsch c4da47cedd integrate code generation into build process (first attempt) 2020-12-30 07:29:52 +00:00
Eyck Jentzsch ab554539e3 first version of tgf_c based on CoreDSL 2.0 2020-12-29 08:48:22 +00:00
Stanislaw Kaushanski 43488676dd Update TGF naming convention 2020-09-11 10:45:44 +02:00
Stanislaw Kaushanski 969b408288 Implement MHARTID register 2020-09-04 15:37:21 +02:00
Stanislaw Kaushanski 886b8f5716 TGF02 is a default core 2020-08-31 14:20:13 +02:00
Stanislaw Kaushanski 9754e3953f Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores 2020-08-24 15:01:54 +02:00
Stanislaw Kaushanski 8fce0c4759 Generate TGF01 and TGF02 cores 2020-08-20 17:29:36 +02:00
Eyck Jentzsch 71b976811b add backend selection 2020-06-18 09:58:43 +02:00
Eyck Jentzsch edeff7add8 update log macros 2020-06-18 07:38:56 +02:00
Eyck Jentzsch e902936931 make interpreter default 2020-06-18 07:22:50 +02:00
Eyck Jentzsch 55450f4900 [WIP] update dependencies in core desc 2020-06-18 06:18:59 +02:00
Eyck Jentzsch c619194465 [WIP] rework generator 2020-06-05 07:25:40 +02:00
Eyck Jentzsch abcfb75011 [WIP] 2020-05-31 16:41:04 +02:00
Eyck Jentzsch 10797a473d modernize build system and cleanup dependencies 2020-05-30 14:16:10 +02:00
Eyck Jentzsch 0ff6ccf9e2 get all compile clean 2020-05-30 11:27:44 +02:00
Eyck Jentzsch 0698b604fd add TCC backend 2020-05-29 08:52:55 +02:00
Eyck Jentzsch 264053a8d6 [WIP] add next increment for TCC 2020-04-17 19:23:43 +02:00
Eyck Jentzsch ae1c0b99fe [WIP] basic infrastructure working 2020-04-13 17:03:50 +02:00
Eyck Jentzsch 8cdf50d69e [WIP] implement basic infrastructure 2020-04-12 12:44:30 +02:00
Eyck Jentzsch 50663a2fbc [WIP] integrate tcc conan package 2020-04-10 17:14:04 +02:00
Eyck Jentzsch 15f4c059e6 [WIP] first working version 2020-01-12 18:19:48 +01:00
Eyck Jentzsch e483887c43 [WIP] Cleanup of namespaces etc to get compile clean 2020-01-10 11:12:20 +01:00
Eyck Jentzsch fd2e40bfd2 Initial setup 2020-01-10 07:24:00 +01:00
Eyck Jentzsch 116ed9bb5c [WIP] started to add TinyCC backend 2020-01-09 19:43:17 +01:00
Eyck Jentzsch 8b9775e06b Changed namespaces for LLVM related stuff 2020-01-07 16:38:31 +01:00
Eyck Jentzsch d037141d98 Fixed C++11 compatibility 2019-07-16 15:52:34 +02:00
Eyck Jentzsch 1947a2114f Fixed FMT header define 2019-07-14 16:51:14 +02:00
Eyck Jentzsch 7f06bba239 Fixed time csr handling 2019-06-28 20:58:02 +02:00
Eyck Jentzsch 2758933c16 Modernized CMake 2019-06-11 19:22:07 +00:00
Eyck Jentzsch 67d9beb7bd reorganized layout to only contain risc-v stuff 2019-06-11 16:49:37 +00:00