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c42e336509
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fix proper debug mode handling (#267 & #268)
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2021-11-07 17:48:44 +01:00 |
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334d3fb296
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adapt to SCC changes
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2021-10-21 22:53:16 +02:00 |
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1d13c8196e
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fix wrong PGMASK usage
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2021-10-11 10:40:01 +02:00 |
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2f15d9676e
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fix unaligned instr fetch behavior
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2021-09-30 19:27:46 +02:00 |
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174259155d
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add support for non-compressed ISA
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2021-09-23 21:09:52 +02:00 |
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d95846a849
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fix trap handling if illegal fetch (PMP) and U-mode CSRs
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2021-08-01 17:23:22 +02:00 |
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e68918c2e8
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fix instruction decode
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2021-07-09 07:37:12 +02:00 |
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23b9741adf
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refine and fix TGC_C iss to becoem compliant
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2021-06-29 11:51:30 +02:00 |
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e432dd8208
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fix handling of exceptions while accessing address spaces
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2021-06-07 22:22:36 +02:00 |
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aaceecd5dc
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fix mu_p platform features and CSRs
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2021-05-17 09:20:09 +02:00 |
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32e4aa83b8
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use extracted variables
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2021-03-27 09:36:52 +00:00 |
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78c7064295
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update groovy template to extract used registers
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2021-03-26 08:24:45 +00:00 |
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b0bcb7febb
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small fixes for robustness and readability
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2021-03-22 22:47:30 +00:00 |
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4e0f20eba0
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rework abort conditions
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2021-03-17 19:32:57 +00:00 |
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80057eef32
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fix RVC description bugs, remove paged fetch
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2021-03-13 10:46:41 +00:00 |
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a6691bcd3c
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update generated code with correct sign extension
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2021-03-09 10:21:36 +00:00 |
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c251fe15d5
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fix desscriptions to conform to ISA spec version 20191213 and TGF-C
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2021-03-07 10:51:00 +00:00 |
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9534d58d01
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regenerated sources and and add opcode enum to headers
Conflicts:
gen_input/CoreDSL-Instruction-Set-Description
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2021-03-01 06:26:33 +00:00 |
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34bb8e62ae
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generate working ISS from CoreDSL 2.0
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2021-02-06 14:47:06 +00:00 |
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c4da47cedd
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integrate code generation into build process (first attempt)
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2020-12-30 07:29:52 +00:00 |
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