Block a user
46f197c287
Add additional registers for input to FW
43e2a299db
fpga_spn: add check if input-/ref-data fits into memory
8450f85c93
raven_spn: add check if input-/ref-data fits into memory
a14ff554b0
Move XSPN input and ref data to Validation-VP
Add allocate+free functionality for fpga
588ca3c7ba
Merge pull request 'Add allocate+free functionality for fpga' (#1) from feature/fpga-alloc-free into master
91f28e9f2b
Add allocate+free functionality for fpga
Improve MINRES-SystemC performance
Improve MINRES-SystemC performance
ticket migrated to OpenProject https://project.minres.com/projects/minres-systemc-performance/work_packages/290/activity
Setup performance analysis flow
In main window: it must be possible to mark several signals at once. E.g. to delete them.
When working with VCD files, property and attribute tabs are useless and should be hidden.