Firmware/MNRS-BM-BSP
9
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Compare commits

base: Firmware:664dd6774028452c8e1ef4721ca8828e58296247
Branches Tags
Firmware:main Firmware:flexki Firmware:develop Firmware:cmake_flow
...
compare: Firmware:main
Branches Tags
Firmware:flexki Firmware:develop Firmware:cmake_flow Firmware:main

13 Commits
664dd67740 ... main

Author SHA1 Message Date
stas
87dc0ec230 Merge remote-tracking branch 'origin/develop' into main 2024-04-17 08:27:23 +02:00
Eyck-Alexander Jentzsch
71c7fd6981 changes type bc of name clashes 2024-04-15 12:17:01 +02:00
Eyck-Alexander Jentzsch
a45fee1f7e removes tgc-vp in favor of ehrenberg/tgc_vp 2024-04-15 12:16:29 +02:00
Eyck-Alexander Jentzsch
8ac5244670 changes fill naming to be stricly increasing 2024-03-28 11:48:37 +01:00
Eyck-Alexander Jentzsch
6365331de8 fixes bug that duplicated variable names 2024-03-28 11:33:57 +01:00
Eyck-Alexander Jentzsch
baddcf17af adds improved firmware headers for peripherals 2024-03-28 09:34:01 +01:00
Eyck Jentzsch
7218dcfa69 changes target extension to become .elf 2024-03-24 21:19:08 +01:00
Eyck Jentzsch
3389875643 fixes rve settings 2024-03-21 07:23:21 +01:00
Eyck Jentzsch
4d25972e4d fixes TGCP environment 2024-03-20 12:53:12 +01:00
Eyck Jentzsch
e051cf180e Merge branch 'develop' 2024-03-20 07:38:03 +01:00
Eyck Jentzsch
28bf59f0e3 Merge branch 'develop' of https://git.minres.com/Firmware/MNRS-BM-BSP.git into develop 2024-03-15 08:35:58 +01:00
Eyck Jentzsch
da52573163 fixes and enhances SPI register description 2024-03-15 08:35:46 +01:00
Eyck Jentzsch
ab2b7214fe fixes TGCP env 2024-03-14 08:12:52 +01:00
23 changed files with 895 additions and 688 deletions
Expand all files Collapse all files

7
env/TGCP/init.c vendored
View File

@ -110,12 +110,13 @@ void _fini()
}
int is_uart_ready(int uart_id){
return 1;
return !UART0_REG(UART_REG_TXFIFO) & 0x80000000;
}
int try_write_uart_char(int uart_id, char c){
*((char*)0x10000000) = c;
if(UART0_REG(UART_REG_TXFIFO) & 0x80000000) return 0;
UART0_REG(UART_REG_TXFIFO) = c;
return 1;
}
void write_uart_char(int uart_id, char c){
*((char*)0x10000000) = c;
UART0_REG(UART_REG_TXFIFO) = c;
}

71
env/TGCP/link.lds vendored
View File

@ -22,13 +22,18 @@ SECTIONS
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
*crt0.o(.text .text.*)
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.init)
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .text.*)
*(.stub)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
@ -50,6 +55,13 @@ SECTIONS
. = ALIGN(4);
/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >flash AT>flash :flash
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >flash AT>flash :flash
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
@ -116,13 +128,6 @@ SECTIONS
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
@ -133,9 +138,11 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
.data :
{
__SDATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
@ -158,7 +165,6 @@ SECTIONS
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
@ -171,4 +177,47 @@ SECTIONS
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
.debug_addr 0 : { *(.debug_addr) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}

13
env/TGCP/platform.h vendored
View File

@ -7,7 +7,18 @@
#define MCAUSE_INT 0x80000000
#define MCAUSE_CAUSE 0x7FFFFFFF
#include "bits.h"
#define UART0_BASE_ADDR 0xffff0000ULL
#define UART_REG_TXFIFO 0x00
#define UART_REG_RXFIFO 0x04
#define UART_REG_TXCTRL 0x08
#define UART_REG_RXCTRL 0x0c
#define UART_REG_IE 0x10
#define UART_REG_IP 0x14
#define UART_REG_DIV 0x18
#define UART_TXEN 0x1
#define UART0_REG(ADDR) *((volatile uint32_t*) (UART0_BASE_ADDR + ADDR))
/****************************************************************************
* Platform definitions
*****************************************************************************/

8
env/common-gcc.mk vendored
View File

@ -2,9 +2,10 @@ ifndef _MK_COMMON
_MK_COMMON := # defined
TL_TARGET?=all
BOARD?=iss
.PHONY: $(TL_TARGET)
$(TL_TARGET): $(TARGET)
$(TL_TARGET): $(TARGET).elf
ENV_DIR:=$(dir $(lastword $(MAKEFILE_LIST)))
BSP_BASE=$(ENV_DIR)/..
@ -12,7 +13,6 @@ PLATFORM_DIR = $(ENV_DIR)/$(BOARD)
include $(BSP_BASE)/libwrap/libwrap.mk
BOARD?=iss
ASM_SRCS += $(ENV_DIR)/start.S $(ENV_DIR)/entry.S
C_SRCS += $(PLATFORM_DIR)/init.c
@ -42,7 +42,7 @@ CXX_OBJS := $(CXX_SRCS:.cpp=.o)
LINK_OBJS += $(ASM_OBJS) $(C_OBJS) $(CXX_OBJS)
LINK_DEPS += $(LINKER_SCRIPT)
CLEAN_OBJS += $(TARGET) $(LINK_OBJS)
CLEAN_OBJS += $(TARGET).elf $(LINK_OBJS)
GCCVERSION = $(shell $(CC) --version | grep gcc | awk '{print($NF);}')
ifeq ($(GCCVERSION),9.2)
@ -63,7 +63,7 @@ OBJDUMP := $(TOOL_DIR)$(TRIPLET)-objdump
OBJCOPY := $(TOOL_DIR)$(TRIPLET)-objcopy
ifndef NO_DEFAULT_LINK
$(TARGET): $(LINK_OBJS) $(LINK_DEPS)
$(TARGET).elf: $(LINK_OBJS) $(LINK_DEPS)
echo LINK_OBJS: $(LINK_OBJS)
$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP_LDFLAGS) $(LIBWRAP) $(LD_SCRIPT) -o $@
$(OBJDUMP) -d -S $@ > $(TARGET).dis

72
env/ehrenberg/link.lds vendored
View File

@ -25,13 +25,18 @@ SECTIONS
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
*crt0.o(.text .text.*)
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.init)
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .text.*)
*(.stub)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
@ -53,6 +58,13 @@ SECTIONS
. = ALIGN(4);
/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >flash AT>flash :flash
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >flash AT>flash :flash
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
@ -119,15 +131,9 @@ SECTIONS
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
@ -135,9 +141,11 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
.data :
{
__SDATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
@ -160,7 +168,6 @@ SECTIONS
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
@ -173,4 +180,47 @@ SECTIONS
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
.debug_addr 0 : { *(.debug_addr) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}

4
env/entry.S vendored
View File

@ -10,7 +10,7 @@
.align 2
.global trap_entry
trap_entry:
#ifndef __riscv_abi_rve
#ifdef __riscv_abi_rve
addi sp, sp, -8*REGBYTES
STORE x1, 1*REGBYTES(sp) // ra
STORE x5, 2*REGBYTES(sp) // t0
@ -43,7 +43,7 @@ trap_entry:
mv a2, sp
call handle_trap
csrw mepc, a0
#ifndef __riscv_abi_rve
#ifdef __riscv_abi_rve
addi sp, sp, -8*REGBYTES
LOAD x1, 1*REGBYTES(sp) // ra
LOAD x5, 2*REGBYTES(sp) // t0

71
env/iss/link.lds vendored
View File

@ -22,13 +22,18 @@ SECTIONS
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
*crt0.o(.text .text.*)
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.init)
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .text.*)
*(.stub)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
@ -50,6 +55,13 @@ SECTIONS
. = ALIGN(4);
/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >flash AT>flash :flash
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >flash AT>flash :flash
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
@ -116,13 +128,6 @@ SECTIONS
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
@ -133,9 +138,11 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
.data :
{
__SDATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
@ -158,7 +165,6 @@ SECTIONS
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
@ -171,4 +177,47 @@ SECTIONS
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
.debug_addr 0 : { *(.debug_addr) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}

71
env/rtl/link.lds vendored
View File

@ -22,13 +22,18 @@ SECTIONS
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
*crt0.o(.text .text.*)
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.init)
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .text.*)
*(.stub)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
@ -50,6 +55,13 @@ SECTIONS
. = ALIGN(4);
/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >flash AT>flash :flash
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >flash AT>flash :flash
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
@ -116,13 +128,6 @@ SECTIONS
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
@ -133,9 +138,11 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
.data :
{
__SDATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
@ -158,7 +165,6 @@ SECTIONS
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
@ -171,4 +177,47 @@ SECTIONS
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
.debug_addr 0 : { *(.debug_addr) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}

1
env/tgc-vp/.gitignore vendored
View File

@ -1 +0,0 @@
/*.o

116
env/tgc-vp/init.c vendored
View File

@ -1,116 +0,0 @@
#include <stdint.h>
#include <stdio.h>
#include <unistd.h>
#include "platform.h"
#include "encoding.h"
extern int main(int argc, char** argv);
extern void trap_entry();
static unsigned long mtime_lo(void)
{
unsigned long ret;
__asm volatile("rdtime %0":"=r"(ret));
return ret;
}
#if __riscv_xlen==32
static uint32_t mtime_hi(void)
{
unsigned long ret;
__asm volatile("rdtimeh %0":"=r"(ret));
return ret;
}
uint64_t get_timer_value()
{
while (1) {
uint32_t hi = mtime_hi();
uint32_t lo = mtime_lo();
if (hi == mtime_hi())
return ((uint64_t)hi << 32) | lo;
}
}
#elif __riscv_xlen==64
uint64_t get_timer_value()
{
return mtime_lo();
}
#endif
unsigned long get_timer_freq()
{
return 32768;
}
unsigned long get_cpu_freq()
{
return 10000000;
}
void init_pll(void){
}
static void uart_init(size_t baud_rate)
{
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
}
#ifdef USE_PLIC
extern void handle_m_ext_interrupt();
#endif
#ifdef USE_M_TIME
extern void handle_m_time_interrupt();
#endif
uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
{
if (0){
#ifdef USE_PLIC
// External Machine-Level interrupt from PLIC
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
handle_m_ext_interrupt();
#endif
#ifdef USE_M_TIME
// External Machine-Level interrupt from PLIC
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
handle_m_time_interrupt();
#endif
}
else {
write(1, "trap\n", 5);
_exit(1 + mcause);
}
return epc;
}
void _init()
{
#ifndef NO_INIT
init_pll();
uart_init(115200);
printf("core freq at %d Hz\n", get_cpu_freq());
write_csr(mtvec, &trap_entry);
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
}
#endif
}
void _fini()
{
}

174
env/tgc-vp/link.lds vendored
View File

@ -1,174 +0,0 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 512M
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128K
}
PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash :flash
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >flash AT>flash :flash
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash :flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash :flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash :flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash :flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash :flash
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash :flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
}

127
env/tgc-vp/platform.h vendored
View File

@ -1,127 +0,0 @@
// See LICENSE for license details.
#ifndef _ISS_PLATFORM_H
#define _ISS_PLATFORM_H
// Some things missing from the official encoding.h
#define MCAUSE_INT 0x80000000
#define MCAUSE_CAUSE 0x7FFFFFFF
#include "bits.h"
#include "tgc-vp/devices/aon.h"
#include "tgc-vp/devices/clint.h"
#include "tgc-vp/devices/gpio.h"
#include "tgc-vp/devices/otp.h"
#include "tgc-vp/devices/plic.h"
#include "tgc-vp/devices/prci.h"
#include "tgc-vp/devices/pwm.h"
#include "tgc-vp/devices/spi.h"
#include "tgc-vp/devices/uart.h"
/****************************************************************************
* Platform definitions
*****************************************************************************/
// Memory map
#define MASKROM_BASE_ADDR _AC(0x00001000,UL)
#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
#define OTP_MMAP_ADDR _AC(0x00020000,UL)
#define CLINT_BASE_ADDR _AC(0x02000000,UL)
#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
#define AON_BASE_ADDR _AC(0x10000000,UL)
#define PRCI_BASE_ADDR _AC(0x10008000,UL)
#define OTP_BASE_ADDR _AC(0x10010000,UL)
#define GPIO_BASE_ADDR _AC(0x10012000,UL)
#define UART0_BASE_ADDR _AC(0x10013000,UL)
#define SPI0_BASE_ADDR _AC(0x10014000,UL)
#define PWM0_BASE_ADDR _AC(0x10015000,UL)
#define UART1_BASE_ADDR _AC(0x10023000,UL)
#define SPI1_BASE_ADDR _AC(0x10024000,UL)
#define PWM1_BASE_ADDR _AC(0x10025000,UL)
#define SPI2_BASE_ADDR _AC(0x10034000,UL)
#define PWM2_BASE_ADDR _AC(0x10035000,UL)
#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
#define MEM_BASE_ADDR _AC(0x80000000,UL)
// IOF masks
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
#define SPI11_NUM_SS (4)
#define IOF_SPI1_SS0 (2u)
#define IOF_SPI1_SS1 (8u)
#define IOF_SPI1_SS2 (9u)
#define IOF_SPI1_SS3 (10u)
#define IOF_SPI1_MOSI (3u)
#define IOF_SPI1_MISO (4u)
#define IOF_SPI1_SCK (5u)
#define IOF_SPI1_DQ0 (3u)
#define IOF_SPI1_DQ1 (4u)
#define IOF_SPI1_DQ2 (6u)
#define IOF_SPI1_DQ3 (7u)
#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
#define SPI2_NUM_SS (1)
#define IOF_SPI2_SS0 (26u)
#define IOF_SPI2_MOSI (27u)
#define IOF_SPI2_MISO (28u)
#define IOF_SPI2_SCK (29u)
#define IOF_SPI2_DQ0 (27u)
#define IOF_SPI2_DQ1 (28u)
#define IOF_SPI2_DQ2 (30u)
#define IOF_SPI2_DQ3 (31u)
//#define IOF0_I2C_MASK _AC(0x00003000,UL)
#define IOF0_UART0_MASK _AC(0x00030000, UL)
#define IOF_UART0_RX (16u)
#define IOF_UART0_TX (17u)
#define IOF0_UART1_MASK _AC(0x03000000, UL)
#define IOF_UART1_RX (24u)
#define IOF_UART1_TX (25u)
#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
// Interrupt numbers
#define INT_RESERVED 0
#define INT_WDOGCMP 1
#define INT_RTCCMP 2
#define INT_UART0_BASE 3
#define INT_UART1_BASE 4
#define INT_SPI0_BASE 5
#define INT_SPI1_BASE 6
#define INT_SPI2_BASE 7
#define INT_GPIO_BASE 8
#define INT_PWM0_BASE 40
#define INT_PWM1_BASE 44
#define INT_PWM2_BASE 48
// Helper functions
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
// Misc
#include <stdint.h>
void init_pll(void);
unsigned long get_cpu_freq(void);
unsigned long get_timer_freq(void);
uint64_t get_timer_value(void);
#endif /* _ISS_PLATFORM_H */

1
env/tgc_vp vendored Symbolic link
View File

@ -0,0 +1 @@
ehrenberg/

56
include/ehrenberg/devices/gen/Apb3AClint.h
View File

@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-02-19 14:24:37 UTC
* by peakrdl_mnrs version 1.2.2
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_APB3ACLINT_H
@ -14,40 +14,72 @@
typedef struct __attribute((__packed__)) {
volatile uint32_t MSIP0;
uint8_t fill0[16380];
volatile uint32_t MTIMECMP0LO;
volatile uint32_t MTIMECMP0HI;
uint8_t fill1[32752];
volatile uint32_t MTIME_LO;
volatile uint32_t MTIME_HI;
}apb3aclint_t;
inline uint32_t get_aclint_msip0(volatile apb3aclint_t *reg){
#define ACLINT_MSIP0_OFFS 0
#define ACLINT_MSIP0_MASK 0x1
#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
#define ACLINT_MTIMECMP0LO_OFFS 0
#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
#define ACLINT_MTIMECMP0HI_OFFS 0
#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
#define ACLINT_MTIME_LO_OFFS 0
#define ACLINT_MTIME_LO_MASK 0xffffffff
#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
#define ACLINT_MTIME_HI_OFFS 0
#define ACLINT_MTIME_HI_MASK 0xffffffff
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
//ACLINT_MSIP0
inline uint32_t get_aclint_msip0(volatile apb3aclint_t* reg){
return (reg->MSIP0 >> 0) & 0x1;
}
inline void set_aclint_msip0(volatile apb3aclint_t *reg, uint8_t value){
inline void set_aclint_msip0(volatile apb3aclint_t* reg, uint8_t value){
reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_aclint_mtimecmp0lo(volatile apb3aclint_t *reg){
//ACLINT_MTIMECMP0LO
inline uint32_t get_aclint_mtimecmp0lo(volatile apb3aclint_t* reg){
return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
}
inline void set_aclint_mtimecmp0lo(volatile apb3aclint_t *reg, uint32_t value){
inline void set_aclint_mtimecmp0lo(volatile apb3aclint_t* reg, uint32_t value){
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
}
inline uint32_t get_aclint_mtimecmp0hi(volatile apb3aclint_t *reg){
//ACLINT_MTIMECMP0HI
inline uint32_t get_aclint_mtimecmp0hi(volatile apb3aclint_t* reg){
return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
}
inline void set_aclint_mtimecmp0hi(volatile apb3aclint_t *reg, uint32_t value){
inline void set_aclint_mtimecmp0hi(volatile apb3aclint_t* reg, uint32_t value){
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
}
inline uint32_t get_aclint_mtime_lo(volatile apb3aclint_t *reg){
//ACLINT_MTIME_LO
inline uint32_t get_aclint_mtime_lo(volatile apb3aclint_t* reg){
return (reg->MTIME_LO >> 0) & 0xffffffff;
}
inline void set_aclint_mtime_lo(volatile apb3aclint_t *reg, uint32_t value){
inline void set_aclint_mtime_lo(volatile apb3aclint_t* reg, uint32_t value){
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
}
inline uint32_t get_aclint_mtime_hi(volatile apb3aclint_t *reg){
//ACLINT_MTIME_HI
inline uint32_t get_aclint_mtime_hi(volatile apb3aclint_t* reg){
return (reg->MTIME_HI >> 0) & 0xffffffff;
}
inline void set_aclint_mtime_hi(volatile apb3aclint_t *reg, uint32_t value){
inline void set_aclint_mtime_hi(volatile apb3aclint_t* reg, uint32_t value){
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_APB3ACLINT_H */

32
include/ehrenberg/devices/gen/Apb3Gpio.h
View File

@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-02-19 14:24:37 UTC
* by peakrdl_mnrs version 1.2.2
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_APB3GPIO_H
@ -18,19 +18,37 @@ typedef struct __attribute((__packed__)) {
volatile uint32_t WRITEENABLE;
}apb3gpio_t;
inline uint32_t get_gpio_value(volatile apb3gpio_t *reg){
#define GPIO_VALUE_OFFS 0
#define GPIO_VALUE_MASK 0xffffffff
#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
#define GPIO_WRITE_OFFS 0
#define GPIO_WRITE_MASK 0xffffffff
#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
#define GPIO_WRITEENABLE_OFFS 0
#define GPIO_WRITEENABLE_MASK 0xffffffff
#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
//GPIO_VALUE
inline uint32_t get_gpio_value(volatile apb3gpio_t* reg){
return (reg->VALUE >> 0) & 0xffffffff;
}
inline uint32_t get_gpio_write(volatile apb3gpio_t *reg){
//GPIO_WRITE
inline uint32_t get_gpio_write(volatile apb3gpio_t* reg){
return (reg->WRITE >> 0) & 0xffffffff;
}
inline void set_gpio_write(volatile apb3gpio_t *reg, uint32_t value){
inline void set_gpio_write(volatile apb3gpio_t* reg, uint32_t value){
reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
}
inline uint32_t get_gpio_writeEnable(volatile apb3gpio_t *reg){
//GPIO_WRITEENABLE
inline uint32_t get_gpio_writeEnable(volatile apb3gpio_t* reg){
return (reg->WRITEENABLE >> 0) & 0xffffffff;
}
inline void set_gpio_writeEnable(volatile apb3gpio_t *reg, uint32_t value){
inline void set_gpio_writeEnable(volatile apb3gpio_t* reg, uint32_t value){
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_APB3GPIO_H */

24
include/ehrenberg/devices/gen/Apb3IrqCtrl.h
View File

@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-02-19 14:24:37 UTC
* by peakrdl_mnrs version 1.2.2
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_APB3IRQCTRL_H
@ -17,16 +17,28 @@ typedef struct __attribute((__packed__)) {
volatile uint32_t MASKSREG;
}apb3irqctrl_t;
inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t *reg){
#define IRQ_PENDINGSREG_OFFS 0
#define IRQ_PENDINGSREG_MASK 0xf
#define IRQ_PENDINGSREG(V) ((V & IRQ_PENDINGSREG_MASK) << IRQ_PENDINGSREG_OFFS)
#define IRQ_MASKSREG_OFFS 0
#define IRQ_MASKSREG_MASK 0xf
#define IRQ_MASKSREG(V) ((V & IRQ_MASKSREG_MASK) << IRQ_MASKSREG_OFFS)
//IRQ_PENDINGSREG
inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t* reg){
return (reg->PENDINGSREG >> 0) & 0xf;
}
inline void set_irq_pendingsReg(volatile apb3irqctrl_t *reg, uint8_t value){
inline void set_irq_pendingsReg(volatile apb3irqctrl_t* reg, uint8_t value){
reg->PENDINGSREG = (reg->PENDINGSREG & ~(0xfU << 0)) | (value << 0);
}
inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t *reg){
//IRQ_MASKSREG
inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t* reg){
return (reg->MASKSREG >> 0) & 0xf;
}
inline void set_irq_masksReg(volatile apb3irqctrl_t *reg, uint8_t value){
inline void set_irq_masksReg(volatile apb3irqctrl_t* reg, uint8_t value){
reg->MASKSREG = (reg->MASKSREG & ~(0xfU << 0)) | (value << 0);
}
#endif /* _BSP_APB3IRQCTRL_H */

301
include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h
View File

@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-02-19 14:24:37 UTC
* by peakrdl_mnrs version 1.2.2
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_APB3SPIXDRMASTERCTRL_H
@ -17,173 +17,366 @@ typedef struct __attribute((__packed__)) {
volatile uint32_t STATUS;
volatile uint32_t CONFIG;
volatile uint32_t INTR;
uint8_t fill0[16];
volatile uint32_t SCLK_CONFIG;
volatile uint32_t SSGEN_SETUP;
volatile uint32_t SSGEN_HOLD;
volatile uint32_t SSGEN_DISABLE;
volatile uint32_t SSGEN_ACTIVE_HIGH;
uint8_t fill1[12];
volatile uint32_t XIP_ENABLE;
volatile uint32_t XIP_CONFIG;
volatile uint32_t XIP_MODE;
uint8_t fill2[4];
volatile uint32_t XIP_WRITE;
volatile uint32_t XIP_READ_WRITE;
volatile uint32_t XIP_READ;
}apb3spixdrmasterctrl_t;
inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
#define SPI_DATA_DATA_OFFS 0
#define SPI_DATA_DATA_MASK 0xff
#define SPI_DATA_DATA(V) ((V & SPI_DATA_DATA_MASK) << SPI_DATA_DATA_OFFS)
#define SPI_DATA_WRITE_OFFS 8
#define SPI_DATA_WRITE_MASK 0x1
#define SPI_DATA_WRITE(V) ((V & SPI_DATA_WRITE_MASK) << SPI_DATA_WRITE_OFFS)
#define SPI_DATA_READ_OFFS 9
#define SPI_DATA_READ_MASK 0x1
#define SPI_DATA_READ(V) ((V & SPI_DATA_READ_MASK) << SPI_DATA_READ_OFFS)
#define SPI_DATA_KIND_OFFS 11
#define SPI_DATA_KIND_MASK 0x1
#define SPI_DATA_KIND(V) ((V & SPI_DATA_KIND_MASK) << SPI_DATA_KIND_OFFS)
#define SPI_DATA_RX_DATA_INVALID_OFFS 31
#define SPI_DATA_RX_DATA_INVALID_MASK 0x1
#define SPI_DATA_RX_DATA_INVALID(V) ((V & SPI_DATA_RX_DATA_INVALID_MASK) << SPI_DATA_RX_DATA_INVALID_OFFS)
#define SPI_STATUS_TX_FREE_OFFS 0
#define SPI_STATUS_TX_FREE_MASK 0x3f
#define SPI_STATUS_TX_FREE(V) ((V & SPI_STATUS_TX_FREE_MASK) << SPI_STATUS_TX_FREE_OFFS)
#define SPI_STATUS_RX_AVAIL_OFFS 16
#define SPI_STATUS_RX_AVAIL_MASK 0x3f
#define SPI_STATUS_RX_AVAIL(V) ((V & SPI_STATUS_RX_AVAIL_MASK) << SPI_STATUS_RX_AVAIL_OFFS)
#define SPI_CONFIG_KIND_OFFS 0
#define SPI_CONFIG_KIND_MASK 0x3
#define SPI_CONFIG_KIND(V) ((V & SPI_CONFIG_KIND_MASK) << SPI_CONFIG_KIND_OFFS)
#define SPI_CONFIG_MODE_OFFS 4
#define SPI_CONFIG_MODE_MASK 0x7
#define SPI_CONFIG_MODE(V) ((V & SPI_CONFIG_MODE_MASK) << SPI_CONFIG_MODE_OFFS)
#define SPI_INTR_TX_IE_OFFS 0
#define SPI_INTR_TX_IE_MASK 0x1
#define SPI_INTR_TX_IE(V) ((V & SPI_INTR_TX_IE_MASK) << SPI_INTR_TX_IE_OFFS)
#define SPI_INTR_RX_IE_OFFS 1
#define SPI_INTR_RX_IE_MASK 0x1
#define SPI_INTR_RX_IE(V) ((V & SPI_INTR_RX_IE_MASK) << SPI_INTR_RX_IE_OFFS)
#define SPI_INTR_TX_IP_OFFS 8
#define SPI_INTR_TX_IP_MASK 0x1
#define SPI_INTR_TX_IP(V) ((V & SPI_INTR_TX_IP_MASK) << SPI_INTR_TX_IP_OFFS)
#define SPI_INTR_RX_IP_OFFS 9
#define SPI_INTR_RX_IP_MASK 0x1
#define SPI_INTR_RX_IP(V) ((V & SPI_INTR_RX_IP_MASK) << SPI_INTR_RX_IP_OFFS)
#define SPI_INTR_TX_ACTIVE_OFFS 16
#define SPI_INTR_TX_ACTIVE_MASK 0x1
#define SPI_INTR_TX_ACTIVE(V) ((V & SPI_INTR_TX_ACTIVE_MASK) << SPI_INTR_TX_ACTIVE_OFFS)
#define SPI_SCLK_CONFIG_OFFS 0
#define SPI_SCLK_CONFIG_MASK 0xfff
#define SPI_SCLK_CONFIG(V) ((V & SPI_SCLK_CONFIG_MASK) << SPI_SCLK_CONFIG_OFFS)
#define SPI_SSGEN_SETUP_OFFS 0
#define SPI_SSGEN_SETUP_MASK 0xfff
#define SPI_SSGEN_SETUP(V) ((V & SPI_SSGEN_SETUP_MASK) << SPI_SSGEN_SETUP_OFFS)
#define SPI_SSGEN_HOLD_OFFS 0
#define SPI_SSGEN_HOLD_MASK 0xfff
#define SPI_SSGEN_HOLD(V) ((V & SPI_SSGEN_HOLD_MASK) << SPI_SSGEN_HOLD_OFFS)
#define SPI_SSGEN_DISABLE_OFFS 0
#define SPI_SSGEN_DISABLE_MASK 0xfff
#define SPI_SSGEN_DISABLE(V) ((V & SPI_SSGEN_DISABLE_MASK) << SPI_SSGEN_DISABLE_OFFS)
#define SPI_SSGEN_ACTIVE_HIGH_OFFS 0
#define SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
#define SPI_SSGEN_ACTIVE_HIGH(V) ((V & SPI_SSGEN_ACTIVE_HIGH_MASK) << SPI_SSGEN_ACTIVE_HIGH_OFFS)
#define SPI_XIP_ENABLE_OFFS 0
#define SPI_XIP_ENABLE_MASK 0x1
#define SPI_XIP_ENABLE(V) ((V & SPI_XIP_ENABLE_MASK) << SPI_XIP_ENABLE_OFFS)
#define SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
#define SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
#define SPI_XIP_CONFIG_INSTRUCTION(V) ((V & SPI_XIP_CONFIG_INSTRUCTION_MASK) << SPI_XIP_CONFIG_INSTRUCTION_OFFS)
#define SPI_XIP_CONFIG_ENABLE_OFFS 8
#define SPI_XIP_CONFIG_ENABLE_MASK 0x1
#define SPI_XIP_CONFIG_ENABLE(V) ((V & SPI_XIP_CONFIG_ENABLE_MASK) << SPI_XIP_CONFIG_ENABLE_OFFS)
#define SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
#define SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
#define SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
#define SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
#define SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
#define SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
#define SPI_XIP_MODE_INSTRUCTION_OFFS 0
#define SPI_XIP_MODE_INSTRUCTION_MASK 0x7
#define SPI_XIP_MODE_INSTRUCTION(V) ((V & SPI_XIP_MODE_INSTRUCTION_MASK) << SPI_XIP_MODE_INSTRUCTION_OFFS)
#define SPI_XIP_MODE_ADDRESS_OFFS 8
#define SPI_XIP_MODE_ADDRESS_MASK 0x7
#define SPI_XIP_MODE_ADDRESS(V) ((V & SPI_XIP_MODE_ADDRESS_MASK) << SPI_XIP_MODE_ADDRESS_OFFS)
#define SPI_XIP_MODE_DUMMY_OFFS 16
#define SPI_XIP_MODE_DUMMY_MASK 0x7
#define SPI_XIP_MODE_DUMMY(V) ((V & SPI_XIP_MODE_DUMMY_MASK) << SPI_XIP_MODE_DUMMY_OFFS)
#define SPI_XIP_MODE_PAYLOAD_OFFS 24
#define SPI_XIP_MODE_PAYLOAD_MASK 0x7
#define SPI_XIP_MODE_PAYLOAD(V) ((V & SPI_XIP_MODE_PAYLOAD_MASK) << SPI_XIP_MODE_PAYLOAD_OFFS)
#define SPI_XIP_WRITE_OFFS 0
#define SPI_XIP_WRITE_MASK 0xff
#define SPI_XIP_WRITE(V) ((V & SPI_XIP_WRITE_MASK) << SPI_XIP_WRITE_OFFS)
#define SPI_XIP_READ_WRITE_OFFS 0
#define SPI_XIP_READ_WRITE_MASK 0xff
#define SPI_XIP_READ_WRITE(V) ((V & SPI_XIP_READ_WRITE_MASK) << SPI_XIP_READ_WRITE_OFFS)
#define SPI_XIP_READ_OFFS 0
#define SPI_XIP_READ_MASK 0xff
#define SPI_XIP_READ(V) ((V & SPI_XIP_READ_MASK) << SPI_XIP_READ_OFFS)
//SPI_DATA
inline uint32_t get_spi_data(volatile apb3spixdrmasterctrl_t* reg){
return reg->DATA;
}
inline void set_spi_data(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->DATA = value;
}
inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_spi_data_write(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_data_write(volatile apb3spixdrmasterctrl_t* reg){
return (reg->DATA >> 8) & 0x1;
}
inline void set_spi_data_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_data_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_spi_data_read(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_data_read(volatile apb3spixdrmasterctrl_t* reg){
return (reg->DATA >> 9) & 0x1;
}
inline void set_spi_data_read(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_data_read(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_data_kind(volatile apb3spixdrmasterctrl_t* reg){
return (reg->DATA >> 11) & 0x1;
}
inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
}
inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t* reg){
return (reg->DATA >> 31) & 0x1;
}
inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t *reg){
//SPI_STATUS
inline uint32_t get_spi_status(volatile apb3spixdrmasterctrl_t* reg){
return reg->STATUS;
}
inline void set_spi_status(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->STATUS = value;
}
inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t* reg){
return (reg->STATUS >> 0) & 0x3f;
}
inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t* reg){
return (reg->STATUS >> 16) & 0x3f;
}
inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg){
//SPI_CONFIG
inline uint32_t get_spi_config(volatile apb3spixdrmasterctrl_t* reg){
return reg->CONFIG;
}
inline void set_spi_config(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->CONFIG = value;
}
inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t* reg){
return (reg->CONFIG >> 0) & 0x3;
}
inline void set_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_config_kind(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t* reg){
return (reg->CONFIG >> 4) & 0x7;
}
inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x7U << 4)) | (value << 4);
}
inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg){
//SPI_INTR
inline uint32_t get_spi_intr(volatile apb3spixdrmasterctrl_t* reg){
return reg->INTR;
}
inline void set_spi_intr(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->INTR = value;
}
inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t* reg){
return (reg->INTR >> 0) & 0x1;
}
inline void set_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t* reg){
return (reg->INTR >> 1) & 0x1;
}
inline void set_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_spi_intr_tx_ip(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_intr_tx_ip(volatile apb3spixdrmasterctrl_t* reg){
return (reg->INTR >> 8) & 0x1;
}
inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t* reg){
return (reg->INTR >> 9) & 0x1;
}
inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t* reg){
return (reg->INTR >> 16) & 0x1;
}
inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg){
//SPI_SCLK_CONFIG
inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t* reg){
return (reg->SCLK_CONFIG >> 0) & 0xfff;
}
inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg){
//SPI_SSGEN_SETUP
inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t* reg){
return (reg->SSGEN_SETUP >> 0) & 0xfff;
}
inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg){
//SPI_SSGEN_HOLD
inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t* reg){
return (reg->SSGEN_HOLD >> 0) & 0xfff;
}
inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg){
//SPI_SSGEN_DISABLE
inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t* reg){
return (reg->SSGEN_DISABLE >> 0) & 0xfff;
}
inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg){
//SPI_SSGEN_ACTIVE_HIGH
inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t* reg){
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
}
inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg){
//SPI_XIP_ENABLE
inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_ENABLE >> 0) & 0x1;
}
inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg){
//SPI_XIP_CONFIG
inline uint32_t get_spi_xip_config(volatile apb3spixdrmasterctrl_t* reg){
return reg->XIP_CONFIG;
}
inline void set_spi_xip_config(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->XIP_CONFIG = value;
}
inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_CONFIG >> 0) & 0xff;
}
inline void set_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_CONFIG >> 8) & 0x1;
}
inline void set_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_CONFIG >> 16) & 0xff;
}
inline void set_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
}
inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_CONFIG >> 24) & 0xf;
}
inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
}
inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg){
//SPI_XIP_MODE
inline uint32_t get_spi_xip_mode(volatile apb3spixdrmasterctrl_t* reg){
return reg->XIP_MODE;
}
inline void set_spi_xip_mode(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->XIP_MODE = value;
}
inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_MODE >> 0) & 0x7;
}
inline void set_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_MODE >> 8) & 0x7;
}
inline void set_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 8)) | (value << 8);
}
inline uint32_t get_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_MODE >> 16) & 0x7;
}
inline void set_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 16)) | (value << 16);
}
inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg){
inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_MODE >> 24) & 0x7;
}
inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 24)) | (value << 24);
}
inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
//SPI_XIP_WRITE
inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
}
inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
//SPI_XIP_READ_WRITE
inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t *reg){
//SPI_XIP_READ
inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_READ >> 0) & 0xff;
}
#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */

98
include/ehrenberg/devices/gen/Apb3Timer.h
View File

@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-02-19 14:24:37 UTC
* by peakrdl_mnrs version 1.2.2
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_APB3TIMER_H
@ -22,52 +22,114 @@ typedef struct __attribute((__packed__)) {
volatile uint32_t T1_VALUE;
}apb3timer_t;
inline uint32_t get_timer_prescaler(volatile apb3timer_t *reg){
#define TIMER_PRESCALER_OFFS 0
#define TIMER_PRESCALER_MASK 0xffff
#define TIMER_PRESCALER(V) ((V & TIMER_PRESCALER_MASK) << TIMER_PRESCALER_OFFS)
#define TIMER_T0_CTRL_ENABLE_OFFS 0
#define TIMER_T0_CTRL_ENABLE_MASK 0x7
#define TIMER_T0_CTRL_ENABLE(V) ((V & TIMER_T0_CTRL_ENABLE_MASK) << TIMER_T0_CTRL_ENABLE_OFFS)
#define TIMER_T0_CTRL_CLEAR_OFFS 3
#define TIMER_T0_CTRL_CLEAR_MASK 0x3
#define TIMER_T0_CTRL_CLEAR(V) ((V & TIMER_T0_CTRL_CLEAR_MASK) << TIMER_T0_CTRL_CLEAR_OFFS)
#define TIMER_T0_OVERFLOW_OFFS 0
#define TIMER_T0_OVERFLOW_MASK 0xffffffff
#define TIMER_T0_OVERFLOW(V) ((V & TIMER_T0_OVERFLOW_MASK) << TIMER_T0_OVERFLOW_OFFS)
#define TIMER_T0_VALUE_OFFS 0
#define TIMER_T0_VALUE_MASK 0xffffffff
#define TIMER_T0_VALUE(V) ((V & TIMER_T0_VALUE_MASK) << TIMER_T0_VALUE_OFFS)
#define TIMER_T1_CTRL_ENABLE_OFFS 0
#define TIMER_T1_CTRL_ENABLE_MASK 0x7
#define TIMER_T1_CTRL_ENABLE(V) ((V & TIMER_T1_CTRL_ENABLE_MASK) << TIMER_T1_CTRL_ENABLE_OFFS)
#define TIMER_T1_CTRL_CLEAR_OFFS 3
#define TIMER_T1_CTRL_CLEAR_MASK 0x3
#define TIMER_T1_CTRL_CLEAR(V) ((V & TIMER_T1_CTRL_CLEAR_MASK) << TIMER_T1_CTRL_CLEAR_OFFS)
#define TIMER_T1_OVERFLOW_OFFS 0
#define TIMER_T1_OVERFLOW_MASK 0xffffffff
#define TIMER_T1_OVERFLOW(V) ((V & TIMER_T1_OVERFLOW_MASK) << TIMER_T1_OVERFLOW_OFFS)
#define TIMER_T1_VALUE_OFFS 0
#define TIMER_T1_VALUE_MASK 0xffffffff
#define TIMER_T1_VALUE(V) ((V & TIMER_T1_VALUE_MASK) << TIMER_T1_VALUE_OFFS)
//TIMER_PRESCALER
inline uint32_t get_timer_prescaler(volatile apb3timer_t* reg){
return (reg->PRESCALER >> 0) & 0xffff;
}
inline void set_timer_prescaler(volatile apb3timer_t *reg, uint16_t value){
inline void set_timer_prescaler(volatile apb3timer_t* reg, uint16_t value){
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
}
inline uint32_t get_timer_t0_ctrl_enable(volatile apb3timer_t *reg){
//TIMER_T0_CTRL
inline uint32_t get_timer_t0_ctrl(volatile apb3timer_t* reg){
return reg->T0_CTRL;
}
inline void set_timer_t0_ctrl(volatile apb3timer_t* reg, uint32_t value){
reg->T0_CTRL = value;
}
inline uint32_t get_timer_t0_ctrl_enable(volatile apb3timer_t* reg){
return (reg->T0_CTRL >> 0) & 0x7;
}
inline void set_timer_t0_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
inline void set_timer_t0_ctrl_enable(volatile apb3timer_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timer_t0_ctrl_clear(volatile apb3timer_t *reg){
inline uint32_t get_timer_t0_ctrl_clear(volatile apb3timer_t* reg){
return (reg->T0_CTRL >> 3) & 0x3;
}
inline void set_timer_t0_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
inline void set_timer_t0_ctrl_clear(volatile apb3timer_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_timer_t0_overflow(volatile apb3timer_t *reg){
//TIMER_T0_OVERFLOW
inline uint32_t get_timer_t0_overflow(volatile apb3timer_t* reg){
return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timer_t0_overflow(volatile apb3timer_t *reg, uint32_t value){
inline void set_timer_t0_overflow(volatile apb3timer_t* reg, uint32_t value){
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
inline uint32_t get_timer_t0_value(volatile apb3timer_t *reg){
//TIMER_T0_VALUE
inline uint32_t get_timer_t0_value(volatile apb3timer_t* reg){
return (reg->T0_VALUE >> 0) & 0xffffffff;
}
inline uint32_t get_timer_t1_ctrl_enable(volatile apb3timer_t *reg){
//TIMER_T1_CTRL
inline uint32_t get_timer_t1_ctrl(volatile apb3timer_t* reg){
return reg->T1_CTRL;
}
inline void set_timer_t1_ctrl(volatile apb3timer_t* reg, uint32_t value){
reg->T1_CTRL = value;
}
inline uint32_t get_timer_t1_ctrl_enable(volatile apb3timer_t* reg){
return (reg->T1_CTRL >> 0) & 0x7;
}
inline void set_timer_t1_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
inline void set_timer_t1_ctrl_enable(volatile apb3timer_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timer_t1_ctrl_clear(volatile apb3timer_t *reg){
inline uint32_t get_timer_t1_ctrl_clear(volatile apb3timer_t* reg){
return (reg->T1_CTRL >> 3) & 0x3;
}
inline void set_timer_t1_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
inline void set_timer_t1_ctrl_clear(volatile apb3timer_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_timer_t1_overflow(volatile apb3timer_t *reg){
//TIMER_T1_OVERFLOW
inline uint32_t get_timer_t1_overflow(volatile apb3timer_t* reg){
return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timer_t1_overflow(volatile apb3timer_t *reg, uint32_t value){
inline void set_timer_t1_overflow(volatile apb3timer_t* reg, uint32_t value){
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
inline uint32_t get_timer_t1_value(volatile apb3timer_t *reg){
//TIMER_T1_VALUE
inline uint32_t get_timer_t1_value(volatile apb3timer_t* reg){
return (reg->T1_VALUE >> 0) & 0xffffffff;
}
#endif /* _BSP_APB3TIMER_H */

160
include/ehrenberg/devices/gen/Apb3Uart.h
View File

@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-02-19 14:24:37 UTC
* by peakrdl_mnrs version 1.2.2
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_APB3UART_H
@ -20,85 +20,187 @@ typedef struct __attribute((__packed__)) {
volatile uint32_t STATUS_REG;
}apb3uart_t;
inline uint32_t get_uart_rx_tx_reg_data(volatile apb3uart_t *reg){
#define UART_RX_TX_REG_DATA_OFFS 0
#define UART_RX_TX_REG_DATA_MASK 0xff
#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
#define UART_RX_TX_REG_TX_FREE_OFFS 15
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
#define UART_CLK_DIVIDER_REG_OFFS 0
#define UART_CLK_DIVIDER_REG_MASK 0xfffff
#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
#define UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS 0
#define UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK 0x7
#define UART_FRAME_CONFIG_REG_DATA_LENGHT(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS)
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
#define UART_STATUS_REG_READ_ERROR_OFFS 0
#define UART_STATUS_REG_READ_ERROR_MASK 0x1
#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
#define UART_STATUS_REG_STALL_OFFS 1
#define UART_STATUS_REG_STALL_MASK 0x1
#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
#define UART_STATUS_REG_BREAK_OFFS 8
#define UART_STATUS_REG_BREAK_MASK 0x1
#define UART_STATUS_REG_BREAK(V) ((V & UART_STATUS_REG_BREAK_MASK) << UART_STATUS_REG_BREAK_OFFS)
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
#define UART_STATUS_REG_SET_BREAK_OFFS 10
#define UART_STATUS_REG_SET_BREAK_MASK 0x1
#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
//UART_RX_TX_REG
inline uint32_t get_uart_rx_tx_reg(volatile apb3uart_t* reg){
return reg->RX_TX_REG;
}
inline void set_uart_rx_tx_reg(volatile apb3uart_t* reg, uint32_t value){
reg->RX_TX_REG = value;
}
inline uint32_t get_uart_rx_tx_reg_data(volatile apb3uart_t* reg){
return (reg->RX_TX_REG >> 0) & 0xff;
}
inline void set_uart_rx_tx_reg_data(volatile apb3uart_t *reg, uint8_t value){
inline void set_uart_rx_tx_reg_data(volatile apb3uart_t* reg, uint8_t value){
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile apb3uart_t *reg){
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile apb3uart_t* reg){
return (reg->RX_TX_REG >> 14) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile apb3uart_t *reg){
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile apb3uart_t* reg){
return (reg->RX_TX_REG >> 15) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg){
//UART_INT_CTRL_REG
inline uint32_t get_uart_int_ctrl_reg(volatile apb3uart_t* reg){
return reg->INT_CTRL_REG;
}
inline void set_uart_int_ctrl_reg(volatile apb3uart_t* reg, uint32_t value){
reg->INT_CTRL_REG = value;
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t* reg){
return (reg->INT_CTRL_REG >> 0) & 0x1;
}
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg, uint8_t value){
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg){
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t* reg){
return (reg->INT_CTRL_REG >> 1) & 0x1;
}
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg, uint8_t value){
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile apb3uart_t *reg){
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile apb3uart_t* reg){
return (reg->INT_CTRL_REG >> 8) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile apb3uart_t *reg){
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile apb3uart_t* reg){
return (reg->INT_CTRL_REG >> 9) & 0x1;
}
inline uint32_t get_uart_clk_divider_reg(volatile apb3uart_t *reg){
//UART_CLK_DIVIDER_REG
inline uint32_t get_uart_clk_divider_reg(volatile apb3uart_t* reg){
return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
}
inline void set_uart_clk_divider_reg(volatile apb3uart_t *reg, uint32_t value){
inline void set_uart_clk_divider_reg(volatile apb3uart_t* reg, uint32_t value){
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
}
inline uint32_t get_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg){
//UART_FRAME_CONFIG_REG
inline uint32_t get_uart_frame_config_reg(volatile apb3uart_t* reg){
return reg->FRAME_CONFIG_REG;
}
inline void set_uart_frame_config_reg(volatile apb3uart_t* reg, uint32_t value){
reg->FRAME_CONFIG_REG = value;
}
inline uint32_t get_uart_frame_config_reg_data_lenght(volatile apb3uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
}
inline void set_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg, uint8_t value){
inline void set_uart_frame_config_reg_data_lenght(volatile apb3uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_uart_frame_config_reg_parity(volatile apb3uart_t *reg){
inline uint32_t get_uart_frame_config_reg_parity(volatile apb3uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
}
inline void set_uart_frame_config_reg_parity(volatile apb3uart_t *reg, uint8_t value){
inline void set_uart_frame_config_reg_parity(volatile apb3uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg){
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile apb3uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
}
inline void set_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg, uint8_t value){
inline void set_uart_frame_config_reg_stop_bit(volatile apb3uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
inline uint32_t get_uart_status_reg_read_error(volatile apb3uart_t *reg){
//UART_STATUS_REG
inline uint32_t get_uart_status_reg(volatile apb3uart_t* reg){
return reg->STATUS_REG;
}
inline void set_uart_status_reg(volatile apb3uart_t* reg, uint32_t value){
reg->STATUS_REG = value;
}
inline uint32_t get_uart_status_reg_read_error(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 0) & 0x1;
}
inline uint32_t get_uart_status_reg_stall(volatile apb3uart_t *reg){
inline uint32_t get_uart_status_reg_stall(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 1) & 0x1;
}
inline uint32_t get_uart_status_reg_break(volatile apb3uart_t *reg){
inline uint32_t get_uart_status_reg_break(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 8) & 0x1;
}
inline uint32_t get_uart_status_reg_break_detected(volatile apb3uart_t *reg){
inline uint32_t get_uart_status_reg_break_detected(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 9) & 0x1;
}
inline void set_uart_status_reg_break_detected(volatile apb3uart_t *reg, uint8_t value){
inline void set_uart_status_reg_break_detected(volatile apb3uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_uart_status_reg_set_break(volatile apb3uart_t *reg){
inline uint32_t get_uart_status_reg_set_break(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 10) & 0x1;
}
inline void set_uart_status_reg_set_break(volatile apb3uart_t *reg, uint8_t value){
inline void set_uart_status_reg_set_break(volatile apb3uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
}
inline uint32_t get_uart_status_reg_clear_break(volatile apb3uart_t *reg){
inline uint32_t get_uart_status_reg_clear_break(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 11) & 0x1;
}
inline void set_uart_status_reg_clear_break(volatile apb3uart_t *reg, uint8_t value){
inline void set_uart_status_reg_clear_break(volatile apb3uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
}
#endif /* _BSP_APB3UART_H */

16
include/ehrenberg/devices/timer.h
View File

@ -1,21 +1,19 @@
#ifndef _BSP_TIMER_H
#define _BSP_TIMER_H
#include <stdint.h>
#include "gen/Apb3Timer.h"
#include <stdint.h>
#define timer_t apb3timer_t
inline void prescaler_init(timer_t* reg, uint16_t value){
set_timer_prescaler(reg, value);
inline void prescaler_init(apb3timer_t *reg, uint16_t value) {
set_timer_prescaler(reg, value);
}
inline void timer_t0__init(timer_t *reg){
set_timer_t0_overflow(reg, 0xffffffff);
inline void timer_t0__init(apb3timer_t *reg) {
set_timer_t0_overflow(reg, 0xffffffff);
}
inline void timer_t1__init(timer_t *reg){
set_timer_t1_overflow(reg, 0xffffffff);
inline void timer_t1__init(apb3timer_t *reg) {
set_timer_t1_overflow(reg, 0xffffffff);
}
#endif /* _BSP_TIMER_H */

22
libwrap/sys/puts.c
View File

@ -1,30 +1,32 @@
/* See LICENSE of license details. */
#include <stdint.h>
#include <errno.h>
#include <unistd.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
int __wrap_puts(const char *s)
{
int __wrap_puts(const char *s) {
while (*s != '\0') {
#if defined(BOARD_ehrenberg)
while (get_uart_rx_tx_reg_tx_free(uart)==0) ;
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
while (get_uart_rx_tx_reg_tx_free(uart) == 0)
;
uart_write(uart, *s);
#elif defined(BOARD_iss)
*((uint32_t*) 0xFFFF0000) = *s;
*((uint32_t *)0xFFFF0000) = *s;
#elif defined(BOARD_TGCP)
//TODO: implement
// TODO: implement
#else
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = *s;
if (*s == '\n') {
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = '\r';
}
#endif

87
libwrap/sys/read.c
View File

@ -1,59 +1,54 @@
/* See LICENSE of license details. */
#include <stdint.h>
#include <errno.h>
#include <unistd.h>
#include <sys/types.h>
#if defined(BOARD_ehrenberg)
#include "platform.h"
#endif
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
ssize_t __wrap_read(int fd, void* ptr, size_t len)
{
uint8_t * current = (uint8_t *)ptr;
ssize_t __wrap_read(int fd, void *ptr, size_t len) {
uint8_t *current = (uint8_t *)ptr;
#if defined(BOARD_hifive1)
volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
volatile uint32_t *uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
volatile uint8_t *uart_rx_cnt =
(uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2);
#elif defined(BOARD_iss)
volatile uint32_t * uart_rx = (uint32_t*)0xFFFF0000;
volatile uint32_t *uart_rx = (uint32_t *)0xFFFF0000;
#elif defined(BOARD_TGCP)
//TODO: implement
#elif !defined(BOARD_ehrenberg)
volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2);
// TODO: implement
#elif !defined(BOARD_ehrenberg) && !defined(BOARD_tgc_vp)
volatile uint32_t *uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
volatile uint8_t *uart_rx_cnt =
(uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2);
#endif
ssize_t result = 0;
if (isatty(fd)) {
#if defined(BOARD_ehrenberg)
for (current = (uint8_t *)ptr;
(current < ((uint8_t *)ptr) + len) && (get_uart_rx_tx_reg_rx_avail(uart) > 0);
current ++) {
*current = uart_read(uart);
result++;
}
#elif defined(BOARD_iss)
for (current = (uint8_t *)ptr;
(current < ((uint8_t *)ptr) + len);
current ++) {
*current = *uart_rx;
result++;
}
#elif defined(BOARD_TGCP)
//TODO: implement
#else
for (current = (uint8_t *)ptr;
(current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);
current ++) {
*current = *uart_rx;
result++;
}
#endif
return result;
ssize_t result = 0;
if (isatty(fd)) {
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
(get_uart_rx_tx_reg_rx_avail(uart) > 0);
current++) {
*current = uart_read(uart);
result++;
}
return _stub(EBADF);
#elif defined(BOARD_iss)
for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len);
current++) {
*current = *uart_rx;
result++;
}
#elif defined(BOARD_TGCP)
// TODO: implement
#else
for (current = (uint8_t *)ptr;
(current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); current++) {
*current = *uart_rx;
result++;
}
#endif
return result;
}
return _stub(EBADF);
}
weak_under_alias(read);

51
libwrap/sys/write.c
View File

@ -1,42 +1,43 @@
/* See LICENSE of license details. */
#include <stdint.h>
#include <errno.h>
#include <unistd.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
ssize_t __wrap_write(int fd, const void* ptr, size_t len)
{
const uint8_t * current = (const uint8_t *)ptr;
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
#if defined(BOARD_ehrenberg)
while (get_uart_rx_tx_reg_tx_free(uart)==0) ;
uart_write(uart, current[jj]);
if (current[jj] == '\n') {
while (get_uart_rx_tx_reg_tx_free(uart)==0) ;
uart_write(uart, '\r');
}
ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
const uint8_t *current = (const uint8_t *)ptr;
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
while (get_uart_rx_tx_reg_tx_free(uart) == 0)
;
uart_write(uart, current[jj]);
if (current[jj] == '\n') {
while (get_uart_rx_tx_reg_tx_free(uart) == 0)
;
uart_write(uart, '\r');
}
#elif defined(BOARD_iss)
*((uint32_t*) 0xFFFF0000) = current[jj];
#elif defined(BOARD_TGCP)
//TODO: implement
#else
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
UART0_REG(UART_REG_TXFIFO) = current[jj];
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = current[jj];
if (current[jj] == '\n') {
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
UART0_REG(UART_REG_TXFIFO) = '\r';
}
if (current[jj] == '\n') {
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;
UART0_REG(UART_REG_TXFIFO) = '\r';
}
#endif
}
return len;
}
return len;
}
return _stub(EBADF);
return _stub(EBADF);
}
weak_under_alias(write);