18 Commits

Author SHA1 Message Date
339d6b0f2c updates bsp 2025-03-14 12:01:16 +01:00
36cb401420 updates BSP and adds options to specify link target 2025-03-07 19:32:14 +01:00
f3dc9aea54 adds wrap for scanf in dhrystone 2024-08-28 18:13:40 +02:00
2f675e9bdd fixes tgc_vp setup in coremark 2024-06-30 17:26:58 +02:00
3114cb265a Merge remote-tracking branch 'origin/main' into develop 2024-06-30 07:54:36 +02:00
48cfa8d868 appendage 2024-06-17 19:04:12 +02:00
64d6045d43 expands README 2024-06-17 19:04:05 +02:00
765f48e85a fixes target naming 2024-06-14 20:46:09 +02:00
1ce18ee1f6 serialzes FW build in cmake build flow 2024-06-14 17:34:53 +02:00
b4a3a36b2e cleans up Makefile 2024-06-14 12:05:55 +00:00
2a541997a4 benchmarks/dhrystone/Makefile aktualisiert 2024-06-14 13:50:22 +02:00
70d94c1051 CMakeLists.txt aktualisiert 2024-06-14 13:38:31 +02:00
0df111f945 cleans up CMakeLists 2024-06-14 10:11:30 +02:00
9105f5fb14 update include paths 2024-05-31 08:55:49 +02:00
4cc156e0d0 Merge branch 'main' of https://git.minres.com/Firmware/Firmwares into main 2024-04-30 08:46:13 +02:00
fca9f04264 Merge remote-tracking branch 'origin/main' into develop 2024-03-20 12:29:57 +01:00
5955f54a4d first semihosting integration 2024-02-26 20:41:13 +01:00
fe1136c7ce fixes ISA handling 2023-12-06 10:00:33 +01:00
7 changed files with 38 additions and 20 deletions

3
.gitignore vendored
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@ -151,3 +151,6 @@ compile_commands.json
CTestTestfile.cmake
*.dump
.vscode/c_cpp_properties.json
semihosting_test/build/semihosting_test
semihosting_test/build/Makefile

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@ -4,16 +4,11 @@ endif()
if (NOT DEFINED ISA)
set(ISA imc)
endif()
message(STATUS "Building firmware using ${BOARD} board configuration")
add_custom_target(fw-hello-world ALL
COMMAND make -C ${riscvfw_SOURCE_DIR}/hello-world BOARD=${BOARD} ISA=${ISA}
USES_TERMINAL
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
add_custom_target(fw-dhrystone ALL
COMMAND make -C ${riscvfw_SOURCE_DIR}/benchmarks/dhrystone BOARD=${BOARD} ISA=${ISA}
USES_TERMINAL
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
add_custom_target(fw-coremark ALL
COMMAND make -C ${riscvfw_SOURCE_DIR}/benchmarks/coremark BOARD=${BOARD} ISA=${ISA}
if(DEFINED LINK_TARGET)
set(LNK LINK_TARGET=${LINK_TARGET})
endif()
message(STATUS "Building firmware using ${BOARD} board configuration and isa ${ISA}")
add_custom_target(fw-common ALL
COMMAND make -C hello-world BOARD=${BOARD} ISA=${ISA} ${LNK} && make -C benchmarks/dhrystone BOARD=${BOARD} ISA=${ISA} ${LNK} && make -C benchmarks/coremark BOARD=${BOARD} ISA=${ISA} ${LNK}
USES_TERMINAL
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})

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@ -1,3 +1,25 @@
# Firmware
# MINRES Firmware Repository
## Structure
This repository comes with several executables ready to be built, such as `hello-world` or `coremark` and `dhrystone` in the `benchmark` directory.
Creating the executables in the easiest way possible is done by calling `make`in the corresponding directory.
Using `make clean && bear -- make ` will cause a correct compile_commands.json to be emitted. This allows using completion tools like clangd.
## Prerequisite
This repository requires `riscv64-unknown-elf-gcc` to be located in `$PATH`.
## How to Use
When compiling executables, the target platform needs to be specified using the 'BOARD' variable. When compiling for the TGC5C for example, use `make BOARD=tgc_vp`, when compiling for RTL `make BOARD=rtl`. The default value for the Board variable is 'iss'.
The arch can be set with the 'ISA' variable, the default value is 'imc'.
When compiling for the TGC5A VP for example, the call to create the correct binary is the following:
```
make BOARD=tgc_vp ISA=e
```
## Useful information
Using `bear -- <build-command>` will cause a compile_commands.json to be emitted. This allows using completion tools like clangd.
## Current Limitations
Currently, this repository only supports creation of 32-bit executables (Even when setting the `RISCV_ARCH` and `RISCV_ABI` manually).
Compiling for the 'e' extension / ISA together with any other extension (`ISA=emc` for example), requires setting the `RISCV_ABI=ilp32e` explicitly.
When switching ABI or ARCH ensure that object files in the corresponding 'env' dir in the 'bare-metal-bsp' submodule are removed, so they get created with the appropriate flags (namely the 'init.o' file).

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@ -664,7 +664,7 @@ ee_vsprintf(char *buf, const char *fmt, va_list args)
void
uart_send_char(char c)
{
#if defined(BOARD_ehrenberg)
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
while (get_uart_rx_tx_reg_tx_free(uart)==0) ;
uart_write(uart, c);
if (c == '\n') {

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@ -9,16 +9,15 @@ HEADERS := dhry.h
BOARD?=iss
LINK_TARGET=link
RISCV_ARCH:=rv32$(ISA)
ifeq ($(ISA),e)
ifneq (,$(findstring e,$(ISA)))
RISCV_ABI:=ilp32e
else
RISCV_ABI:=ilp32
endif
# '-lgcc -lm' are needed to add softfloat routines
CFLAGS := -g -march=$(RISCV_ARCH)_zicsr_zifencei -mabi=$(RISCV_ABI) -mcmodel=medlow -O3 -DITERATIONS=$(ITERATIONS) -DHZ=32768 -DTIME -DNO_INIT -fno-inline -fno-builtin-printf -fno-common -Wno-implicit \
CFLAGS := -g -O3 -DITERATIONS=$(ITERATIONS) -DHZ=32768 -DTIME -DNO_INIT -fno-inline -fno-builtin-printf -fno-common -Wno-implicit \
-funroll-loops -fpeel-loops -fgcse-sm -fgcse-las
LDFLAGS := -g -march=$(RISCV_ARCH)_zicsr_zifencei -mabi=$(RISCV_ABI) -mcmodel=medlow -Wl,--wrap=scanf -Wl,--wrap=printf -Wl,--wrap=exit -lgcc -lm
LDFLAGS := -Wl,--wrap=scanf
TOOL_DIR=$(dir $(compiler))
BSP_BASE = ../../bare-metal-bsp

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@ -1,4 +1,3 @@
TARGET = hello
ISA?=imc