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ac45dc11a3
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fixes dhrystone make settings
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2025-02-14 11:30:57 +01:00 |
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ea32dd9ce3
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adds BOARD_tgc_vp check to coremark send_char
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2025-01-07 22:31:46 +01:00 |
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b4a3a36b2e
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cleans up Makefile
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2024-06-14 12:05:55 +00:00 |
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2a541997a4
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benchmarks/dhrystone/Makefile aktualisiert
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2024-06-14 13:50:22 +02:00 |
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877672a5a4
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fixes iterations count for benchmarks
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2024-03-25 10:56:34 +01:00 |
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45b6f24dfc
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changes coremark build system to use BSP
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2024-03-24 21:19:16 +01:00 |
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749fab2c01
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WIP
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2024-03-24 19:16:24 +01:00 |
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70ee11ad3d
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fixes coremark linker setting
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2024-03-21 07:32:20 +01:00 |
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a04e6d3c5b
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fixes TGCP settings in coremark port
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2024-03-20 12:53:35 +01:00 |
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06add2e20d
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reduces dhrystone iterations to 20000 for reasonable RTL sim times
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2024-03-20 12:24:57 +01:00 |
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2fb5920348
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updates coremark portable part to match BSP
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2024-03-20 11:55:48 +01:00 |
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6d33d0b066
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fixes wrone use of bsp in coremark
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2024-03-20 07:46:42 +01:00 |
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d5c672c288
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updates coremark build system to use BSP definitions
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2024-03-20 07:40:21 +01:00 |
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3381b01ec1
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replaces bare-metal-bsp with submodule
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2024-01-13 15:37:10 +01:00 |
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51c8a93336
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fixes march definitions for dhrystone and coremark
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2023-12-09 16:38:45 +01:00 |
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6ff0161882
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adds some consistency fixes for variable ISA settings
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2023-12-02 17:41:14 +01:00 |
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63f57b9ba1
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extends eclipse build configs
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2023-10-26 06:11:12 +02:00 |
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af3a154882
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adds tgc-vp environment
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2023-10-25 20:35:44 +02:00 |
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9c0047b3ea
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updates linker script for rtl env
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2023-08-30 15:07:56 +02:00 |
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ca1adccb2b
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fixes TGC5L settings
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2023-08-28 10:01:06 +02:00 |
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3a3cbf38c3
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re-adds coremark as submodule
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2023-08-20 15:23:05 +02:00 |
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822696ae0d
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cleanup
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2023-08-20 15:20:39 +02:00 |
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314ceeb072
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rework structure
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2023-08-20 15:00:51 +02:00 |
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