Firmware
/
Firmwares
9
0
Fork 1
Code Issues Pull Requests Releases Wiki Activity

fixes coremark linker setting

This commit is contained in:
Eyck Jentzsch 2024-03-21 07:32:20 +01:00
parent a04e6d3c5b
commit 70ee11ad3d
3 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bare-metal-bsp

@ -1 +1 @@
Subproject commit 4d25972e4dd8f0053cc4fbd88be1b85f4b869cae
Subproject commit 33898756434cc490557540dadbfc9bf1f0626d4d

4
benchmarks/coremark/tgc/core_portme.mak
View File

@ -25,6 +25,7 @@ else
RISCV_ABI:=ilp32
endif
BSP_BASE = ../../../bare-metal-bsp
LINKER_SCRIPT=link.lds
TRIPLET?=riscv64-unknown-elf
# Flag : OUTFLAG
@ -58,7 +59,8 @@ ASFLAGS =
OFLAG = -o
COUT = -c
LFLAGS_END =
LFLAGS_END = -T $(BSP_BASE)/env/$(BOARD)/$(LINKER_SCRIPT)
# Flag : PORT_SRCS
# Port specific source files can be added here
# You may also need cvt.c if the fcvt functions are not provided as intrinsics by your compiler!

2
benchmarks/dhrystone/Makefile
View File

@ -5,7 +5,7 @@ ASM_SRCS :=
C_SRCS := dhry_stubs.c dhry_1.c dhry_2.c
HEADERS := dhry.h
BOARD=iss
BOARD?=iss
LINK_TARGET=link
RISCV_ARCH:=rv32$(ISA)
ifeq ($(ISA),e)