update definitions of derived constants

integrate code generation into build process (first attempt)
first version of tgf_c based on CoreDSL 2.0
2021-01-01 09:19:48 +00:00 · 2020-12-30 07:29:52 +00:00 · 2020-12-29 08:48:22 +00:00 · 2020-12-23 16:24:10 +00:00
10 changed files with 2642 additions and 3011 deletions
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.12)

-project("riscv" VERSION 1.0.0)
+project("tgfs" VERSION 1.0.0)

 include(GNUInstallDirs)

@@ -28,7 +28,7 @@ add_subdirectory(softfloat)

 # library files
 FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h)
-set(LIB_HEADERS ${RiscVSCHeaders} )
+set(LIB_HEADERS tgfscVSCHeaders} )
 set(LIB_SOURCES 
 	src/iss/tgf_b.cpp
 	src/iss/tgf_c.cpp
@@ -49,56 +49,58 @@ set(LIB_SOURCES ${LIB_SOURCES}
 endif()

 # Define the library
-add_library(riscv SHARED ${LIB_SOURCES})
-target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
-target_include_directories(riscv PUBLIC incl ../external/elfio)
-target_link_libraries(riscv PUBLIC softfloat scc-util)
-target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
-set_target_properties(riscv PROPERTIES
+add_library(tgfs SHARED ${LIB_SOURCES})
+# list code gen dependencies
+add_dependencies(tgfs TGF_C_src)
+
+target_compile_options(tgfs PRIVATE -Wno-shift-count-overflow)
+target_include_directories(tgfs PUBLIC incl)
+target_link_libraries(tgfs PUBLIC softfloat scc-util)
+target_link_libraries(tgfs PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
+set_target_properties(tgfs PROPERTIES
  VERSION ${PROJECT_VERSION}
  FRAMEWORK FALSE
  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
 )

 if(SystemC_FOUND)
-	add_library(riscv_sc src/sysc/core_complex.cpp)
-	target_compile_definitions(riscv_sc PUBLIC WITH_SYSTEMC) 
-	target_include_directories(riscv_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
+	add_library(tgfs_sc src/sysc/core_complex.cpp)
+	target_compile_definitions(tgfs_sc PUBLIC WITH_SYSTEMC) 
+	target_include_directories(tgfs_sc PUBLIC ../incl ${SystemC_INCLUDE_DIRS} ${CCI_INCLUDE_DIRS})
 	
 	if(SCV_FOUND)   
-	    target_compile_definitions(riscv_sc PUBLIC WITH_SCV)
-	    target_include_directories(riscv_sc PUBLIC ${SCV_INCLUDE_DIRS})
+	    target_compile_definitions(tgfs_sc PUBLIC WITH_SCV)
+	    target_include_directories(tgfs_sc PUBLIC ${SCV_INCLUDE_DIRS})
 	endif()
-	target_link_libraries(riscv_sc PUBLIC riscv scc )
+	target_link_libraries(tgfs_sc PUBLIC tgfs scc )
 	if(WITH_LLVM)
-		target_link_libraries(riscv_sc PUBLIC ${llvm_libs})
+		target_link_libraries(tgfs_sc PUBLIC ${llvm_libs})
 	endif()
-	target_link_libraries(riscv_sc PUBLIC ${Boost_LIBRARIES} )
-	set_target_properties(riscv_sc PROPERTIES
+	target_link_libraries(tgfs_sc PUBLIC ${Boost_LIBRARIES} )
+	set_target_properties(tgfs_sc PROPERTIES
 	  VERSION ${PROJECT_VERSION}
 	  FRAMEWORK FALSE
 	  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
 	)
 endif()

-project("riscv-sim")
-add_executable(riscv-sim src/main.cpp)
+project("tgfs-sim")
+add_executable(tgfs-sim src/main.cpp)
 # This sets the include directory for the reference project. This is the -I flag in gcc.
-target_include_directories(riscv-sim PRIVATE ../external/libGIS)
+
 if(WITH_LLVM)
-	target_compile_definitions(riscv-sim PRIVATE WITH_LLVM)
-	target_link_libraries(riscv-sim PUBLIC ${llvm_libs})
+	target_compile_definitions(tgfs-sim PRIVATE WITH_LLVM)
+	target_link_libraries(tgfs-sim PUBLIC ${llvm_libs})
 endif()
 # Links the target exe against the libraries
-target_link_libraries(riscv-sim riscv)
-target_link_libraries(riscv-sim jsoncpp)
-target_link_libraries(riscv-sim external)
-target_link_libraries(riscv-sim ${Boost_LIBRARIES} )
+target_link_libraries(tgfs-sim tgfs)
+target_link_libraries(tgfs-sim jsoncpp)
+target_link_libraries(tgfs-sim ${Boost_LIBRARIES} )
 if (Tcmalloc_FOUND)
-    target_link_libraries(riscv-sim ${Tcmalloc_LIBRARIES})
+    target_link_libraries(tgfs-sim ${Tcmalloc_LIBRARIES})
 endif(Tcmalloc_FOUND)

-install(TARGETS riscv riscv-sim
+install(TARGETS tgfs tgfs-sim
  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} COMPONENT libs   # binaries
--- a/gen_input/CoreDSL-Instruction-Set-Description
+++ b/gen_input/CoreDSL-Instruction-Set-Description
--- a/gen_input/TGFS.core_desc
+++ b/gen_input/TGFS.core_desc
@@ -4,25 +4,24 @@ import "CoreDSL-Instruction-Set-Description/RVC.core_desc"

 Core TGF_B provides RV32I {
 	constants {
-        XLEN:=32;
-        PCLEN:=32;
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
        // definitions for the architecture wrapper
        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000000000000000100000000;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
+        unsigned MISA_VAL=0b01000000000000000000000100000000;
+        unsigned PGSIZE = 0x1000; //1 << 12;
+        unsigned PGMASK = 0xfff; //PGSIZE-1
 	}
 }

 Core TGF_C provides RV32I, RV32M, RV32IC {
    constants {
-        XLEN:=32;
-        PCLEN:=32;
-        MUL_LEN:=64;
+        unsigned XLEN=32;
+        unsigned PCLEN=32;
        // definitions for the architecture wrapper
        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000000000001000100000100;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
+        unsigned MISA_VAL=0b01000000000000000001000100000100;
+        unsigned PGSIZE = 0x1000; //1 << 12;
+        unsigned PGMASK = 0xfff; //PGSIZE-1
    }
 }
--- a/gen_input/minres_rv.core_desc
+++ b/gen_input/minres_rv.core_desc
@@ -1,74 +0,0 @@
-import "RV32I.core_desc"
-import "RV64I.core_desc"
-import "RVM.core_desc"
-import "RVA.core_desc"
-import "RVC.core_desc"
-import "RVF.core_desc"
-import "RVD.core_desc"
-
-
-Core MNRV32 provides RV32I, RV32IC {
-    constants {
-        XLEN:=32;
-        PCLEN:=32;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100000101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
-    constants {
-        XLEN:=32;
-        PCLEN:=32;
-        MUL_LEN:=64;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100000101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
-    constants {
-        XLEN:=32;
-        FLEN:=64;
-        PCLEN:=32;
-        MUL_LEN:=64;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100101101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV64I provides RV64I {
-    constants {
-        XLEN:=64;
-        PCLEN:=64;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b10000000000001000000000100000000;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
-Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV32FC, RV32DC, RV64IC {
-    constants {
-        XLEN:=64;
-        FLEN:=64;
-        PCLEN:=64;
-        MUL_LEN:=128;
-        // definitions for the architecture wrapper
-        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        MISA_VAL:=0b01000000000101000001000100101101;
-        PGSIZE := 0x1000; //1 << 12;
-        PGMASK := 0xfff; //PGSIZE-1
-    }
-}
-
--- a/gen_input/templates/interp/src-CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/src-CORENAME.cpp.gtl
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -29,45 +29,7 @@
 * POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************/
- <% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
+
 #include "util/ities.h"
 #include <util/logging.h>
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
@@ -77,10 +39,10 @@ def getRegisterAliasNames(){

 using namespace iss::arch;

-constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
-constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
-constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
-constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;

 ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
    reg.icount = 0;
--- a/gen_input/templates/interp/incl-CORENAME.h.gtl
+++ b/gen_input/templates/interp/incl-CORENAME.h.gtl
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -30,48 +30,6 @@
 *
 *******************************************************************************/

-<% 
-import com.minres.coredsl.coreDsl.Register
-import com.minres.coredsl.coreDsl.RegisterFile
-import com.minres.coredsl.coreDsl.RegisterAlias
-def getTypeSize(size){
-	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
-}
-def getOriginalName(reg){
-    if( reg.original instanceof RegisterFile) {
-    	if( reg.index != null ) {
-        	return reg.original.name+generator.generateHostCode(reg.index)
-        } else {
-        	return reg.original.name
-        }
-    } else if(reg.original instanceof Register){
-        return reg.original.name
-    }
-}
-def getRegisterNames(){
-	def regNames = []
- 	allRegs.each { reg -> 
-		if( reg instanceof RegisterFile) {
-			(reg.range.right..reg.range.left).each{
-    			regNames+=reg.name.toLowerCase()+it
-            }
-        } else if(reg instanceof Register){
-    		regNames+=reg.name.toLowerCase()
-        }
-    }
-    return regNames
-}
-def getRegisterAliasNames(){
-	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
- 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
-		if( reg instanceof RegisterFile) {
-			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
-        } else if(reg instanceof Register){
-    		regMap[reg.name]?:reg.name.toLowerCase()
-        }
- 	}.flatten()
-}
-%>
 #ifndef _${coreDef.name.toUpperCase()}_H_
 #define _${coreDef.name.toUpperCase()}_H_

@@ -89,25 +47,19 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {

 	constexpr static char const* const core_type = "${coreDef.name}";
    
-  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
- 		{"${getRegisterNames().join("\", \"")}"}};
+  	static constexpr std::array<const char*, ${registers.size}> reg_names{
+ 		{"${registers.collect{it.name}.join('", "')}"}};
 
-  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
- 		{"${getRegisterAliasNames().join("\", \"")}"}};
+  	static constexpr std::array<const char*, ${registers.size}> reg_aliases{
+ 		{"${registers.collect{it.alias}.join('", "')}"}};

-    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
+    enum constants {${constants.collect{c -> c.name+"="+c.value}.join(', ')}};

-    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
+    constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};

    enum reg_e {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        ${reg.name}${it},<%
-                }
-            } else if(reg instanceof Register){ %>
+     	registers.each { reg -> %>
        ${reg.name},<%  
-            }
        }%>
        NUM_REGS,
        NEXT_${pc.name}=NUM_REGS,
@@ -115,15 +67,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
        PENDING_TRAP,
        MACHINE_STATE,
        LAST_BRANCH,
-        ICOUNT<% 
-     	allRegs.each { reg -> 
-    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
-        ${reg.name} = ${aliasname}<%
-            }
-        }%>
+        ICOUNT
    };

-    using reg_t = uint${regDataWidth}_t;
+    using reg_t = uint${addrDataWidth}_t;

    using addr_t = uint${addrDataWidth}_t;

@@ -133,17 +80,17 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {

    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;

- 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
- 		{${regSizes.join(",")}}};
+ 	static constexpr std::array<const uint32_t, ${registers.size}> reg_bit_widths{
+ 		{${registers.collect{it.size}.join(',')}}};

-    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
-    	{${regOffsets.join(",")}}};
+    static constexpr std::array<const uint32_t, ${registers.size}> reg_byte_offsets{
+ 		{${registers.collect{it.offset}.join(',')}}};

    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);

    enum sreg_flag_e { FLAGS };

-    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
+    enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
 };

 struct ${coreDef.name.toLowerCase()}: public arch_if {
@@ -190,16 +137,10 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {

 protected:
    struct ${coreDef.name}_regs {<%
-     	allRegs.each { reg -> 
-    		if( reg instanceof RegisterFile) {
-    			(reg.range.right..reg.range.left).each{%>
-        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
-                }
-            } else if(reg instanceof Register){ %>
-        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
-            }
+     	registers.each { reg ->%> 
+        uint${reg.size}_t ${reg.name} = 0;<%
        }%>
-        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
+        uint${pc.size}_t NEXT_${pc.name} = 0;
        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
        uint64_t icount = 0;
    } reg;
@@ -208,10 +149,10 @@ protected:
    
    uint64_t interrupt_sim=0;
 <%
-def fcsr = allRegs.find {it.name=='FCSR'}
+def fcsr = registers.find {it.name=='FCSR'}
 if(fcsr != null) {%>
-	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
-	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
+	uint${fcsr.size}_t get_fcsr(){return reg.FCSR;}
+	void set_fcsr(uint${fcsr.size}_t val){reg.FCSR = val;}		
 <%} else { %>
 	uint32_t get_fcsr(){return 0;}
 	void set_fcsr(uint32_t val){}
--- a/gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/vm-vm_CORENAME.cpp.gtl
@@ -56,13 +56,14 @@ using namespace iss::debugger;

 template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
 public:
-    using super = typename iss::interp::vm_base<ARCH>;
+    using traits = arch::traits<ARCH>;
+    using super       = typename iss::interp::vm_base<ARCH>;
    using virt_addr_t = typename super::virt_addr_t;
    using phys_addr_t = typename super::phys_addr_t;
    using code_word_t = typename super::code_word_t;
-    using addr_t = typename super::addr_t;
-    using reg_t = typename traits<ARCH>::reg_t;
-    using iss::interp::vm_base<ARCH>::get_reg;
+    using addr_t      = typename super::addr_t;
+    using reg_t       = typename traits::reg_t;
+    using mem_type_e  = typename traits::mem_type_e;

    vm_impl();

@@ -82,7 +83,7 @@ protected:
    using compile_ret_t = virt_addr_t;
    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);

-    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}

    virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;

@@ -138,23 +139,31 @@ protected:
        return lut_val;
    }

-    void raise_trap(uint16_t trap_id, uint16_t cause){
+    void raise(uint16_t trap_id, uint16_t cause){
        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE) = trap_val;
-        this->template get_reg<uint32_t>(arch::traits<ARCH>::NEXT_PC) = std::numeric_limits<uint32_t>::max();
+        this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
+        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
    }

-    void leave_trap(unsigned lvl){
+    void leave(unsigned lvl){
        this->core.leave_trap(lvl);
-        auto pc_val = super::template read_mem<reg_t>(traits<ARCH>::CSR, (lvl << 8) + 0x41);
-        this->template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc_val;
-        this->template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
+        auto pc_val = super::template read_mem<reg_t>(traits::CSR, (lvl << 8) + 0x41);
+        this->template get_reg<reg_t>(traits::NEXT_PC) = pc_val;
+        this->template get_reg<uint32_t>(traits::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
    }

    void wait(unsigned type){
        this->core.wait_until(type);
    }

+    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint8_t>(space, addr);}
+    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint16_t>(space, addr);}
+    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint32_t>(space, addr);}
+    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint64_t>(space, addr);}
+    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){super::write_mem(space, addr, data);}
+    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){super::write_mem(space, addr, data);}
+    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){super::write_mem(space, addr, data);}
+    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){super::write_mem(space, addr, data);}

 private:
    /****************************************************************************
@@ -170,13 +179,33 @@ private:
    const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
         /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
    }};
 
    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
    /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){<%instr.code.eachLine{%>
-        ${it}<%}%>
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
+		this->do_sync(PRE_SYNC, ${idx});
+		<%instr.fields.eachLine{%>${it}
+		<%}%>if(this->disass_enabled){
+		    /* generate console output when executing the command */
+			<%instr.disass.eachLine{%>${it}
+		<%}%>}
+		auto cur_pc_val = pc.val;
+		super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = cur_pc_val + ${instr.length/8};
+		uint${addrDataWidth}_t* X = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::X0);
+		uint${addrDataWidth}_t* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::PC);
+		<%instr.behavior.eachLine{%>${it}
+		<%}%>this->do_sync(POST_SYNC, ${idx});
+		auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
+		// trap check
+		if(trap_state!=0){
+		    auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
+		    last_br = std::numeric_limits<uint32_t>::max();
+		    super::core.enter_trap(trap_state, cur_pc_val);
+		}
+		pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
+		return pc;
    }
    <%}%>
    /****************************************************************************
@@ -212,7 +241,7 @@ template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
    // we fetch at max 4 byte, alignment is 2
    enum {TRAP_ID=1<<16};
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    const typename traits::addr_t upper_bits = ~traits::PGMASK;
    code_word_t insn = 0;
    auto *const data = (uint8_t *)&insn;
    auto pc=start;
--- a/incl/iss/arch/tgf_c.h
+++ b/incl/iss/arch/tgf_c.h
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -30,7 +30,6 @@
 *
 *******************************************************************************/

-
 #ifndef _TGF_C_H_
 #define _TGF_C_H_

@@ -49,12 +48,12 @@ template <> struct traits<tgf_c> {
 	constexpr static char const* const core_type = "TGF_C";
    
  	static constexpr std::array<const char*, 33> reg_names{
- 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
+ 		{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC"}};
 
  	static constexpr std::array<const char*, 33> reg_aliases{
- 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
+ 		{"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC"}};

-    enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff};
+    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};

    constexpr static unsigned FP_REGS_SIZE = 0;

@@ -98,39 +97,7 @@ template <> struct traits<tgf_c> {
        PENDING_TRAP,
        MACHINE_STATE,
        LAST_BRANCH,
-        ICOUNT,
-        ZERO = X0,
-        RA = X1,
-        SP = X2,
-        GP = X3,
-        TP = X4,
-        T0 = X5,
-        T1 = X6,
-        T2 = X7,
-        S0 = X8,
-        S1 = X9,
-        A0 = X10,
-        A1 = X11,
-        A2 = X12,
-        A3 = X13,
-        A4 = X14,
-        A5 = X15,
-        A6 = X16,
-        A7 = X17,
-        S2 = X18,
-        S3 = X19,
-        S4 = X20,
-        S5 = X21,
-        S6 = X22,
-        S7 = X23,
-        S8 = X24,
-        S9 = X25,
-        S10 = X26,
-        S11 = X27,
-        T3 = X28,
-        T4 = X29,
-        T5 = X30,
-        T6 = X31
+        ICOUNT
    };

    using reg_t = uint32_t;
@@ -143,11 +110,11 @@ template <> struct traits<tgf_c> {

    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;

- 	static constexpr std::array<const uint32_t, 39> reg_bit_widths{
- 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
+ 	static constexpr std::array<const uint32_t, 33> reg_bit_widths{
+ 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32}};

-    static constexpr std::array<const uint32_t, 40> reg_byte_offsets{
-    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}};
+    static constexpr std::array<const uint32_t, 33> reg_byte_offsets{
+ 		{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128}};

    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);

@@ -199,39 +166,39 @@ struct tgf_c: public arch_if {
    inline uint32_t get_last_branch() { return reg.last_branch; }

 protected:
-    struct TGF_C_regs {
-        uint32_t X0 = 0;
-        uint32_t X1 = 0;
-        uint32_t X2 = 0;
-        uint32_t X3 = 0;
-        uint32_t X4 = 0;
-        uint32_t X5 = 0;
-        uint32_t X6 = 0;
-        uint32_t X7 = 0;
-        uint32_t X8 = 0;
-        uint32_t X9 = 0;
-        uint32_t X10 = 0;
-        uint32_t X11 = 0;
-        uint32_t X12 = 0;
-        uint32_t X13 = 0;
-        uint32_t X14 = 0;
-        uint32_t X15 = 0;
-        uint32_t X16 = 0;
-        uint32_t X17 = 0;
-        uint32_t X18 = 0;
-        uint32_t X19 = 0;
-        uint32_t X20 = 0;
-        uint32_t X21 = 0;
-        uint32_t X22 = 0;
-        uint32_t X23 = 0;
-        uint32_t X24 = 0;
-        uint32_t X25 = 0;
-        uint32_t X26 = 0;
-        uint32_t X27 = 0;
-        uint32_t X28 = 0;
-        uint32_t X29 = 0;
-        uint32_t X30 = 0;
-        uint32_t X31 = 0;
+    struct TGF_C_regs { 
+        uint32_t X0 = 0; 
+        uint32_t X1 = 0; 
+        uint32_t X2 = 0; 
+        uint32_t X3 = 0; 
+        uint32_t X4 = 0; 
+        uint32_t X5 = 0; 
+        uint32_t X6 = 0; 
+        uint32_t X7 = 0; 
+        uint32_t X8 = 0; 
+        uint32_t X9 = 0; 
+        uint32_t X10 = 0; 
+        uint32_t X11 = 0; 
+        uint32_t X12 = 0; 
+        uint32_t X13 = 0; 
+        uint32_t X14 = 0; 
+        uint32_t X15 = 0; 
+        uint32_t X16 = 0; 
+        uint32_t X17 = 0; 
+        uint32_t X18 = 0; 
+        uint32_t X19 = 0; 
+        uint32_t X20 = 0; 
+        uint32_t X21 = 0; 
+        uint32_t X22 = 0; 
+        uint32_t X23 = 0; 
+        uint32_t X24 = 0; 
+        uint32_t X25 = 0; 
+        uint32_t X26 = 0; 
+        uint32_t X27 = 0; 
+        uint32_t X28 = 0; 
+        uint32_t X29 = 0; 
+        uint32_t X30 = 0; 
+        uint32_t X31 = 0; 
        uint32_t PC = 0;
        uint32_t NEXT_PC = 0;
        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
--- a/src/iss/tgf_c.cpp
+++ b/src/iss/tgf_c.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017 - 2020 MINRES Technologies GmbH
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
@@ -29,7 +29,7 @@
 * POSSIBILITY OF SUCH DAMAGE.
 *
 *******************************************************************************/
- 
+
 #include "util/ities.h"
 #include <util/logging.h>
 #include <iss/arch/tgf_c.h>
@@ -41,8 +41,8 @@ using namespace iss::arch;

 constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_c>::reg_names;
 constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::tgf_c>::reg_aliases;
-constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;
+constexpr std::array<const uint32_t, 33> iss::arch::traits<iss::arch::tgf_c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 33> iss::arch::traits<iss::arch::tgf_c>::reg_byte_offsets;

 tgf_c::tgf_c() {
    reg.icount = 0;
--- a/src/vm/interp/vm_tgf_c.cpp
+++ b/src/vm/interp/vm_tgf_c.cpp
Author	SHA1	Message	Date
eyck	da7e29fbb7	update definitions of derived constants	2021-01-01 09:19:48 +00:00
eyck	c4da47cedd	integrate code generation into build process (first attempt)	2020-12-30 07:29:52 +00:00
eyck	ab554539e3	first version of tgf_c based on CoreDSL 2.0	2020-12-29 08:48:22 +00:00
eyck	d43b35949e	fix CMakeList.txt so that it builds without platform and external libs	2020-12-23 16:24:10 +00:00