Compare commits
9 Commits
ffe730219d
...
2115e9ceae
| Author | SHA1 | Date | |
|---|---|---|---|
| 2115e9ceae | |||
| 2bea95c1a7 | |||
| 7001b693ae | |||
| e6f11081eb | |||
| 09db0cd35d | |||
| 980c8031c3 | |||
| b86d7a517d | |||
| b7478965ab | |||
| bf4a6deb86 |
@ -27,84 +27,84 @@ RV32I:
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
delay: [1,2]
|
||||
BEQ:
|
||||
index: 4
|
||||
encoding: 0b00000000000000000000000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
delay: [1,2]
|
||||
BNE:
|
||||
index: 5
|
||||
encoding: 0b00000000000000000001000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
delay: [1,2]
|
||||
BLT:
|
||||
index: 6
|
||||
encoding: 0b00000000000000000100000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
delay: [1,2]
|
||||
BGE:
|
||||
index: 7
|
||||
encoding: 0b00000000000000000101000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
delay: [1,2]
|
||||
BLTU:
|
||||
index: 8
|
||||
encoding: 0b00000000000000000110000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
delay: [1,2]
|
||||
BGEU:
|
||||
index: 9
|
||||
encoding: 0b00000000000000000111000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
delay: [1,2]
|
||||
LB:
|
||||
index: 10
|
||||
encoding: 0b00000000000000000000000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
LH:
|
||||
index: 11
|
||||
encoding: 0b00000000000000000001000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
LW:
|
||||
index: 12
|
||||
encoding: 0b00000000000000000010000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
LBU:
|
||||
index: 13
|
||||
encoding: 0b00000000000000000100000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
LHU:
|
||||
index: 14
|
||||
encoding: 0b00000000000000000101000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
SB:
|
||||
index: 15
|
||||
encoding: 0b00000000000000000000000000100011
|
||||
@ -356,56 +356,56 @@ RV32M:
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
MULH:
|
||||
index: 50
|
||||
encoding: 0b00000010000000000001000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
MULHSU:
|
||||
index: 51
|
||||
encoding: 0b00000010000000000010000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
MULHU:
|
||||
index: 52
|
||||
encoding: 0b00000010000000000011000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
DIV:
|
||||
index: 53
|
||||
encoding: 0b00000010000000000100000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 17
|
||||
DIVU:
|
||||
index: 54
|
||||
encoding: 0b00000010000000000101000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 17
|
||||
REM:
|
||||
index: 55
|
||||
encoding: 0b00000010000000000110000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 17
|
||||
REMU:
|
||||
index: 56
|
||||
encoding: 0b00000010000000000111000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 17
|
||||
Zca:
|
||||
C__ADDI4SPN:
|
||||
index: 57
|
||||
@ -420,7 +420,7 @@ Zca:
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
C__SW:
|
||||
index: 59
|
||||
encoding: 0b1100000000000000
|
||||
@ -542,14 +542,14 @@ Zca:
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
delay: [1,2]
|
||||
C__BNEZ:
|
||||
index: 76
|
||||
encoding: 0b1110000000000001
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: true
|
||||
delay: [1,1]
|
||||
delay: [1,2]
|
||||
C__SLLI:
|
||||
index: 77
|
||||
encoding: 0b0000000000000010
|
||||
@ -564,7 +564,7 @@ Zca:
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
delay: 2
|
||||
C__MV:
|
||||
index: 79
|
||||
encoding: 0b1000000000000010
|
||||
|
||||
624
contrib/instr/TGC5C_slow.yaml
Normal file
624
contrib/instr/TGC5C_slow.yaml
Normal file
@ -0,0 +1,624 @@
|
||||
|
||||
RV32I:
|
||||
LUI:
|
||||
index: 0
|
||||
encoding: 0b00000000000000000000000000110111
|
||||
mask: 0b00000000000000000000000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
AUIPC:
|
||||
index: 1
|
||||
encoding: 0b00000000000000000000000000010111
|
||||
mask: 0b00000000000000000000000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
JAL:
|
||||
index: 2
|
||||
encoding: 0b00000000000000000000000001101111
|
||||
mask: 0b00000000000000000000000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: 1
|
||||
JALR:
|
||||
index: 3
|
||||
encoding: 0b00000000000000000000000001100111
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
BEQ:
|
||||
index: 4
|
||||
encoding: 0b00000000000000000000000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
BNE:
|
||||
index: 5
|
||||
encoding: 0b00000000000000000001000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
BLT:
|
||||
index: 6
|
||||
encoding: 0b00000000000000000100000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
BGE:
|
||||
index: 7
|
||||
encoding: 0b00000000000000000101000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
BLTU:
|
||||
index: 8
|
||||
encoding: 0b00000000000000000110000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
BGEU:
|
||||
index: 9
|
||||
encoding: 0b00000000000000000111000001100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
LB:
|
||||
index: 10
|
||||
encoding: 0b00000000000000000000000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 2
|
||||
LH:
|
||||
index: 11
|
||||
encoding: 0b00000000000000000001000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 2
|
||||
LW:
|
||||
index: 12
|
||||
encoding: 0b00000000000000000010000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 2
|
||||
LBU:
|
||||
index: 13
|
||||
encoding: 0b00000000000000000100000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 2
|
||||
LHU:
|
||||
index: 14
|
||||
encoding: 0b00000000000000000101000000000011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 2
|
||||
SB:
|
||||
index: 15
|
||||
encoding: 0b00000000000000000000000000100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
SH:
|
||||
index: 16
|
||||
encoding: 0b00000000000000000001000000100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
SW:
|
||||
index: 17
|
||||
encoding: 0b00000000000000000010000000100011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
ADDI:
|
||||
index: 18
|
||||
encoding: 0b00000000000000000000000000010011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
SLTI:
|
||||
index: 19
|
||||
encoding: 0b00000000000000000010000000010011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
SLTIU:
|
||||
index: 20
|
||||
encoding: 0b00000000000000000011000000010011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
XORI:
|
||||
index: 21
|
||||
encoding: 0b00000000000000000100000000010011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
ORI:
|
||||
index: 22
|
||||
encoding: 0b00000000000000000110000000010011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
ANDI:
|
||||
index: 23
|
||||
encoding: 0b00000000000000000111000000010011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
SLLI:
|
||||
index: 24
|
||||
encoding: 0b00000000000000000001000000010011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: "u_24:20"
|
||||
SRLI:
|
||||
index: 25
|
||||
encoding: 0b00000000000000000101000000010011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: "u_24:20"
|
||||
SRAI:
|
||||
index: 26
|
||||
encoding: 0b01000000000000000101000000010011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: "u_24:20"
|
||||
ADD:
|
||||
index: 27
|
||||
encoding: 0b00000000000000000000000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
SUB:
|
||||
index: 28
|
||||
encoding: 0b01000000000000000000000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
SLL:
|
||||
index: 29
|
||||
encoding: 0b00000000000000000001000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: "X_24:20"
|
||||
SLT:
|
||||
index: 30
|
||||
encoding: 0b00000000000000000010000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
SLTU:
|
||||
index: 31
|
||||
encoding: 0b00000000000000000011000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
XOR:
|
||||
index: 32
|
||||
encoding: 0b00000000000000000100000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
SRL:
|
||||
index: 33
|
||||
encoding: 0b00000000000000000101000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: "X_24:20"
|
||||
SRA:
|
||||
index: 34
|
||||
encoding: 0b01000000000000000101000000110011
|
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mask: 0b11111110000000000111000001111111
|
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size: 32
|
||||
branch: false
|
||||
delay: "X_24:20"
|
||||
OR:
|
||||
index: 35
|
||||
encoding: 0b00000000000000000110000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
AND:
|
||||
index: 36
|
||||
encoding: 0b00000000000000000111000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
FENCE:
|
||||
index: 37
|
||||
encoding: 0b00000000000000000000000000001111
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
ECALL:
|
||||
index: 38
|
||||
encoding: 0b00000000000000000000000001110011
|
||||
mask: 0b11111111111111111111111111111111
|
||||
attributes: [[name:no_cont]]
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
EBREAK:
|
||||
index: 39
|
||||
encoding: 0b00000000000100000000000001110011
|
||||
mask: 0b11111111111111111111111111111111
|
||||
attributes: [[name:no_cont]]
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
MRET:
|
||||
index: 40
|
||||
encoding: 0b00110000001000000000000001110011
|
||||
mask: 0b11111111111111111111111111111111
|
||||
attributes: [[name:no_cont]]
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
WFI:
|
||||
index: 41
|
||||
encoding: 0b00010000010100000000000001110011
|
||||
mask: 0b11111111111111111111111111111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
Zicsr:
|
||||
CSRRW:
|
||||
index: 42
|
||||
encoding: 0b00000000000000000001000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
CSRRS:
|
||||
index: 43
|
||||
encoding: 0b00000000000000000010000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
CSRRC:
|
||||
index: 44
|
||||
encoding: 0b00000000000000000011000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
CSRRWI:
|
||||
index: 45
|
||||
encoding: 0b00000000000000000101000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
CSRRSI:
|
||||
index: 46
|
||||
encoding: 0b00000000000000000110000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
CSRRCI:
|
||||
index: 47
|
||||
encoding: 0b00000000000000000111000001110011
|
||||
mask: 0b00000000000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
Zifencei:
|
||||
FENCE_I:
|
||||
index: 48
|
||||
encoding: 0b00000000000000000001000000001111
|
||||
mask: 0b00000000000000000111000001111111
|
||||
attributes: [[name:flush]]
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 1
|
||||
RV32M:
|
||||
MUL:
|
||||
index: 49
|
||||
encoding: 0b00000010000000000000000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 32
|
||||
MULH:
|
||||
index: 50
|
||||
encoding: 0b00000010000000000001000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 32
|
||||
MULHSU:
|
||||
index: 51
|
||||
encoding: 0b00000010000000000010000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 32
|
||||
MULHU:
|
||||
index: 52
|
||||
encoding: 0b00000010000000000011000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 32
|
||||
DIV:
|
||||
index: 53
|
||||
encoding: 0b00000010000000000100000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 33
|
||||
DIVU:
|
||||
index: 54
|
||||
encoding: 0b00000010000000000101000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 33
|
||||
REM:
|
||||
index: 55
|
||||
encoding: 0b00000010000000000110000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 33
|
||||
REMU:
|
||||
index: 56
|
||||
encoding: 0b00000010000000000111000000110011
|
||||
mask: 0b11111110000000000111000001111111
|
||||
size: 32
|
||||
branch: false
|
||||
delay: 33
|
||||
Zca:
|
||||
C__ADDI4SPN:
|
||||
index: 57
|
||||
encoding: 0b0000000000000000
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__LW:
|
||||
index: 58
|
||||
encoding: 0b0100000000000000
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 2
|
||||
C__SW:
|
||||
index: 59
|
||||
encoding: 0b1100000000000000
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__ADDI:
|
||||
index: 60
|
||||
encoding: 0b0000000000000001
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__NOP:
|
||||
index: 61
|
||||
encoding: 0b0000000000000001
|
||||
mask: 0b1110111110000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__JAL:
|
||||
index: 62
|
||||
encoding: 0b0010000000000001
|
||||
mask: 0b1110000000000011
|
||||
attributes: [[name:enable, value:1]]
|
||||
size: 16
|
||||
branch: true
|
||||
delay: 1
|
||||
C__LI:
|
||||
index: 63
|
||||
encoding: 0b0100000000000001
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__LUI:
|
||||
index: 64
|
||||
encoding: 0b0110000000000001
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__ADDI16SP:
|
||||
index: 65
|
||||
encoding: 0b0110000100000001
|
||||
mask: 0b1110111110000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
__reserved_clui:
|
||||
index: 66
|
||||
encoding: 0b0110000000000001
|
||||
mask: 0b1111000001111111
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__SRLI:
|
||||
index: 67
|
||||
encoding: 0b1000000000000001
|
||||
mask: 0b1111110000000011
|
||||
attributes: [[name:enable, value:1]]
|
||||
size: 16
|
||||
branch: false
|
||||
delay: "u_12:12*16+u_6:2"
|
||||
C__SRAI:
|
||||
index: 68
|
||||
encoding: 0b1000010000000001
|
||||
mask: 0b1111110000000011
|
||||
attributes: [[name:enable, value:1]]
|
||||
size: 16
|
||||
branch: false
|
||||
delay: "u_12:12*16+u_6:2"
|
||||
C__ANDI:
|
||||
index: 69
|
||||
encoding: 0b1000100000000001
|
||||
mask: 0b1110110000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__SUB:
|
||||
index: 70
|
||||
encoding: 0b1000110000000001
|
||||
mask: 0b1111110001100011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__XOR:
|
||||
index: 71
|
||||
encoding: 0b1000110000100001
|
||||
mask: 0b1111110001100011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__OR:
|
||||
index: 72
|
||||
encoding: 0b1000110001000001
|
||||
mask: 0b1111110001100011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__AND:
|
||||
index: 73
|
||||
encoding: 0b1000110001100001
|
||||
mask: 0b1111110001100011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__J:
|
||||
index: 74
|
||||
encoding: 0b1010000000000001
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: true
|
||||
delay: 1
|
||||
C__BEQZ:
|
||||
index: 75
|
||||
encoding: 0b1100000000000001
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
C__BNEZ:
|
||||
index: 76
|
||||
encoding: 0b1110000000000001
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: true
|
||||
delay: [1,2]
|
||||
C__SLLI:
|
||||
index: 77
|
||||
encoding: 0b0000000000000010
|
||||
mask: 0b1111000000000011
|
||||
attributes: [[name:enable, value:1]]
|
||||
size: 16
|
||||
branch: false
|
||||
delay: "u_12:12*16+u_6:2"
|
||||
C__LWSP:
|
||||
index: 78
|
||||
encoding: 0b0100000000000010
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 2
|
||||
C__MV:
|
||||
index: 79
|
||||
encoding: 0b1000000000000010
|
||||
mask: 0b1111000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__JR:
|
||||
index: 80
|
||||
encoding: 0b1000000000000010
|
||||
mask: 0b1111000001111111
|
||||
size: 16
|
||||
branch: true
|
||||
delay: 1
|
||||
__reserved_cmv:
|
||||
index: 81
|
||||
encoding: 0b1000000000000010
|
||||
mask: 0b1111111111111111
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__ADD:
|
||||
index: 82
|
||||
encoding: 0b1001000000000010
|
||||
mask: 0b1111000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__JALR:
|
||||
index: 83
|
||||
encoding: 0b1001000000000010
|
||||
mask: 0b1111000001111111
|
||||
size: 16
|
||||
branch: true
|
||||
delay: 1
|
||||
C__EBREAK:
|
||||
index: 84
|
||||
encoding: 0b1001000000000010
|
||||
mask: 0b1111111111111111
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
C__SWSP:
|
||||
index: 85
|
||||
encoding: 0b1100000000000010
|
||||
mask: 0b1110000000000011
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
DII:
|
||||
index: 86
|
||||
encoding: 0b0000000000000000
|
||||
mask: 0b1111111111111111
|
||||
size: 16
|
||||
branch: false
|
||||
delay: 1
|
||||
|
||||
@ -30,18 +30,20 @@
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include "iss_factory.h"
|
||||
#include <sysc/iss_factory.h>
|
||||
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
||||
#include <iss/arch/riscv_hart_m_p.h>
|
||||
#include <iss/arch/riscv_hart_mu_p.h>
|
||||
#include "sc_core_adapter.h"
|
||||
#include "core_complex.h"
|
||||
#include <sysc/sc_core_adapter.h>
|
||||
#include <sysc/core_complex.h>
|
||||
#include <array>
|
||||
|
||||
<%
|
||||
def array_count = coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e"? 3 : 2;
|
||||
%>
|
||||
namespace iss {
|
||||
namespace interp {
|
||||
using namespace sysc;
|
||||
volatile std::array<bool, 2> ${coreDef.name.toLowerCase()}_init = {
|
||||
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
|
||||
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
|
||||
@ -51,13 +53,40 @@ volatile std::array<bool, 2> ${coreDef.name.toLowerCase()}_init = {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
|
||||
})
|
||||
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
|
||||
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
|
||||
})<%}%>
|
||||
};
|
||||
}
|
||||
#if defined(WITH_LLVM)
|
||||
namespace llvm {
|
||||
using namespace sysc;
|
||||
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
|
||||
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
|
||||
}),
|
||||
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
|
||||
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
|
||||
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
|
||||
})<%}%>
|
||||
};
|
||||
}
|
||||
#endif
|
||||
#if defined(WITH_TCC)
|
||||
namespace tcc {
|
||||
using namespace sysc;
|
||||
volatile std::array<bool, 2> ${coreDef.name.toLowerCase()}_init = {
|
||||
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
|
||||
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
|
||||
@ -67,7 +96,34 @@ volatile std::array<bool, 2> ${coreDef.name.toLowerCase()}_init = {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
|
||||
})
|
||||
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
|
||||
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
|
||||
})<%}%>
|
||||
};
|
||||
}
|
||||
#endif
|
||||
#if defined(WITH_ASMJIT)
|
||||
namespace asmjit {
|
||||
using namespace sysc;
|
||||
volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
|
||||
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
|
||||
}),
|
||||
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
|
||||
})<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
|
||||
iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
|
||||
})<%}%>
|
||||
};
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -37,7 +37,7 @@
|
||||
#include <iss/asmjit/vm_base.h>
|
||||
#include <asmjit/asmjit.h>
|
||||
#include <util/logging.h>
|
||||
|
||||
#include <fp_functions.h>
|
||||
#ifndef FMT_HEADER_ONLY
|
||||
#define FMT_HEADER_ONLY
|
||||
#endif
|
||||
|
||||
@ -39,6 +39,7 @@ def nativeTypeSize(int size){
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
#include <iss/interp/vm_base.h>
|
||||
#include <vm/fp_functions.h>
|
||||
#include <util/logging.h>
|
||||
#include <boost/coroutine2/all.hpp>
|
||||
#include <functional>
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2017 - 2023, MINRES Technologies GmbH
|
||||
* All rights reserved.
|
||||
@ -34,6 +33,7 @@
|
||||
******************************************************************************/
|
||||
|
||||
#include "cycle_estimate.h"
|
||||
#include <iss/plugin/calculator.h>
|
||||
#include <yaml-cpp/yaml.h>
|
||||
|
||||
#include <iss/arch_if.h>
|
||||
@ -48,11 +48,12 @@ iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
|
||||
{
|
||||
}
|
||||
|
||||
iss::plugin::cycle_estimate::~cycle_estimate() {
|
||||
}
|
||||
iss::plugin::cycle_estimate::~cycle_estimate() = default;
|
||||
|
||||
bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
|
||||
instr_if = vm.get_arch()->get_instrumentation_if();
|
||||
assert(instr_if && "No instrumentation interface available but callback executed");
|
||||
reg_base_ptr = reinterpret_cast<uint32_t*>(vm.get_arch()->get_regs_base_ptr());
|
||||
if(!instr_if) return false;
|
||||
const string core_name = instr_if->core_type_name();
|
||||
if (config_file_name.length() > 0) {
|
||||
@ -67,17 +68,23 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
|
||||
auto isa_subset = p.first;
|
||||
auto instructions = p.second;
|
||||
for (auto const& instr : instructions) {
|
||||
instr_desc res;
|
||||
auto idx = instr.second["index"].as<unsigned>();
|
||||
if(delays.size()<=idx)
|
||||
delays.resize(idx+1);
|
||||
auto& res = delays[idx];
|
||||
res.is_branch = instr.second["branch"].as<bool>();
|
||||
auto delay = instr.second["delay"];
|
||||
if(delay.IsSequence()) {
|
||||
res.not_taken = delay[0].as<uint64_t>();
|
||||
res.taken = delay[1].as<uint64_t>();
|
||||
} else {
|
||||
try {
|
||||
res.not_taken = delay.as<uint64_t>();
|
||||
res.taken = res.not_taken;
|
||||
} catch (const YAML::BadConversion& e) {
|
||||
res.f = iss::plugin::calculator(reg_base_ptr, delay.as<std::string>());
|
||||
}
|
||||
}
|
||||
delays.push_back(std::move(res));
|
||||
}
|
||||
}
|
||||
} catch (YAML::ParserException &e) {
|
||||
@ -90,15 +97,19 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
|
||||
}
|
||||
}
|
||||
return true;
|
||||
|
||||
}
|
||||
|
||||
void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
|
||||
assert(instr_if && "No instrumentation interface available but callback executed");
|
||||
auto entry = delays[instr_info.instr_id];
|
||||
bool taken = instr_if->is_branch_taken();
|
||||
if (taken && (entry.taken > 1))
|
||||
instr_if->update_last_instr_cycles(entry.taken);
|
||||
else if (entry.not_taken > 1)
|
||||
instr_if->update_last_instr_cycles(entry.not_taken);
|
||||
size_t instr_id = instr_info.instr_id;
|
||||
auto& entry = instr_id<delays.size()?delays[instr_id]:illegal_desc;
|
||||
if(instr_info.phase_id==PRE_SYNC) {
|
||||
if(entry.f)
|
||||
current_delay = entry.f(instr_if->get_instr_word());
|
||||
} else {
|
||||
if(!entry.f)
|
||||
current_delay = instr_if->is_branch_taken()? entry.taken: entry.not_taken;
|
||||
if(current_delay>1)
|
||||
instr_if->update_last_instr_cycles(current_delay);
|
||||
current_delay = 1;
|
||||
}
|
||||
}
|
||||
|
||||
@ -40,24 +40,20 @@
|
||||
#include <string>
|
||||
#include <unordered_map>
|
||||
#include <vector>
|
||||
#include <functional>
|
||||
|
||||
namespace iss {
|
||||
|
||||
namespace plugin {
|
||||
|
||||
class cycle_estimate: public vm_plugin {
|
||||
BEGIN_BF_DECL(instr_desc, uint32_t)
|
||||
BF_FIELD(taken, 24, 8)
|
||||
BF_FIELD(not_taken, 16, 8)
|
||||
BF_FIELD(is_branch, 8, 8)
|
||||
BF_FIELD(size, 0, 8)
|
||||
instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
|
||||
this->size=size;
|
||||
this->taken=taken;
|
||||
this->not_taken=not_taken;
|
||||
this->is_branch=branch;
|
||||
}
|
||||
END_BF_DECL();
|
||||
struct instr_desc {
|
||||
size_t size{0};
|
||||
bool is_branch{false};
|
||||
unsigned not_taken{1};
|
||||
unsigned taken{1};
|
||||
std::function<unsigned(uint64_t)> f;
|
||||
};
|
||||
|
||||
public:
|
||||
cycle_estimate() = delete;
|
||||
@ -76,13 +72,16 @@ public:
|
||||
|
||||
bool registration(const char *const version, vm_if &arch) override;
|
||||
|
||||
sync_type get_sync() override { return POST_SYNC; };
|
||||
sync_type get_sync() override { return ALL_SYNC; };
|
||||
|
||||
void callback(instr_info_t instr_info) override;
|
||||
|
||||
private:
|
||||
iss::instrumentation_if *instr_if;
|
||||
iss::instrumentation_if *instr_if{nullptr};
|
||||
uint32_t* reg_base_ptr {nullptr};
|
||||
instr_desc illegal_desc{};
|
||||
std::vector<instr_desc> delays;
|
||||
unsigned current_delay{0};
|
||||
struct pair_hash {
|
||||
size_t operator()(const std::pair<uint64_t, uint64_t> &p) const {
|
||||
std::hash<uint64_t> hash;
|
||||
|
||||
@ -48,6 +48,7 @@
|
||||
#include <iostream>
|
||||
#include <sstream>
|
||||
#include <array>
|
||||
#include <numeric>
|
||||
#include <iss/plugin/cycle_estimate.h>
|
||||
#include <iss/plugin/instruction_count.h>
|
||||
|
||||
@ -126,7 +127,7 @@ public:
|
||||
core_wrapper(core_complex *owner) : owner(owner) { }
|
||||
|
||||
void reset(uint64_t addr){vm->reset(addr);}
|
||||
inline void start(){vm->start();}
|
||||
inline void start(bool dump = false){vm->start(std::numeric_limits<uint64_t>::max(), dump);}
|
||||
inline std::pair<uint64_t, bool> load_file(std::string const& name){
|
||||
iss::arch_if* cc = cpu->get_arch_if();
|
||||
return cc->load_file(name);};
|
||||
@ -147,7 +148,7 @@ public:
|
||||
} else {
|
||||
auto base_isa = type.substr(0, 5);
|
||||
if(base_isa=="tgc5d" || base_isa=="tgc5e") {
|
||||
std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port);
|
||||
std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port, owner);
|
||||
} else {
|
||||
std::tie(cpu, vm) = f.create(type + "|m_p|" + backend, gdb_port, owner);
|
||||
}
|
||||
@ -379,7 +380,7 @@ void core_complex::run() {
|
||||
}
|
||||
quantum_keeper.reset();
|
||||
cpu->set_interrupt_execution(false);
|
||||
cpu->start();
|
||||
cpu->start(dump_ir);
|
||||
} while (cpu->get_interrupt_execution());
|
||||
sc_stop();
|
||||
}
|
||||
@ -390,7 +391,10 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
|
||||
if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
|
||||
quantum_keeper.inc(lut_entry.get_read_latency());
|
||||
if(is_fetch)
|
||||
ibus_inc+=lut_entry.get_read_latency()/curr_clk;
|
||||
else
|
||||
dbus_inc+=lut_entry.get_read_latency()/curr_clk;
|
||||
return true;
|
||||
} else {
|
||||
auto& sckt = is_fetch? ibus : dbus;
|
||||
@ -408,17 +412,22 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
|
||||
auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
|
||||
gp.set_extension(preExt);
|
||||
}
|
||||
sckt->b_transport(gp, delay);
|
||||
auto incr = delay-quantum_keeper.get_local_time();
|
||||
auto pre_delay = delay;
|
||||
dbus->b_transport(gp, delay);
|
||||
if(pre_delay>delay) {
|
||||
quantum_keeper.reset();
|
||||
} else {
|
||||
auto incr = (delay-quantum_keeper.get_local_time())/curr_clk;
|
||||
if(is_fetch)
|
||||
ibus_inc+=incr;
|
||||
else
|
||||
dbus_inc+=incr;
|
||||
}
|
||||
SCCTRACE(this->name()) << "[local time: "<<delay<<"]: finish read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
|
||||
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
|
||||
return false;
|
||||
}
|
||||
if (gp.is_dmi_allowed()) {
|
||||
if (gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
tlm_dmi_ext dmi_data;
|
||||
@ -438,7 +447,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
|
||||
addr + length <= lut_entry.get_end_address() + 1) {
|
||||
auto offset = addr - lut_entry.get_start_address();
|
||||
std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
|
||||
quantum_keeper.inc(lut_entry.get_read_latency());
|
||||
dbus_inc+=lut_entry.get_write_latency()/curr_clk;
|
||||
return true;
|
||||
} else {
|
||||
write_buf.resize(length);
|
||||
@ -454,13 +463,17 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
|
||||
auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
|
||||
gp.set_extension(preExt);
|
||||
}
|
||||
auto pre_delay = delay;
|
||||
dbus->b_transport(gp, delay);
|
||||
dbus_inc+=delay-quantum_keeper.get_local_time();
|
||||
if(pre_delay>delay)
|
||||
quantum_keeper.reset();
|
||||
else
|
||||
dbus_inc+=(delay-quantum_keeper.get_local_time())/curr_clk;
|
||||
SCCTRACE() << "[local time: "<<delay<<"]: finish write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
|
||||
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
|
||||
return false;
|
||||
}
|
||||
if (gp.is_dmi_allowed()) {
|
||||
if (gp.is_dmi_allowed() && !GET_PROP_VALUE(disable_dmi)) {
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(addr);
|
||||
tlm_dmi_ext dmi_data;
|
||||
|
||||
@ -94,6 +94,8 @@ public:
|
||||
|
||||
cci::cci_param<bool> enable_disass{"enable_disass", false};
|
||||
|
||||
cci::cci_param<bool> disable_dmi{"disable_dmi", false};
|
||||
|
||||
cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
|
||||
|
||||
cci::cci_param<std::string> core_type{"core_type", "tgc5c"};
|
||||
@ -119,6 +121,8 @@ public:
|
||||
|
||||
scml_property<bool> enable_disass{"enable_disass", false};
|
||||
|
||||
scml_property<bool> disable_dmi{"disable_dmi", false};
|
||||
|
||||
scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
|
||||
|
||||
scml_property<std::string> core_type{"core_type", "tgc5c"};
|
||||
@ -156,17 +160,21 @@ public:
|
||||
|
||||
~core_complex();
|
||||
|
||||
|
||||
inline unsigned get_last_bus_cycles() {
|
||||
auto mem_incr = std::max(ibus_inc, dbus_inc);
|
||||
ibus_inc = dbus_inc = 0;
|
||||
return mem_incr>1?mem_incr:1;
|
||||
}
|
||||
|
||||
inline void sync(uint64_t cycle) {
|
||||
auto core_inc = curr_clk * (cycle - last_sync_cycle);
|
||||
auto incr = std::max(core_inc, std::max(ibus_inc, dbus_inc));
|
||||
quantum_keeper.inc(incr);
|
||||
quantum_keeper.inc(core_inc);
|
||||
if (quantum_keeper.need_sync()) {
|
||||
wait(quantum_keeper.get_local_time());
|
||||
quantum_keeper.reset();
|
||||
}
|
||||
last_sync_cycle = cycle;
|
||||
ibus_inc = sc_core::SC_ZERO_TIME;
|
||||
dbus_inc = sc_core::SC_ZERO_TIME;
|
||||
}
|
||||
|
||||
bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
|
||||
@ -198,7 +206,7 @@ protected:
|
||||
std::vector<uint8_t> write_buf;
|
||||
core_wrapper* cpu{nullptr};
|
||||
sc_core::sc_signal<sc_core::sc_time> curr_clk;
|
||||
sc_core::sc_time ibus_inc, dbus_inc;
|
||||
uint64_t ibus_inc{0}, dbus_inc{0};
|
||||
core_trace* trc{nullptr};
|
||||
std::unique_ptr<scc::tick2time> t2t;
|
||||
private:
|
||||
|
||||
@ -54,6 +54,23 @@ volatile std::array<bool, 2> tgc_init = {
|
||||
})
|
||||
};
|
||||
}
|
||||
#if defined(WITH_LLVM)
|
||||
namespace llvm {
|
||||
using namespace sysc;
|
||||
volatile std::array<bool, 2> tgc_init = {
|
||||
iss_factory::instance().register_creator("tgc5c|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
|
||||
}),
|
||||
iss_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
|
||||
})
|
||||
};
|
||||
}
|
||||
#endif
|
||||
#if defined(WITH_TCC)
|
||||
namespace tcc {
|
||||
using namespace sysc;
|
||||
@ -71,4 +88,21 @@ volatile std::array<bool, 2> tgc_init = {
|
||||
};
|
||||
}
|
||||
#endif
|
||||
#if defined(WITH_ASMJIT)
|
||||
namespace asmjit {
|
||||
using namespace sysc;
|
||||
volatile std::array<bool, 2> tgc_init = {
|
||||
iss_factory::instance().register_creator("tgc5c|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
|
||||
}),
|
||||
iss_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
|
||||
auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
|
||||
auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
|
||||
return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
|
||||
})
|
||||
};
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -39,9 +39,14 @@ public:
|
||||
uint64_t get_state() override { return this->state.mstatus.backing.val; }
|
||||
|
||||
void notify_phase(iss::arch_if::exec_phase p) override {
|
||||
if (p == iss::arch_if::ISTART)
|
||||
if (p == iss::arch_if::ISTART && !first) {
|
||||
auto cycle_incr = owner->get_last_bus_cycles();
|
||||
if(cycle_incr>1)
|
||||
this->instr_if.update_last_instr_cycles(cycle_incr);
|
||||
owner->sync(this->instr_if.get_total_cycles());
|
||||
}
|
||||
first=false;
|
||||
}
|
||||
|
||||
iss::sync_type needed_sync() const override { return iss::PRE_SYNC; }
|
||||
|
||||
@ -70,6 +75,34 @@ public:
|
||||
if (addr.access && iss::access_type::DEBUG)
|
||||
return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
|
||||
else {
|
||||
auto tohost_upper = (sizeof(reg_t) == 4 && addr.val == (this->tohost + 4)) ||
|
||||
(sizeof(reg_t) == 8 && addr.val == this->tohost);
|
||||
auto tohost_lower = (sizeof(reg_t) == 4 && addr.val == this->tohost) ||
|
||||
(sizeof(reg_t)== 64 && addr.val == this->tohost);
|
||||
if (tohost_lower || tohost_upper) {
|
||||
if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
|
||||
switch (hostvar >> 48) {
|
||||
case 0:
|
||||
if (hostvar != 0x1) {
|
||||
SCCINFO(owner->name()) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
||||
<< "), stopping simulation";
|
||||
} else {
|
||||
SCCINFO(owner->name()) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
|
||||
<< "), stopping simulation";
|
||||
}
|
||||
this->reg.trap_state=std::numeric_limits<uint32_t>::max();
|
||||
this->interrupt_sim=hostvar;
|
||||
#ifndef WITH_TCC
|
||||
throw(iss::simulation_stopped(hostvar));
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else if (tohost_lower)
|
||||
to_host_wr_cnt++;
|
||||
return iss::Ok;
|
||||
} else {
|
||||
auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
|
||||
// clear MTIP on mtimecmp write
|
||||
if (addr.val == 0x2004000) {
|
||||
@ -80,6 +113,7 @@ public:
|
||||
return res;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
iss::status read_csr(unsigned addr, reg_t &val) override {
|
||||
#ifndef CWR_SYSTEMC
|
||||
@ -146,6 +180,9 @@ public:
|
||||
private:
|
||||
sysc::tgfs::core_complex *const owner;
|
||||
sc_core::sc_event wfi_evt;
|
||||
uint64_t hostvar{std::numeric_limits<uint64_t>::max()};
|
||||
unsigned to_host_wr_cnt = 0;
|
||||
bool first{true};
|
||||
};
|
||||
}
|
||||
#endif /* _SYSC_SC_CORE_ADAPTER_H_ */
|
||||
|
||||
@ -4549,13 +4549,13 @@ volatile std::array<bool, 2> dummy = {
|
||||
auto* vm = new llvm::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
|
||||
return {cpu_ptr{cpu}, vm_ptr{vm}};
|
||||
})/*,
|
||||
}),
|
||||
core_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
|
||||
auto* vm = new llvm::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
|
||||
return {cpu_ptr{cpu}, vm_ptr{vm}};
|
||||
})*/
|
||||
})
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user