Merge branch 'develop'

.gitignore

@@ -30,5 +30,5 @@ language.settings.xml
 /.gdbinit
 /*.out
 /dump.json
+/src-gen/
 /*.yaml
-/*.json

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "gen_input/CoreDSL-Instruction-Set-Description"]
+	path = gen_input/CoreDSL-Instruction-Set-Description
+	url = ../CoreDSL-Instruction-Set-Description.git

.project

@@ -23,5 +23,6 @@
 		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
 	</natures>
 </projectDescription>

CMakeLists.txt

@@ -6,9 +6,7 @@ project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
 
-find_package(elfio QUIET)
+find_package(elfio)
-find_package(Boost COMPONENTS coroutine)
-find_package(jsoncpp)
 
 if(WITH_LLVM)
     if(DEFINED ENV{LLVM_HOME})
@@ -29,44 +27,30 @@ endif()
 
 add_subdirectory(softfloat)
 
+# library files
+FILE(GLOB TGC_SOURCES
+    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp 
+    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp
+)
 set(LIB_SOURCES 
-    src/iss/plugin/instruction_count.cpp
+    src/vm/fp_functions.cpp
-	src/iss/arch/tgc_c.cpp
+    src/plugin/instruction_count.cpp
-	src/vm/interp/vm_tgc_c.cpp
+    src/plugin/cycle_estimate.cpp
-	src/vm/fp_functions.cpp
+    ${TGC_SOURCES}
 )
 
-# library files
-if(TARGET ${CORE_NAME}_cpp)
-    list(APPEND LIB_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
-else()
-    FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
-    FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
-    list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
-    foreach(FILEPATH ${GEN_ISS_SOURCES})
-        get_filename_component(CORE ${FILEPATH} NAME_WE)
-        string(TOUPPER ${CORE} CORE)
-        list(APPEND LIB_DEFINES CORE_${CORE})
-    endforeach()
-    message("Defines are ${LIB_DEFINES}")
-endif()
-
-if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
-    list(APPEND LIB_SOURCES src/iss/plugin/cycle_estimate.cpp src/iss/plugin/pctrace.cpp)
-endif()
-
 if(WITH_LLVM)
-	FILE(GLOB LLVM_GEN_SOURCES
+	FILE(GLOB TGC_LLVM_SOURCES
-	    ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/llvm/vm_*.cpp
 	)
-	list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
+	list(APPEND LIB_SOURCES ${TGC_LLVM_SOURCES})
 endif()
 
 if(WITH_TCC)
-	FILE(GLOB TCC_GEN_SOURCES
+	FILE(GLOB TGC_TCC_SOURCES
 	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
 	)
-	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+	list(APPEND LIB_SOURCES ${TGC_TCC_SOURCES})
 endif()
 
 # Define the library
@@ -81,34 +65,20 @@ if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
 elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
     target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
 endif()
-target_include_directories(${PROJECT_NAME} PUBLIC src)
+target_include_directories(${PROJECT_NAME} PUBLIC incl)
-target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
+target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
-target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util Boost::coroutine)
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
-if(TARGET jsoncpp::jsoncpp)
+    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
-	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp::jsoncpp)
 else()
-	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp)
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-core)
 endif()
-if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" AND BUILD_SHARED_LIBS)
+if(TARGET CONAN_PKG::elfio)
-    target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-rise-core -Wl,--no-whole-archive)
+    target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
-else()
+elseif(TARGET elfio::elfio)
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-core)
-endif()
-if(TARGET elfio::elfio)
     target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
 else()
     message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
 endif()
-if(TARGET lz4::lz4)
-    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_LZ4)
-    target_link_libraries(${PROJECT_NAME} PUBLIC lz4::lz4)
-endif()
-if(TARGET RapidJSON::RapidJSON)
-    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON::RapidJSON)
-elseif(TARGET RapidJSON)
-    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
-endif()
-
 
 set_target_properties(${PROJECT_NAME} PROPERTIES
   VERSION ${PROJECT_VERSION}
@@ -135,31 +105,12 @@ project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)
 
 add_executable(${PROJECT_NAME} src/main.cpp)
-if(TARGET ${CORE_NAME}_cpp)
+# This sets the include directory for the reference project. This is the -I flag in gcc.
-    list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
+target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-else()
-    FILE(GLOB TGC_SOURCES
-        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
-    )
-    list(APPEND TGC_SOURCES ${GEN_SOURCES})
-endif()
-
-foreach(F IN LISTS TGC_SOURCES)
-    if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
-        string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
-        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-    endif()
-endforeach()
-
 if(WITH_LLVM)
     target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
     target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
 endif()
-if(WITH_TCC)
-    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
-endif()
 # Links the target exe against the libraries
 target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
 if(TARGET Boost::program_options)
@@ -184,27 +135,28 @@ install(TARGETS tgc-sim
 ###############################################################################
 #
 ###############################################################################
-if(TARGET scc-sysc)
+project(dbt-rise-tgc_sc VERSION 1.0.0)
-	project(dbt-rise-tgc_sc VERSION 1.0.0)
+
-    add_library(${PROJECT_NAME} 
+include(SystemCPackage)
-    	src/sysc/core_complex.cpp
+if(SystemC_FOUND)
-    	src/sysc/register_tgc_c.cpp
+    add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
-    )
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
     target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-    foreach(F IN LISTS TGC_SOURCES)
+    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
-        if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_B)
-            string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+    endif()
-            string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
-            target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_C)
-        endif()
+    endif()
-    endforeach()
+    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
-    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_D)
+    endif()
+    target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
     if(WITH_LLVM)
         target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
     endif()
     
-	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
+	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/core_complex.h)
     set_target_properties(${PROJECT_NAME} PROPERTIES
       VERSION ${PROJECT_VERSION}
       FRAMEWORK FALSE

TGC_C_instr.yaml

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-    delay:   1
-  - CMV:
-    encoding: 0b1000000000000010
-    mask: 0b1111000000000011
-    size:   16
-    branch:   false
-    delay:   1
-  - CJR:
-    encoding: 0b1000000000000010
-    mask: 0b1111000001111111
-    attributes: [[name:no_cont]]
-    size:   16
-    branch:   true
-    delay:   1
-  - CADD:
-    encoding: 0b1001000000000010
-    mask: 0b1111000000000011
-    size:   16
-    branch:   false
-    delay:   1
-  - CJALR:
-    encoding: 0b1001000000000010
-    mask: 0b1111000001111111
-    attributes: [[name:no_cont]]
-    size:   16
-    branch:   true
-    delay:   1
-  - CEBREAK:
-    encoding: 0b1001000000000010
-    mask: 0b1111111111111111
-    attributes: [[name:no_cont]]
-    size:   16
-    branch:   false
-    delay:   1
-  - CSWSP:
-    encoding: 0b1100000000000010
-    mask: 0b1110000000000011
-    size:   16
-    branch:   false
-    delay:   1
-  - DII:
-    encoding: 0b0000000000000000
-    mask: 0b1111111111111111
-    attributes: [[name:no_cont]]
-    size:   16
-    branch:   false
-    delay:   1
-

contrib/.gitignore

@@ -1,3 +0,0 @@
-/results
-/cwr
-/*.xml

contrib/README.md

@@ -1,43 +0,0 @@
-# Notes
-
-* requires conan version 1.59
-* requires decent cmake version 3.23
-
-Setup for tcsh:
-
-```
-git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
-cd TGC-ISS/
-setenv TGFS_INSTALL_ROOT `pwd`/install
-setenv COWAREHOME <your SNPS PA installation>
-setenv SNPSLMD_LICENSE_FILE <your SNPS PA license file>
-source $COWAREHOME/SLS/linux/setup.csh pae
-setenv SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM 1
-setenv PATH $COWAREHOME/common/bin/:${PATH}
-setenv CC  $COWAREHOME/SLS/linux/common/bin/gcc
-setenv CXX $COWAREHOME/SLS/linux/common/bin/g++
-cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
-    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
-cmake --build build/PA --target install -j16
-cd dbt-rise-tgc/contrib
-# import the TGC core itself
-pct tgc_import_tb.tcl
-```
-
-Setup for bash:
-
-```
-git clone --recursive -b develop https://git.minres.com/TGFS/TGC-ISS.git
-cd TGC-ISS/
-export TGFS_INSTALL_ROOT `pwd`/install
-module load tools/pa/T-2022.06
-export SNPS_ENABLE_MEM_ON_DEMAND_IN_GENERIC_MEM=1
-export CC=$COWAREHOME/SLS/linux/common/bin/gcc
-export CXX=$COWAREHOME/SLS/linux/common/bin/g++
-cmake -S . -B build/PA -DCMAKE_BUILD_TYPE=Debug -DUSE_CWR_SYSTEMC=ON -DBUILD_SHARED_LIBS=ON \
-    -DCODEGEN=OFF -DCMAKE_INSTALL_PREFIX=${TGFS_INSTALL_ROOT}
-cmake --build build/PA --target install -j16
-cd dbt-rise-tgc/contrib
-# import the TGC core itself
-pct tgc_import_tb.tcl
-```

contrib/build.tcl

@@ -16,7 +16,7 @@ namespace eval Specification {
                 set libdir "${install_dir}/lib64"
                 set preprocessorOptions [concat $preprocessorOptions "-I${incldir}"]
                 # Set the Linker paths.
-                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc -lscc-sysc"]
+                set linkerOptions [concat $linkerOptions "-Wl,-rpath,${libdir} -L${libdir} -ldbt-rise-tgc_sc"]
             }
             default {
                puts stderr "ERROR: \"$target\" is not supported, [::scsh::version]"

contrib/tgc_import.tcl

@@ -6,11 +6,14 @@ proc getScriptDirectory {} {
     set scriptFolder [file dirname $dispScriptFile]
     return $scriptFolder
 }
+if { $::env(SNPS_VP_PRODUCT) == "PAULTRA" } {
     set hardware /HARDWARE/HW/HW
+} else {
+    set hardware /HARDWARE
+}
 
 set scriptDir [getScriptDirectory]
 set top_design_name core_complex
-set encap_name sysc::tgfs::${top_design_name}
 set clocks clk_i
 set resets rst_i
 set model_prefix "i_"
@@ -25,8 +28,7 @@ set model_postfix ""
 ::pct::set_update_existing_encaps_flag true
 ::pct::set_dynamic_port_arrays_flag true
 ::pct::set_import_scml_properties_flag true
-::pct::set_import_encap_prop_as_extra_prop_flag true
+::pct::load_modules --set-category modules tgc_import.cc
-::pct::load_modules --set-category modules ${scriptDir}/tgc_import.cc
 
 # Set Port Protocols correctly
 set block ${top_design_name}
@@ -36,15 +38,13 @@ foreach clock ${clocks} {
 foreach reset ${resets} {
     ::pct::set_block_port_protocol --set-category SYSTEM_LIBRARY:$block/${reset} SYSTEM_LIBRARY:RESET
 }
-#::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
+::pct::set_encap_port_array_size SYSTEM_LIBRARY:$block/local_irq_i 16
 
 # Set compile settings and look
 set block SYSTEM_LIBRARY:${top_design_name}
-::pct::set_encap_build_script $block/${encap_name} $scriptDir/build.tcl
+::pct::set_encap_build_script $block/${top_design_name} $scriptDir/build.tcl
 ::pct::set_background_color_rgb $block 255 255 255 255
-::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${encap_name} ${encap_name}() 
+::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} ${top_design_name} 
-::pct::set_bounds i_${top_design_name} 200 300 100 400
-::pct::set_image i_${top_design_name} "$scriptDir/minres.png" center center false true
 
 # export the result as component
 ::pct::export_system_library ${top_design_name}  ${top_design_name}.xml

contrib/tgc_import_tb.tcl

@@ -1,71 +0,0 @@
-source tgc_import.tcl
-set hardware /HARDWARE/HW/HW
-set FW_name ${scriptDir}/hello.elf
-
-puts "instantiate testbench elements"
-::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
-::pct::set_param_value i_Memory_Generic/MEM:protocol {Protocol Common Parameters} address_width 30
-::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/LT/clock_period_in_ns 1
-::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/read/cmd_accept_cycles 1
-::pct::set_param_value i_Memory_Generic {Scml Properties} /timing/write/cmd_accept_cycles 1
-::pct::set_bounds i_Memory_Generic 1000 300 100 100
-
-::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
-::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
-						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
-::pct::set_bounds i_Bus 700 300 100 400
-::pct::create_connection C_ibus i_core_complex/ibus i_Bus/i_core_complex_ibus
-::pct::set_location_on_owner i_Bus/i_core_complex_ibus 10
-::pct::create_connection C_dbus i_core_complex/dbus i_Bus/i_core_complex_dbus
-::pct::set_location_on_owner i_Bus/i_core_complex_dbus 10
-::pct::create_connection C_mem i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
-
-puts "instantiating clock manager"
-set clock "Clk"
-::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
-::pct::set_bounds ${clock}_clock 100 100 100 100
-::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
-::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
-
-puts "instantiating reset manager"
-set reset "Rst"
- ::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
- ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 0
- ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
- ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
- ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
- ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
-::pct::set_bounds ${reset}_reset 300 100 100 100
-
-puts "connecting reset/clock"
-::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
-::pct::add_ports_to_connection C_clk i_Bus/Clk
-::pct::add_ports_to_connection C_clk i_Memory_Generic/CLK
-::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
-::pct::add_ports_to_connection C_rst i_Bus/Rst
-
-puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
-::pct::set_param_value $hardware/i_${top_design_name} {Extra properties} elf_file ${FW_name}
-::pct::set_address $hardware/i_${top_design_name}/ibus:i_Memory_Generic/MEM 0x0
-::pct::set_address $hardware/i_${top_design_name}/dbus:i_Memory_Generic/MEM 0x0
-::BLWizard::updateFramework i_Bus {} { common_configuration:BackBone:/advanced/num_resources_per_target:1 }
-
-::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
-::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
-::pct::create_simulation_build_config Debug
-::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
-# add build settings and save design for next steps
-#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
-#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
-
-#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
-#::simulation::run_simulation Simulation
-
-#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
-#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
-#::pct::export_system "export"
-#::cd "export"
-#::scsh::open-project
-#::scsh::build
-#::scsh::elab sim
-::pct::save_system testbench.xml

gen_input/.gitignore

@@ -1,2 +1 @@
 /src-gen/
-/CoreDSL-Instruction-Set-Description

gen_input/TGC_B.core_desc

@@ -0,0 +1,14 @@
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+Core TGC_B provides RV32I, Zicsr, Zifencei {
+	architectural_state {
+        XLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000000000100000000;
+        unsigned MARCHID_VAL = 0x80000002;
+	}
+}
+

gen_input/TGC_C.core_desc

@@ -1,13 +1,13 @@
-import "ISA/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
-import "ISA/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
-import "ISA/RVC.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
 Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
     architectural_state {
         XLEN=32;
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned int MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
-        unsigned int MARCHID_VAL = 0x80000003;
+        unsigned MARCHID_VAL = 0x80000003;
     }
 }

gen_input/TGC_D.core_desc

@@ -0,0 +1,13 @@
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+Core TGC_D provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
+    architectural_state {
+        XLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000100000011000100000100;
+        unsigned MARCHID_VAL = 0x80000004;
+    }
+}

gen_input/TGC_D_XRB_MAC.core_desc

@@ -0,0 +1,73 @@
+import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+InstructionSet X_RB_MAC extends RISCVBase {
+  architectural_state {
+    register unsigned<64> ACC;
+  }
+
+  instructions {
+    RESET_ACC { // v-- funct7       v-- funct3
+      encoding: 7'd0 :: 10'b0 :: 3'd0 :: 5'b0 :: 7'b0001011;
+      behavior: ACC = 0;
+    }
+    
+    GET_ACC_LO {
+      encoding: 7'd1 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
+      behavior: if (rd != 0) X[rd] = ACC[31:0];
+    }
+    
+    GET_ACC_HI {
+      encoding: 7'd2 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
+      behavior: if (rd != 0) X[rd] = ACC[63:32];
+    }
+    
+    MACU_32 {
+      encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        unsigned<64> mul = X[rs1]    * X[rs2];
+        unsigned<33> add = mul[31:0] + ACC[31:0];
+        ACC = add[31:0];
+      }
+    }
+    
+    MACS_32 {
+      encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        signed<64> mul = ((signed) X[rs1])    * ((signed) X[rs2]);
+        signed<33> add = ((signed) mul[31:0]) + ((signed) ACC[31:0]);
+        ACC = add[31:0]; // bit range always yields unsigned type
+      }
+    }
+    
+    MACU_64 {
+      encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        unsigned<64> mul = X[rs1] * X[rs2];
+        unsigned<65> add = mul    + ACC;
+        ACC = add[63:0];
+      }
+    }
+    
+    MACS_64 {
+      encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
+      behavior: {
+        signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
+        signed<65> add =           mul     + ((signed) ACC);
+        ACC = add[63:0];
+      }
+    }
+  }
+}
+
+Core TGC_D_XRB_MAC provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_MAC {
+    architectural_state {
+        XLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned MARCHID_VAL = 0x80000004;
+    }
+}

gen_input/TGC_D_XRB_NN.core_desc

@@ -0,0 +1,133 @@
+import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
+import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
+import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
+
+InstructionSet X_RB_NN extends RISCVBase {
+     
+    instructions { 
+        
+        // signed saturate with pre-shift
+        SSAT {
+            // instruction format: R-type
+            // opcode space: custom-1 (inst[6:2] = 01010)
+            // opcode = 0b0101011, func3 = 0b000, func7 = <bit position to saturate to>
+            encoding: sat_bit_pos[6:0] :: rs2[4:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0101011;
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}, {name(sat_bit_pos)}";
+            behavior: {
+               signed<XLEN> val_s = (signed<XLEN>)X[rs1];
+               unsigned<XLEN> pre_shift = (unsigned<XLEN>)X[rs2];
+               unsigned<XLEN> sat_limit;
+               signed<XLEN> upper_limit;
+               signed<XLEN> lower_limit;             
+                              
+               if((rd != 0) && (sat_bit_pos > 0) && (sat_bit_pos <= 32) && (pre_shift < 32)) {                                    
+                  sat_limit = (unsigned<XLEN>)(1 << (sat_bit_pos - 1));
+                  upper_limit = (signed)sat_limit - 1;
+                  lower_limit = (signed)sat_limit * (-1); 
+
+                  // important: arithmetical shift right                
+                  val_s = val_s >> pre_shift;
+                  X[rd] = (val_s > upper_limit) ? (upper_limit) : ( (val_s < lower_limit) ? (lower_limit) : (val_s) );
+               } 
+            }
+        }
+        
+        // custom packed dot product with accumulation (4x8bit)
+        PDOT8 {
+            // instruction format: R-type
+            // opcode space: custom-1 (inst[6:2] = 01010)
+            // opcode = 0b0101011, func3 = 0b001, func7 = 0b0000000
+            encoding: 0b0000000 :: rs2[4:0] :: rs1[4:0] :: 0b001 :: rd[4:0] :: 0b0101011;
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
+            behavior: {              
+              signed<8> op1_0 = (signed<8>)X[rs1][ 7: 0];
+              signed<8> op1_1 = (signed<8>)X[rs1][15: 8];
+              signed<8> op1_2 = (signed<8>)X[rs1][23:16];
+              signed<8> op1_3 = (signed<8>)X[rs1][31:24];
+              
+              signed<8> op2_0 = (signed<8>)X[rs2][ 7: 0];
+              signed<8> op2_1 = (signed<8>)X[rs2][15: 8];
+              signed<8> op2_2 = (signed<8>)X[rs2][23:16];
+              signed<8> op2_3 = (signed<8>)X[rs2][31:24];
+              
+              signed<XLEN> op3 = (signed<XLEN>)X[rd];
+              
+              signed<16> mul0 = op1_0 * op2_0;
+              signed<16> mul1 = op1_1 * op2_1;
+              signed<16> mul2 = op1_2 * op2_2;
+              signed<16> mul3 = op1_3 * op2_3;
+              
+              signed<19> sum_tmp = mul0 + mul1 + mul2 + mul3;
+              
+              signed<33> result = op3 + sum_tmp;
+              
+              if(rd != 0) X[rd] = result[31:0];
+            }
+        }        
+        
+        // standard signed multiply accumulate with 32 bit operands and 32 bit result
+        MAC {
+            // instruction format: R-type
+            // opcode space: custom-1 (inst[6:2] = 01010)
+            // opcode = 0b0101011, func3 = 0b010, func7 = 0b0000000
+            encoding: 0b0000000 :: rs2[4:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0101011;
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
+            behavior: {
+              signed<65> result = (signed)X[rs1] * (signed)X[rs2] + (signed)X[rd];
+              if(rd != 0) X[rd] = result[31:0];
+            }
+        }
+        
+        
+        // WARNING: The following two HW loop instructions are not fully specified or implemented. The idea is to design the HW loops identical to the RI5CY core (current naming: CV32E40P)
+        // See "Short Hardware Loop Setup Instructions" from RI5CY specification document from April 2019, revision 4.0: https://www.pulp-platform.org/docs/ri5cy_user_manual.pdf -> page 38, chapter 14.2
+        // Specific CSRs are introduced to support the HW loops (see page 17, chapter 7).
+        
+        // lp.setup HW loop (Short Hardware Loop Setup Instruction)        
+        LOOP {
+            // instruction format: I-type
+            // opcode space: custom-3 (inst[6:2] = 11110)
+            // opcode = 0b1111011, func3 = 0b100        
+            // uimmL[11:0] src1 100 0000 L 111 1011 -> lp.setup L,rs1, uimmL
+            encoding: imm[11:0] :: rs1[4:0] :: 0b100 :: 0b0000 :: L[0:0] :: 0b1111011;
+            args_disass:"{name(L)}, {name(rs1)}, {imm}";
+            behavior: {
+                // L: loop level (two loop levels would be sufficient); L=0 has higher priority and is considered as the inner loop.
+                /*
+                lpstart[L] = PC + 4;
+                lpend[L] = PC + ((unsigned<12>)imm << 1);
+                lpcount[L] = rs1;
+                */
+            }
+        }
+        
+        // lp.setupi HW loop (Short Hardware Loop Setup Instruction with immediate value for loop count)        
+        LOOPI {
+            // instruction format: I-type
+            // opcode space: custom-3 (inst[6:2] = 11110)
+            // opcode = 0b1111011, func3 = 0b101
+            // uimmL[11:0] uimmS[4:0] 101 0000 L 111 1011 -> lp.setupi L, uimmS, uimmL
+            encoding: imm2[11:0] :: imm1[4:0] :: 0b101 :: 0b0000 :: L[0:0] :: 0b1111011;
+            args_disass:"{name(L)}, {imm1}, {imm2}";
+            behavior: {
+                // L: loop level (two loop levels would be sufficient); L=0 has higher priority and is considered as the inner loop.
+                /*
+                lpstart[L] = PC + 4;
+                lpend[L] = PC + ((unsigned<5>)imm1 << 1);
+                lpcount[L] = (unsigned<12>)imm2;    
+                */
+            }
+        }
+    }
+}
+
+Core TGC_D_XRB_NN provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_NN {
+    architectural_state {
+        XLEN=32;
+        // definitions for the architecture wrapper
+        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
+        unsigned MISA_VAL = 0b01000000100100000011000100000100;
+        unsigned MARCHID_VAL = 0x80000004;
+    }
+}

gen_input/templates/CORENAME.cpp.gtl

@@ -33,13 +33,13 @@
 def getRegisterSizes(){
 	def regs = registers.collect{it.size}
 	regs[-1]=64 // correct for NEXT_PC
-	regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+	regs+=[32, 32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
     return regs
 }
 %>
-#include "${coreDef.name.toLowerCase()}.h"
 #include "util/ities.h"
 #include <util/logging.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
@@ -51,7 +51,9 @@ constexpr std::array<const char*, ${registers.size}>    iss::arch::traits<iss::a
 constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
 constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
 
-${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}()  = default;
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
+    reg.icount = 0;
+}
 
 ${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
 

gen_input/templates/CORENAME.h.gtl

@@ -30,12 +30,14 @@
  *
  *******************************************************************************/
 <%
+import com.minres.coredsl.util.BigIntegerWithRadix
+
 def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 def getRegisterSizes(){
     def regs = registers.collect{nativeTypeSize(it.size)}
-    regs+=[32,32, 64, 64, 64, 32, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+    regs+=[32,32, 64, 64, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET
     return regs
 }
 def getRegisterOffsets(){
@@ -55,7 +57,10 @@ def byteSize(int size){
     return 128;
 }
 def getCString(def val){
-    return val.toString()
+    if(val instanceof BigIntegerWithRadix)
+        return ((BigIntegerWithRadix)val).toCString()
+    else
+        return val.toString()
 }
 %>
 #ifndef _${coreDef.name.toUpperCase()}_H_
@@ -86,7 +91,12 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
     constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
 
     enum reg_e {
-        ${registers.collect{it.name}.join(', ')}, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+        ${registers.collect{it.name}.join(', ')}, NUM_REGS,
+        TRAP_STATE=NUM_REGS,
+        PENDING_TRAP,
+        ICOUNT,
+        CYCLE,
+        INSTRET
     };
 
     using reg_t = uint${addrDataWidth}_t;
@@ -111,7 +121,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
     
-    enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
+    enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
         ${instr.instruction.name} = ${index},<%}%>
         MAX_OPCODE
     };
@@ -151,7 +161,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
 
     inline uint32_t get_last_branch() { return reg.last_branch; }
 
-
+protected:
 #pragma pack(push, 1)
     struct ${coreDef.name}_regs {<%
         registers.each { reg -> if(reg.size>0) {%> 
@@ -161,8 +171,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
         uint64_t icount = 0;
         uint64_t cycle = 0;
         uint64_t instret = 0;
-        uint32_t instruction = 0;
+        uint32_t last_branch;
-        uint32_t last_branch = 0;
     } reg;
 #pragma pack(pop)
     std::array<address_type, 4> addr_mode;

gen_input/templates/CORENAME_cyles.txt.gtl

@@ -1,12 +1,9 @@
-{
+{ 
 	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
 		{
-			"name"  :   "${instr.name}",
+			"name"  : "${instr.name}",
-			"size"  :   ${instr.length},
+			"size"  : ${instr.length},
-			"encoding": "${instr.encoding}",
+			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
-            "mask":     "${instr.mask}",
-			"branch":   ${instr.modifiesPC},
-			"delay" :   ${instr.isConditional?"[1,1]":"1"}
 		}<%}%>
 	]
 }

gen_input/templates/CORENAME_decoder.cpp.gtl

@@ -1,86 +0,0 @@
-#include "${coreDef.name.toLowerCase()}.h"
-#include <vector>
-#include <array>
-#include <cstdlib>
-#include <algorithm>
-
-namespace iss {
-namespace arch {
-namespace {
-// according to
-// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
-#ifdef __GCC__
-constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
-#elif __cplusplus < 201402L
-constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
-constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
-#else
-constexpr size_t bit_count(uint32_t u) {
-    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
-    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
-}
-#endif
-
-using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
-
-/****************************************************************************
- * start opcode definitions
- ****************************************************************************/
-struct instruction_desriptor {
-    size_t length;
-    uint32_t value;
-    uint32_t mask;
-    opcode_e op;
-};
-
-const std::array<instruction_desriptor, ${instructions.size}> instr_descr = {{
-     /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-    {${instr.length}, ${instr.encoding}, ${instr.mask}, opcode_e::${instr.instruction.name}},<%}%>
-}};
-
-}
-
-template<>
-struct instruction_decoder<${coreDef.name.toLowerCase()}> {
-    using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
-    using code_word_t=traits<${coreDef.name.toLowerCase()}>::code_word_t;
-
-    struct instruction_pattern {
-        uint32_t value;
-        uint32_t mask;
-        opcode_e id;
-    };
-
-    std::array<std::vector<instruction_pattern>, 4> qlut;
-
-    template<typename T>
-    unsigned decode_instruction(T);
-
-    instruction_decoder() {
-        for (auto instr : instr_descr) {
-            auto quadrant = instr.value & 0x3;
-            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
-        }
-        for(auto& lut: qlut){
-            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
-                return bit_count(a.mask) < bit_count(b.mask);
-            });
-        }
-    }
-};
-
-template<>
-unsigned instruction_decoder<${coreDef.name.toLowerCase()}>::decode_instruction<traits<${coreDef.name.toLowerCase()}>::code_word_t>(traits<${coreDef.name.toLowerCase()}>::code_word_t instr){
-    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
-        return !((instr&e.mask) ^ e.value );
-    });
-    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
-}
-
-
-std::unique_ptr<instruction_decoder<${coreDef.name.toLowerCase()}>> traits<${coreDef.name.toLowerCase()}>::get_decoder(){
-    return std::make_unique<instruction_decoder<${coreDef.name.toLowerCase()}>>();
-}
-
-}
-}

gen_input/templates/CORENAME_instr.yaml.gtl

@@ -12,9 +12,5 @@
 ${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
   - ${it.instruction.name}:
     encoding: ${it.encoding}
-    mask: ${it.mask}<%if(it.attributes.size) {%>
+    mask: ${it.mask}<%}}%>
-    attributes: ${it.attributes}<%}%>
-    size:   ${it.length}
-    branch:   ${it.modifiesPC}
-    delay:   ${it.isConditional?"[1,1]":"1"}<%}}%>
 

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -30,19 +30,21 @@
  *
  *******************************************************************************/
 <%
+import com.minres.coredsl.util.BigIntegerWithRadix
+
 def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 %>
+#include "../fp_functions.h"
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
 #include <util/logging.h>
 #include <sstream>
-#include <boost/coroutine2/all.hpp>
-#include <functional>
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -57,7 +59,6 @@ namespace interp {
 namespace ${coreDef.name.toLowerCase()} {
 using namespace iss::arch;
 using namespace iss::debugger;
-using namespace std::placeholders;
 
 template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
 public:
@@ -69,7 +70,6 @@ public:
     using addr_t      = typename super::addr_t;
     using reg_t       = typename traits::reg_t;
     using mem_type_e  = typename traits::mem_type_e;
-    using opcode_e    = typename traits::opcode_e;
     
     vm_impl();
 
@@ -89,9 +89,9 @@ protected:
     using compile_ret_t = virt_addr_t;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
 
-    inline const char *name(size_t index){return index<traits::reg_aliases.size()?traits::reg_aliases[index]:"illegal";}
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
-    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
+    compile_func decode_inst(code_word_t instr) ;
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
@@ -111,15 +111,15 @@ protected:
     struct instruction_pattern {
         uint32_t value;
         uint32_t mask;
-        typename arch::traits<ARCH>::opcode_e id;
+        compile_func opc;
     };
 
     std::array<std::vector<instruction_pattern>, 4> qlut;
 
     inline void raise(uint16_t trap_id, uint16_t cause){
         auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->core.reg.trap_state = trap_val;
+        this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
-        this->template get_reg<uint${addrDataWidth}_t>(traits::NEXT_PC) = std::numeric_limits<uint${addrDataWidth}_t>::max();
+        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
     }
 
     inline void leave(unsigned lvl){
@@ -130,29 +130,50 @@ protected:
         this->core.wait_until(type);
     }
 
-    using yield_t = boost::coroutines2::coroutine<void>::push_type;
+    template<typename T>
-    using coro_t = boost::coroutines2::coroutine<void>::pull_type;
+    T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-    std::vector<coro_t> spawn_blocks;
+    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
-
+        auto ret = super::template read_mem<uint8_t>(space, addr);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        return ret;
+    }
+    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint16_t>(space, addr);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        return ret;
+    }
+    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint32_t>(space, addr);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        return ret;
+    }
+    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
+        auto ret = super::template read_mem<uint64_t>(space, addr);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+        return ret;
+    }
+    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
+        super::write_mem(space, addr, data);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+    }
+    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
+        super::write_mem(space, addr, data);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+    }
+    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
+        super::write_mem(space, addr, data);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+    }
+    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
+        super::write_mem(space, addr, data);
+        if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0;
+    }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
         auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
-    
-    inline void process_spawn_blocks() {
-        if(spawn_blocks.size()==0) return;
-        for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
-             if(*it){
-                 (*it)();
-                 ++it;
-             } else
-                 spawn_blocks.erase(it);
-    }
-<%functions.each{ it.eachLine { %>
-    ${it}<%}%>
-<%}%>
 
 private:
     /****************************************************************************
@@ -162,13 +183,74 @@ private:
         size_t length;
         uint32_t value;
         uint32_t mask;
-        typename arch::traits<ARCH>::opcode_e op;
+        compile_func op;
     };
 
     const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
+        /* instruction ${instr.instruction.name} */
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
     }};
+ 
+    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
+    /* instruction ${idx}: ${instr.name} */
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
+        // pre execution stuff
+        auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+        auto NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+        *PC=*NEXT_PC;
+        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
+        *trap_state = *reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PENDING_TRAP]);
+        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, ${idx});
+        <%instr.fields.eachLine{%>${it}
+        <%}%>if(this->disass_enabled){
+            /* generate console output when executing the command */
+            <%instr.disass.eachLine{%>${it}
+            <%}%>
+        }
+        // used registers<%instr.usedVariables.each{ k,v->
+            if(v.isArray) {%>
+        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
+        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
+        <%}}%>// calculate next pc value
+        *NEXT_PC = *PC + ${instr.length/8};
+        // execute instruction
+        try {
+        <%instr.behavior.eachLine{%>${it}
+        <%}%>} catch(...){}
+        // post execution stuff
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
+        // trap check
+        if(*trap_state!=0){
+            super::core.enter_trap(*trap_state, pc.val, instr);
+        } else {
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
+        }
+        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
+        pc.val=*NEXT_PC;
+        return pc;
+    }
+    <%}%>
+    /****************************************************************************
+     * end opcode definitions
+     ****************************************************************************/
+    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
+        this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
+        uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+        uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+        *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
+        raise(0,  2);
+        // post execution stuff
+        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
+        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
+        // trap check
+        if(*trap_state!=0){
+            super::core.enter_trap(*trap_state, pc.val, instr);
+        }
+        pc.val=*NEXT_PC;
+        return pc;
+    }
 
     //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
@@ -208,7 +290,6 @@ constexpr size_t bit_count(uint32_t u) {
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
-    unsigned id=0;
     for (auto instr : instr_descr) {
         auto quadrant = instr.value & 0x3;
         qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
@@ -229,82 +310,37 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
 }
 
 template <typename ARCH>
-typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
+typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
     for(auto& e: qlut[instr&0x3]){
-        if(!((instr&e.mask) ^ e.value )) return e.id;
+        if(!((instr&e.mask) ^ e.value )) return e.opc;
     }
-    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
+    return &this_class::illegal_intruction;
 }
 
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
-    auto pc=start;
-    auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-    auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-    auto& trap_state = this->core.reg.trap_state;
-    auto& icount =  this->core.reg.icount;
-    auto& cycle =  this->core.reg.cycle;
-    auto& instret =  this->core.reg.instret;
-    auto& instr =  this->core.reg.instruction;
     // we fetch at max 4 byte, alignment is 2
-    auto *const data = reinterpret_cast<uint8_t*>(&instr);
+    code_word_t insn = 0;
-
+    auto *const data = (uint8_t *)&insn;
+    auto pc=start;
     while(!this->core.should_stop() &&
-            !(is_count_limit_enabled(cond) && icount >= icount_limit)){
+            !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
-        if(fetch_ins(pc, data)!=iss::Ok){
+        auto res = fetch_ins(pc, data);
+        if(res!=iss::Ok){
             this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
             pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
-                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+                    (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            auto inst_id = decode_inst_id(instr);
+            auto f = decode_inst(insn);
-            // pre execution stuff
+            auto old_pc = pc.val;
-             this->core.reg.last_branch = 0;
+            pc = (this->*f)(pc, insn);
-            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
-            switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
-            case arch::traits<ARCH>::opcode_e::${instr.name}: {
-                <%instr.fields.eachLine{%>${it}
-                <%}%>if(this->disass_enabled){
-                    /* generate console output when executing the command */<%instr.disass.eachLine{%>
-                    ${it}<%}%>
-                }
-                // used registers<%instr.usedVariables.each{ k,v->
-                if(v.isArray) {%>
-                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
-                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
-                <%}}%>// calculate next pc value
-                *NEXT_PC = *PC + ${instr.length/8};
-                // execute instruction<%instr.behavior.eachLine{%>
-                ${it}<%}%>
-                TRAP_${instr.name}:break;
-            }// @suppress("No break at end of case")<%}%>
-            default: {
-                *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
-                raise(0,  2);
-            }
-            }
-            // post execution stuff
-            process_spawn_blocks();
-            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
-            // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt
-            //    this->core.reg.trap_state =  this->core.reg.pending_trap;
-            // trap check
-            if(trap_state!=0){
-                super::core.enter_trap(trap_state, pc.val, instr);
-            } else {
-                icount++;
-                instret++;
-            }
-            cycle++;
-            pc.val=*NEXT_PC;
-            this->core.reg.PC = this->core.reg.NEXT_PC;
-            this->core.reg.trap_state =  this->core.reg.pending_trap;
         }
     }
     return pc;
 }
 
-}
+} // namespace mnrv32
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -314,30 +350,3 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 }
 } // namespace interp
 } // namespace iss
-
-#include <iss/factory.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-namespace iss {
-namespace {
-std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}
-extern "C" {
-	bool* get_${coreDef.name.toLowerCase()}_interp_creators() {
-		return iss::dummy.data();
-	}
-}

gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl

@@ -30,10 +30,10 @@
  *
  *******************************************************************************/
 
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/server.h>
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <iss/arch/riscv_hart_m_p.h>
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>

gen_input/templates/tcc/CORENAME_cyles.txt.gtl

@@ -0,0 +1,9 @@
+{ 
+	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
+		{
+			"name"  : "${instr.name}",
+			"size"  : ${instr.length},
+			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+		}<%}%>
+	]
+}

gen_input/templates/tcc/incl-CORENAME.h.gtl

@@ -0,0 +1,223 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+<% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getTypeSize(size){
+	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
+}
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#ifndef _${coreDef.name.toUpperCase()}_H_
+#define _${coreDef.name.toUpperCase()}_H_
+
+#include <array>
+#include <iss/arch/traits.h>
+#include <iss/arch_if.h>
+#include <iss/vm_if.h>
+
+namespace iss {
+namespace arch {
+
+struct ${coreDef.name.toLowerCase()};
+
+template <> struct traits<${coreDef.name.toLowerCase()}> {
+
+	constexpr static char const* const core_type = "${coreDef.name}";
+    
+  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
+ 		{"${getRegisterNames().join("\", \"")}"}};
+ 
+  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
+ 		{"${getRegisterAliasNames().join("\", \"")}"}};
+
+    enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
+
+    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
+
+    enum reg_e {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        ${reg.name}${it},<%
+                }
+            } else if(reg instanceof Register){ %>
+        ${reg.name},<%  
+            }
+        }%>
+        NUM_REGS,
+        NEXT_${pc.name}=NUM_REGS,
+        TRAP_STATE,
+        PENDING_TRAP,
+        MACHINE_STATE,
+        LAST_BRANCH,
+        ICOUNT<% 
+     	allRegs.each { reg -> 
+    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
+        ${reg.name} = ${aliasname}<%
+            }
+        }%>
+    };
+
+    using reg_t = uint${regDataWidth}_t;
+
+    using addr_t = uint${addrDataWidth}_t;
+
+    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
+
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
+
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
+
+ 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
+ 		{${regSizes.join(",")}}};
+
+    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
+    	{${regOffsets.join(",")}}};
+
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
+
+    enum sreg_flag_e { FLAGS };
+
+    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
+};
+
+struct ${coreDef.name.toLowerCase()}: public arch_if {
+
+    using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
+    using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
+    using reg_t =  typename traits<${coreDef.name.toLowerCase()}>::reg_t;
+    using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
+
+    ${coreDef.name.toLowerCase()}();
+    ~${coreDef.name.toLowerCase()}();
+
+    void reset(uint64_t address=0) override;
+
+    uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    bool get_flag(int flag) override {return false;}
+    void set_flag(int, bool value) override {};
+    /// deprecated
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
+
+    inline uint64_t get_icount() { return reg.icount; }
+
+    inline bool should_stop() { return interrupt_sim; }
+
+    inline uint64_t stop_code() { return interrupt_sim; }
+
+    inline phys_addr_t v2p(const iss::addr_t& addr){
+        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
+        } else
+            return virt2phys(addr);
+    }
+
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
+
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
+
+    inline uint32_t get_last_branch() { return reg.last_branch; }
+
+protected:
+    struct ${coreDef.name}_regs {<%
+     	allRegs.each { reg -> 
+    		if( reg instanceof RegisterFile) {
+    			(reg.range.right..reg.range.left).each{%>
+        uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
+                }
+            } else if(reg instanceof Register){ %>
+        uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
+            }
+        }%>
+        uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
+        uint64_t icount = 0;
+    } reg;
+
+    std::array<address_type, 4> addr_mode;
+    
+    uint64_t interrupt_sim=0;
+<%
+def fcsr = allRegs.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
+	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
+<%} else { %>
+	uint32_t get_fcsr(){return 0;}
+	void set_fcsr(uint32_t val){}
+<%}%>
+};
+
+}
+}            
+#endif /* _${coreDef.name.toUpperCase()}_H_ */

gen_input/templates/tcc/src-CORENAME.cpp.gtl

@@ -0,0 +1,107 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+ <% 
+import com.minres.coredsl.coreDsl.Register
+import com.minres.coredsl.coreDsl.RegisterFile
+import com.minres.coredsl.coreDsl.RegisterAlias
+def getOriginalName(reg){
+    if( reg.original instanceof RegisterFile) {
+    	if( reg.index != null ) {
+        	return reg.original.name+generator.generateHostCode(reg.index)
+        } else {
+        	return reg.original.name
+        }
+    } else if(reg.original instanceof Register){
+        return reg.original.name
+    }
+}
+def getRegisterNames(){
+	def regNames = []
+ 	allRegs.each { reg -> 
+		if( reg instanceof RegisterFile) {
+			(reg.range.right..reg.range.left).each{
+    			regNames+=reg.name.toLowerCase()+it
+            }
+        } else if(reg instanceof Register){
+    		regNames+=reg.name.toLowerCase()
+        }
+    }
+    return regNames
+}
+def getRegisterAliasNames(){
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
+		if( reg instanceof RegisterFile) {
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
+        } else if(reg instanceof Register){
+    		regMap[reg.name]?:reg.name.toLowerCase()
+        }
+ 	}.flatten()
+}
+%>
+#include "util/ities.h"
+#include <util/logging.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <cstdio>
+#include <cstring>
+#include <fstream>
+
+using namespace iss::arch;
+
+constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
+constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
+constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
+constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
+
+${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
+    reg.icount = 0;
+}
+
+${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
+
+void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
+    reg.PC=address;
+    reg.NEXT_PC=reg.PC;
+    reg.trap_state=0;
+    reg.machine_state=0x3;
+    reg.icount=0;
+}
+
+uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
+	return reinterpret_cast<uint8_t*>(&reg);
+}
+
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
+    return phys_addr_t(pc); // change logical address to physical address
+}
+

gen_input/templates/tcc/vm-vm_CORENAME.cpp.gtl

@@ -31,6 +31,7 @@
  *******************************************************************************/
 
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
@@ -54,12 +55,10 @@ using namespace iss::debugger;
 
 template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
 public:
-    using traits = arch::traits<ARCH>;
     using super       = typename iss::tcc::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;
     using code_word_t = typename super::code_word_t;
-    using mem_type_e  = typename traits::mem_type_e;    
     using addr_t      = typename super::addr_t;
     using tu_builder  = typename super::tu_builder;
 
@@ -83,7 +82,7 @@ protected:
     using compile_ret_t = std::tuple<continuation_e>;
     using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
 
-    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
+    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
 
     void setup_module(std::string m) override {
         super::setup_module(m);
@@ -105,10 +104,10 @@ protected:
 
     inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
         switch(reg_num){
-        case traits::NEXT_PC:
+        case traits<ARCH>::NEXT_PC:
             tu("*next_pc = {:#x};", pc.val);
             break;
-        case traits::PC:
+        case traits<ARCH>::PC:
             tu("*pc = {:#x};", pc.val);
             break;
         default:
@@ -124,7 +123,7 @@ protected:
     // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
     enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
     enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
-    enum { LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)), LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16)) };
+    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
 
     std::array<compile_func, LUT_SIZE> lut;
 
@@ -171,12 +170,6 @@ protected:
         }
         return lut_val;
     }
-    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
-    inline S sext(U from) {
-        auto mask = (1ULL<<W) - 1;
-        auto sign_mask = 1ULL<<(W-1);
-        return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    }    
 
 private:
     /****************************************************************************
@@ -192,28 +185,13 @@ private:
     const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
         /* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, 0b${instr.value}, 0b${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
     }};
  
     /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
     /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
+    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, tu_builder& tu){<%instr.code.eachLine{%>
-        tu("${instr.name}_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,${idx});
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate console output when executing the command */<%instr.disass.eachLine{%>
-            ${it}<%}%>
-        }
-        auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc=pc+ ${instr.length/8};
-        gen_set_pc(tu, pc, traits::NEXT_PC);
-        tu.open_scope();<%instr.behavior.eachLine{%>
         ${it}<%}%>
-        tu.close_scope();
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC,${idx});
-        gen_trap_check(tu);
-        return returnValue;
     }
     <%}%>
     /****************************************************************************
@@ -255,20 +233,20 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
     // we fetch at max 4 byte, alignment is 2
     enum {TRAP_ID=1<<16};
     code_word_t insn = 0;
-    // const typename traits::addr_t upper_bits = ~traits::PGMASK;
+    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
     phys_addr_t paddr(pc);
     auto *const data = (uint8_t *)&insn;
     paddr = this->core.v2p(pc);
-//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-//        auto res = this->core.read(paddr, 2, data);
+        auto res = this->core.read(paddr, 2, data);
-//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-//        }
+        }
-//    } else {
+    } else {
         auto res = this->core.read(paddr, 4, data);
         if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-//    }
+    }
     if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
@@ -282,13 +260,13 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
     tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
     tu("leave_trap(core_ptr, {});", lvl);
-    tu.store(traits::NEXT_PC, tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN));
+    tu.store(tu.read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN),traits<ARCH>::NEXT_PC);
-    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(), 32),traits<ARCH>::LAST_BRANCH);
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
@@ -296,8 +274,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned t
 
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("trap_entry:");
-    tu("enter_trap(core_ptr, *trap_state, *pc, 0);");
+    tu("enter_trap(core_ptr, *trap_state, *pc);");
-    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(),32));
+    tu.store(tu.constant(std::numeric_limits<uint32_t>::max(),32),traits<ARCH>::LAST_BRANCH);
     tu("return *next_pc;");
 }
 
@@ -309,32 +287,5 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
-} // namesapce tcc
+}
 } // namespace iss
-
-#include <iss/factory.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-namespace iss {
-namespace {
-std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
-        })
-};
-}
-}
-extern "C" {
-	bool* get_${coreDef.name.toLowerCase()}_tcc_creators() {
-		return iss::dummy.data();
-	}
-}

incl/iss/arch/.gitignore

@@ -0,0 +1 @@
+/tgc_*.h

incl/iss/arch/riscv_hart_common.h

@@ -43,7 +43,7 @@ namespace arch {
 
 enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
 
-enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8, FEAT_TCM=16};
+enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8};
 
 enum riscv_csr {
     /* user-level CSR */
@@ -51,18 +51,12 @@ enum riscv_csr {
     ustatus = 0x000,
     uie = 0x004,
     utvec = 0x005,
-    utvt = 0x007, //CLIC
     // User Trap Handling
     uscratch = 0x040,
     uepc = 0x041,
     ucause = 0x042,
     utval = 0x043,
     uip = 0x044,
-    uxnti = 0x045, //CLIC
-    uintstatus   = 0xCB1, // MRW Current interrupt levels (CLIC) - addr subject to change
-    uintthresh   = 0x047, // MRW Interrupt-level threshold (CLIC) - addr subject to change
-    uscratchcsw  = 0x048, // MRW Conditional scratch swap on priv mode change (CLIC)
-    uscratchcswl = 0x049, // MRW Conditional scratch swap on level change (CLIC)
     // User Floating-Point CSRs
     fflags = 0x001,
     frm = 0x002,
@@ -120,10 +114,11 @@ enum riscv_csr {
     mtval = 0x343,
     mip = 0x344,
     mxnti = 0x345, //CLIC
-    mintstatus   = 0xFB1, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
-    mintthresh   = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change
     mscratchcsw  = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
     mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
+    mintthresh   = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    mclicbase    = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
     // Physical Memory Protection
     pmpcfg0 = 0x3A0,
     pmpcfg1 = 0x3A1,
@@ -193,7 +188,7 @@ enum {
 
 template <typename T> inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); }
 
-enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4};
+enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3 };
 
 enum {
     ISA_A = 1,
@@ -219,15 +214,6 @@ struct vm_info {
     bool is_active() { return levels; }
 };
 
-struct feature_config {
-    uint64_t clic_base{0xc0000000};
-    unsigned clic_int_ctl_bits{4};
-    unsigned clic_num_irq{16};
-    unsigned clic_num_trigger{0};
-    uint64_t tcm_base{0x10000000};
-    uint64_t tcm_size{0x8000};
-};
-
 class trap_load_access_fault : public trap_access {
 public:
     trap_load_access_fault(uint64_t badaddr)
@@ -253,49 +239,6 @@ public:
     trap_store_page_fault(uint64_t badaddr)
     : trap_access(15 << 16, badaddr) {}
 };
-
-inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, unsigned length) {
-    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
-    switch (offs & 0x3) {
-    case 0:
-        for (auto i = 0U; i < length; ++i)
-            *(data + i) = *(reg_ptr + i);
-    break;
-    case 1:
-        for (auto i = 0U; i < length; ++i)
-            *(data + i) = *(reg_ptr + 1 + i);
-    break;
-    case 2:
-        for (auto i = 0U; i < length; ++i)
-            *(data + i) = *(reg_ptr + 2 + i);
-    break;
-    case 3:
-        *data = *(reg_ptr + 3);
-    break;
-    }
-}
-
-inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t *const data, unsigned length) {
-    auto reg_ptr = reinterpret_cast<uint8_t*>(&reg);
-    switch (offs & 0x3) {
-    case 0:
-        for (auto i = 0U; i < length; ++i)
-            *(reg_ptr + i) = *(data + i);
-    break;
-    case 1:
-        for (auto i = 0U; i < length; ++i)
-            *(reg_ptr + 1 + i) = *(data + i);
-    break;
-    case 2:
-        for (auto i = 0U; i < length; ++i)
-            *(reg_ptr + 2 + i) = *(data + i);
-    break;
-    case 3:
-        *(reg_ptr + 3) = *data ;
-    break;
-    }
-}
-
 }
 }
 

incl/iss/arch/riscv_hart_m_p.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2019 - 2023 MINRES Technologies GmbH
+ * Copyright (C) 2021 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -97,10 +97,8 @@ public:
     using reg_t = typename core::reg_t;
     using addr_t = typename core::addr_t;
 
-    using rd_csr_f    = iss::status (this_class::*)(unsigned addr, reg_t &);
+    using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
-    using wr_csr_f    = iss::status (this_class::*)(unsigned addr, reg_t);
+    using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
-    using mem_read_f  = iss::status(phys_addr_t addr, unsigned, uint8_t *const);
-    using mem_write_f = iss::status(phys_addr_t addr, unsigned, uint8_t const *const);
 
     // primary template
     template <class T, class Enable = void> struct hart_state {};
@@ -172,94 +170,17 @@ public:
             return 0b00000000000000000001100010001000;
         }
     };
-
-    // specialization 64bit
-    template <typename T> class hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
-    public:
-        BEGIN_BF_DECL(mstatus_t, T);
-        // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
-        BF_FIELD(SD, 63, 1);
-        // value of XLEN for S-mode
-        BF_FIELD(SXL, 34, 2);
-        // value of XLEN for U-mode
-        BF_FIELD(UXL, 32, 2);
-        // Trap SRET
-        BF_FIELD(TSR, 22, 1);
-        // Timeout Wait
-        BF_FIELD(TW, 21, 1);
-        // Trap Virtual Memory
-        BF_FIELD(TVM, 20, 1);
-        // Make eXecutable Readable
-        BF_FIELD(MXR, 19, 1);
-        // permit Supervisor User Memory access
-        BF_FIELD(SUM, 18, 1);
-        // Modify PRiVilege
-        BF_FIELD(MPRV, 17, 1);
-        // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty
-        BF_FIELD(XS, 15, 2);
-        // floating-point unit status Off/Initial/Clean/Dirty
-        BF_FIELD(FS, 13, 2);
-        // machine previous privilege
-        BF_FIELD(MPP, 11, 2);
-        // supervisor previous privilege
-        BF_FIELD(SPP, 8, 1);
-        // previous machine interrupt-enable
-        BF_FIELD(MPIE, 7, 1);
-        // previous supervisor interrupt-enable
-        BF_FIELD(SPIE, 5, 1);
-        // previous user interrupt-enable
-        BF_FIELD(UPIE, 4, 1);
-        // machine interrupt-enable
-        BF_FIELD(MIE, 3, 1);
-        // supervisor interrupt-enable
-        BF_FIELD(SIE, 1, 1);
-        // user interrupt-enable
-        BF_FIELD(UIE, 0, 1);
-        END_BF_DECL();
-
-        mstatus_t mstatus;
-
-        static const reg_t mstatus_reset_val = 0x1800;
-
-        void write_mstatus(T val) {
-            auto mask = get_mask() &0xff; // MPP is hardcode as 0x3
-            auto new_val = (mstatus.backing.val & ~mask) | (val & mask);
-            mstatus = new_val;
-        }
-
-        static constexpr T get_mask() {
-            //return 0x8000000f007ff9ddULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011
-            //
-            //                +-TSR
-            //                |+-TW
-            //                ||+-TVM
-            //                |||+-MXR
-            //                ||||+-SUM
-            //                |||||+-MPRV
-            //                |||||| +-XS
-            //                |||||| | +-FS
-            //                |||||| | | +-MPP
-            //                |||||| | | |  +-SPP
-            //                |||||| | | |  |+-MPIE
-            //                ||||||/|/|/|  ||   +-MIE
-            return 0b00000000000000000001100010001000;
-        }
-    };
-
     using hart_state_type = hart_state<reg_t>;
 
     constexpr reg_t get_irq_mask() {
         return 0b100010001000; // only machine mode is supported
     }
 
-    constexpr bool has_compressed() {
-        return traits<BASE>::MISA_VAL&0b0100;
-    }
     constexpr reg_t get_pc_mask() {
-        return has_compressed()?(reg_t)~1:(reg_t)~3;
+        return traits<BASE>::MISA_VAL&0b0100?~1:~3;
     }
 
-    riscv_hart_m_p(feature_config cfg = feature_config{});
+    riscv_hart_m_p();
     virtual ~riscv_hart_m_p() = default;
 
     void reset(uint64_t address) override;
@@ -271,27 +192,32 @@ public:
     iss::status write(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
-    uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
+    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
-    uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
+    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    uint64_t leave_trap(uint64_t flags) override;
+    virtual uint64_t leave_trap(uint64_t flags) override;
 
     const reg_t& get_mhartid() const { return mhartid_reg;	}
 	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
 
     void disass_output(uint64_t pc, const std::string instr) override {
         CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [s:0x{:x};c:{}]",
-                pc, instr, (reg_t)state.mstatus, this->reg.icount + cycle_offset);
+                pc, instr, (reg_t)state.mstatus, this->reg.icount);
     };
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
 
+    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
+        mem_read_cb = memReadCb;
+    }
+
+    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
+        mem_write_cb = memWriteCb;
+    }
+
     void set_csr(unsigned addr, reg_t val){
         csr[addr & csr.page_addr_mask] = val;
     }
 
-    void set_irq_num(unsigned i) {
-        mcause_max_irq=1<<util::ilog2(i);
-    }
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
@@ -304,26 +230,18 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        uint64_t get_pc() override { return arch.reg.PC; };
+        virtual uint64_t get_pc() { return arch.get_pc(); };
 
-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
+        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
 
-        uint64_t get_instr_word() override { return arch.reg.instruction; }
+        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
-
-        uint64_t get_instr_count() override { return arch.reg.icount; }
-
-        uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
-
-        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
-
-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
-
-        bool is_branch_taken() override { return arch.reg.last_branch; };
 
         riscv_hart_m_p<BASE, FEAT> &arch;
     };
 
     friend struct riscv_instrumentation_if;
+    addr_t get_pc() { return this->reg.PC; }
+    addr_t get_next_pc() { return this->reg.NEXT_PC; }
 
     virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
     virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
@@ -356,6 +274,7 @@ protected:
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
     std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
     uint8_t clic_cfg_reg{0};
+    uint32_t clic_info_reg{0};
     std::array<uint32_t, 32> clic_inttrig_reg;
     union clic_int_reg_t {
         struct{
@@ -367,10 +286,6 @@ protected:
         uint32_t raw;
     };
     std::vector<clic_int_reg_t> clic_int_reg;
-    uint8_t clic_mprev_lvl{0};
-    uint8_t clic_mact_lvl{0};
-
-    std::vector<uint8_t> tcm;
 
     iss::status read_csr_reg(unsigned addr, reg_t &val);
     iss::status write_csr_reg(unsigned addr, reg_t val);
@@ -384,71 +299,51 @@ protected:
     iss::status read_time(unsigned addr, reg_t &val);
     iss::status read_status(unsigned addr, reg_t &val);
     iss::status write_status(unsigned addr, reg_t val);
-    iss::status read_cause(unsigned addr, reg_t &val);
     iss::status write_cause(unsigned addr, reg_t val);
     iss::status read_ie(unsigned addr, reg_t &val);
     iss::status write_ie(unsigned addr, reg_t val);
     iss::status read_ip(unsigned addr, reg_t &val);
+    iss::status write_ip(unsigned addr, reg_t val);
     iss::status read_hartid(unsigned addr, reg_t &val);
     iss::status write_epc(unsigned addr, reg_t val);
-    iss::status read_intstatus(unsigned addr, reg_t& val);
+    iss::status write_intstatus(unsigned addr, reg_t val);
     iss::status write_intthresh(unsigned addr, reg_t val);
-    iss::status write_xtvt(unsigned addr, reg_t val);
     iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
     iss::status read_dcsr_reg(unsigned addr, reg_t &val);
     iss::status write_dcsr_reg(unsigned addr, reg_t val);
     iss::status read_dpc_reg(unsigned addr, reg_t &val);
     iss::status write_dpc_reg(unsigned addr, reg_t val);
 
-    virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
-    virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
-
-    void register_custom_csr_rd(unsigned addr){
-        csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
-    }
-    void register_custom_csr_wr(unsigned addr){
-        csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
-    }
-
     reg_t mhartid_reg{0x0};
+    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
+    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
 
     void check_interrupt();
     bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
-    std::vector<std::tuple<uint64_t, uint64_t>> memfn_range;
+    uint64_t clic_base_addr{0};
-    std::vector<std::function<mem_read_f>> memfn_read;
+    unsigned clic_num_irq{0};
-    std::vector<std::function<mem_write_f>> memfn_write;
+    unsigned clic_num_trigger{0};
-    void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
+    unsigned mcause_max_irq{16};
-    feature_config cfg;
-    uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
     inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
-    std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
-    replace_mem_access(std::function<mem_read_f> rd, std::function<mem_write_f> wr){
-        std::pair<std::function<mem_read_f>, std::function<mem_write_f>> ret{hart_mem_rd_delegate, hart_mem_wr_delegate};
-        hart_mem_rd_delegate = rd;
-        hart_mem_wr_delegate = wr;
-        return ret;
-    }
-    std::function<mem_read_f> hart_mem_rd_delegate;
-    std::function<mem_write_f> hart_mem_wr_delegate;
 };
 
 template <typename BASE, features_e FEAT>
-riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
+riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
 : state()
-, instr_if(*this)
+, instr_if(*this) {
-, cfg(cfg) {
     // reset values
     csr[misa] = traits<BASE>::MISA_VAL;
     csr[mvendorid] = 0x669;
     csr[marchid] = traits<BASE>::MARCHID_VAL;
     csr[mimpid] = 1;
+    csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file
 
     uart_buf.str("");
     for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
-    if(traits<BASE>::XLEN==32) for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
+    for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
@@ -459,45 +354,39 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
     for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
     }
-    if(traits<BASE>::XLEN==32) for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
+    for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 4> roaddrs{{misa, mvendorid, marchid, mimpid}};
+    const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
-    for(auto addr: roaddrs) {
+    for(auto addr: addrs) {
-        csr_rd_cb[addr] = &this_class::read_csr_reg;
-        csr_wr_cb[addr] = &this_class::write_null;
-    }
-    const std::array<unsigned, 4> rwaddrs{{mepc, mtvec, mscratch, mtval}};
-    for(auto addr: rwaddrs) {
         csr_rd_cb[addr] = &this_class::read_csr_reg;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // special handling & overrides
     csr_rd_cb[time] = &this_class::read_time;
-    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
+    csr_rd_cb[timeh] = &this_class::read_time;
     csr_rd_cb[cycle] = &this_class::read_cycle;
-    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
+    csr_rd_cb[cycleh] = &this_class::read_cycle;
     csr_rd_cb[instret] = &this_class::read_instret;
-    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;
+    csr_rd_cb[instreth] = &this_class::read_instret;
 
     csr_rd_cb[mcycle] = &this_class::read_cycle;
     csr_wr_cb[mcycle] = &this_class::write_cycle;
-    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    csr_rd_cb[mcycleh] = &this_class::read_cycle;
-    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
+    csr_wr_cb[mcycleh] = &this_class::write_cycle;
     csr_rd_cb[minstret] = &this_class::read_instret;
     csr_wr_cb[minstret] = &this_class::write_instret;
-    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
+    csr_rd_cb[minstreth] = &this_class::read_instret;
-    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
+    csr_wr_cb[minstreth] = &this_class::write_instret;
     csr_rd_cb[mstatus] = &this_class::read_status;
     csr_wr_cb[mstatus] = &this_class::write_status;
-    csr_rd_cb[mcause] = &this_class::read_cause;
     csr_wr_cb[mcause] = &this_class::write_cause;
     csr_rd_cb[mtvec] = &this_class::read_tvec;
     csr_wr_cb[mepc] = &this_class::write_epc;
     csr_rd_cb[mip] = &this_class::read_ip;
-    csr_wr_cb[mip] = &this_class::write_null;
+    csr_wr_cb[mip] = &this_class::write_ip;
     csr_rd_cb[mie] = &this_class::read_ie;
     csr_wr_cb[mie] = &this_class::write_ie;
     csr_rd_cb[mhartid] = &this_class::read_hartid;
@@ -505,41 +394,6 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
     csr_wr_cb[mvendorid] = &this_class::write_null;
     csr_wr_cb[marchid] = &this_class::write_null;
     csr_wr_cb[mimpid] = &this_class::write_null;
-    if(FEAT & FEAT_CLIC) {
-        csr_rd_cb[mtvt] = &this_class::read_csr_reg;
-        csr_wr_cb[mtvt] = &this_class::write_xtvt;
-//        csr_rd_cb[mxnti] = &this_class::read_csr_reg;
-//        csr_wr_cb[mxnti] = &this_class::write_csr_reg;
-        csr_rd_cb[mintstatus] = &this_class::read_intstatus;
-        csr_wr_cb[mintstatus] = &this_class::write_null;
-//        csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
-//        csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
-//        csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
-//        csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg;
-        csr_rd_cb[mintthresh] = &this_class::read_csr_reg;
-        csr_wr_cb[mintthresh] = &this_class::write_intthresh;
-        clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
-        clic_cfg_reg=0x20;
-        clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
-        csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
-        insert_mem_range(cfg.clic_base, 0x5000UL,
-                [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
-                [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
-    }
-    if(FEAT & FEAT_TCM) {
-        tcm.resize(cfg.tcm_size);
-        std::function<mem_read_f> read_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t * const data) {
-            auto offset=addr.val-this->cfg.tcm_base;
-            std::copy(tcm.data() + offset, tcm.data() + offset + length, data);
-            return iss::Ok;
-        };
-        std::function<mem_write_f> write_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {
-            auto offset=addr.val-this->cfg.tcm_base;
-            std::copy(data, data + length, tcm.data() + offset);
-            return iss::Ok;
-        };
-        insert_mem_range(cfg.tcm_base, cfg.tcm_size, read_clic_cb, write_clic_cb);
-    }
     if(FEAT & FEAT_DEBUG){
         csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
         csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
@@ -550,12 +404,6 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
         csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
         csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
     }
-    hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status {
-        return this->read_mem(a, l, d);
-    };
-    hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status {
-        return this->write_mem(a, l, d);
-    };
 }
 
 template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT>::load_file(std::string name, int type) {
@@ -563,10 +411,10 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
     if (fp) {
         std::array<char, 5> buf;
         auto n = fread(buf.data(), 1, 4, fp);
-        fclose(fp);
         if (n != 4) throw std::runtime_error("input file has insufficient size");
         buf[4] = 0;
         if (strcmp(buf.data() + 1, "ELF") == 0) {
+            fclose(fp);
             // Create elfio reader
             ELFIO::elfio reader;
             // Load ELF data
@@ -619,23 +467,9 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
+        throw std::runtime_error("memory load file is not a valid elf file");
     }
-    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    throw std::runtime_error("memory load file not found");
-}
-
-template<typename BASE, features_e FEAT>
-inline void riscv_hart_m_p<BASE, FEAT>::insert_mem_range(uint64_t base, uint64_t size, std::function<mem_read_f> rd_f,
-        std::function<mem_write_f> wr_fn) {
-    std::tuple<uint64_t, uint64_t> entry{base, size};
-    auto it = std::upper_bound( memfn_range.begin(), memfn_range.end(), entry,
-            [](std::tuple<uint64_t, uint64_t> const& a, std::tuple<uint64_t, uint64_t> const& b){
-        return std::get<0>(a)<std::get<0>(b);
-    });
-    auto idx = std::distance(memfn_range.begin(), it);
-    memfn_range.insert(it, entry);
-    memfn_read.insert(std::begin(memfn_read)+idx, rd_f);
-    memfn_write.insert(std::begin(memfn_write)+idx, wr_fn);
 }
 
 template <typename BASE, features_e FEAT>
@@ -653,40 +487,29 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
     try {
         switch (space) {
         case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access)? (has_compressed()? 2 : 4) : length;
+            if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
-            if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
-                if (is_debug(access)) throw trap_access(0, addr);
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1UL << 31); // issue trap 0
+                this->reg.trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
             try {
-                if(!is_debug(access) && (addr&(alignment-1))){
+                auto alignment = access == iss::access_type::FETCH? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
-                    this->reg.trap_state = (1UL << 31) | 4<<16;
+                if(alignment>1 && (addr&(alignment-1))){
+                    this->reg.trap_state = 1<<31 | 4<<16;
                     fault_data=addr;
                     return iss::Err;
                 }
-                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
+                auto res = type==iss::address_type::PHYSICAL?
-                auto res = iss::Err;
+                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
-                if(access != access_type::FETCH && memfn_range.size()){
+                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
-                        return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
-                    });
-                    if(it!=std::end(memfn_range)) {
-                        auto idx = std::distance(std::begin(memfn_range), it);
-                        res = memfn_read[idx](phys_addr, length, data);
-                    } else
-                        res = hart_mem_rd_delegate( phys_addr, length, data);
-                } else {
-                    res = hart_mem_rd_delegate( phys_addr, length, data);
-                }
                 if (unlikely(res != iss::Ok)){
-                    this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
+                    this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->reg.trap_state = (1UL << 31) | ta.id;
+                this->reg.trap_state = (1 << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -712,7 +535,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        this->reg.trap_state = (1 << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }
@@ -750,36 +573,25 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
             if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                 fault_data = addr;
                 if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->reg.trap_state = (1UL << 31); // issue trap 0
+                this->reg.trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
             try {
-                if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
+                if(!(access && iss::access_type::DEBUG) &&  length>1 && (addr&(length-1))){
-                    this->reg.trap_state = (1UL << 31) | 6<<16;
+                    this->reg.trap_state = 1<<31 | 6<<16;
                     fault_data=addr;
                     return iss::Err;
                 }
-                auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
+                auto res = type==iss::address_type::PHYSICAL?
-                auto res = iss::Err;
+                        write_mem(phys_addr_t{access, space, addr}, length, data):
-                if(access != access_type::FETCH && memfn_range.size()){
+                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
-                    auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
-                        return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
-                    });
-                    if(it!=std::end(memfn_range)) {
-                        auto idx = std::distance(std::begin(memfn_range), it);
-                        res = memfn_write[idx]( phys_addr, length, data);
-                    } else
-                        res = write_mem( phys_addr, length, data);
-                } else {
-                    res = write_mem( phys_addr, length, data);
-                }
                 if (unlikely(res != iss::Ok)) {
-                    this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->reg.trap_state = (1UL << 31) | ta.id;
+                this->reg.trap_state = (1 << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -839,7 +651,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        this->reg.trap_state = (1 << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }
@@ -889,6 +701,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
     if (addr == mcycle) {
         val = static_cast<reg_t>(cycle_val);
     } else if (addr == mcycleh) {
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
         val = static_cast<reg_t>(cycle_val >> 32);
     }
     return iss::Ok;
@@ -896,6 +709,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cycle(unsigned addr, reg_t val) {
     if (sizeof(typename traits<BASE>::reg_t) != 4) {
+        if (addr == mcycleh)
+            return iss::Err;
         mcycle_csr = static_cast<uint64_t>(val);
     } else {
         if (addr == mcycle) {
@@ -912,6 +727,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
     if ((addr&0xff) == (minstret&0xff)) {
         val = static_cast<reg_t>(this->reg.instret);
     } else if ((addr&0xff) == (minstreth&0xff)) {
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
         val = static_cast<reg_t>(this->reg.instret >> 32);
     }
     return iss::Ok;
@@ -919,6 +735,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_instret(unsigned addr, reg_t val) {
     if (sizeof(typename traits<BASE>::reg_t) != 4) {
+        if ((addr&0xff) == (minstreth&0xff))
+            return iss::Err;
         this->reg.instret = static_cast<uint64_t>(val);
     } else {
         if ((addr&0xff) == (minstret&0xff)) {
@@ -943,7 +761,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
-    val = FEAT & features_e::FEAT_CLIC? csr[addr] : csr[addr] & ~2;
+    val = csr[mtvec] & ~2;
     return iss::Ok;
 }
 
@@ -958,28 +776,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
     return iss::Ok;
 }
 
-template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cause(unsigned addr, reg_t &val) {
-    if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
-        val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
-        val |= clic_mprev_lvl<<16;
-        val |= state.mstatus.MPIE<<27;
-        val |= state.mstatus.MPP<<28;
-    } else
-        val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
-    return iss::Ok;
-}
-
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
-    if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
+    csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
-        auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
-        csr[addr] = (val & mask) | (csr[addr] & ~mask);
-        clic_mprev_lvl = ((val>>16)&0xff) | (1<<(8-cfg. clic_int_ctl_bits)) - 1;
-        state.mstatus.MPIE=(val>>27)&0x1;
-        state.mstatus.MPP=(val>>28)&0x3;
-    } else {
-        auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
-        csr[addr] = (val & mask) | (csr[addr] & ~mask);
-    }
     return iss::Ok;
 }
 
@@ -1007,6 +805,14 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
     return iss::Ok;
 }
 
+template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
+    auto mask = get_irq_mask();
+    mask &= 0xf; // only xSIP is writable
+    csr[mip] = (csr[mip] & ~mask) | (val & mask);
+    check_interrupt();
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_epc(unsigned addr, reg_t val) {
     csr[addr] = val & get_pc_mask();
     return iss::Ok;
@@ -1051,27 +857,22 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
     return iss::Ok;
 }
 
-template<typename BASE, features_e FEAT>
-iss::status riscv_hart_m_p<BASE, FEAT>::read_intstatus(unsigned addr, reg_t& val) {
-	val = (clic_mact_lvl&0xff) <<24;
-    return iss::Ok;
-}
-
-template<typename BASE, features_e FEAT>
-iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
-    csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1;
-    return iss::Ok;
-}
-
-template<typename BASE, features_e FEAT>
-iss::status riscv_hart_m_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
-    csr[addr]= val & ~0x3fULL;
-    return iss::Ok;
-}
-
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
+    if(mem_read_cb) return mem_read_cb(paddr, length, data);
     switch (paddr.val) {
+    case 0x0200BFF8: { // CLINT base, mtime reg
+        if (sizeof(reg_t) < length) return iss::Err;
+        reg_t time_val;
+        this->read_csr(time, time_val);
+        std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
+    } break;
+    case 0x10008000: {
+        const mem_type::page_type &p = mem(paddr.val / mem.page_size);
+        uint64_t offs = paddr.val & mem.page_addr_mask;
+        std::copy(p.data() + offs, p.data() + offs + length, data);
+        if (this->reg.icount > 30000) data[3] |= 0x80;
+    } break;
     default: {
         for(auto offs=0U; offs<length; ++offs) {
             *(data + offs)=mem[(paddr.val+offs)%mem.size()];
@@ -1083,14 +884,32 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned len
 
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
+    if(mem_write_cb) return mem_write_cb(paddr, length, data);
     switch (paddr.val) {
-    case 0xFFFF0000: // UART0 base, TXFIFO reg
+    case 0x10013000: // UART0 base, TXFIFO reg
+    case 0x10023000: // UART1 base, TXFIFO reg
+        uart_buf << (char)data[0];
         if (((char)data[0]) == '\n' || data[0] == 0) {
-            LOG(INFO)<<"UART"<<((paddr.val>>12)&0x3)<<" send '"<<uart_buf.str()<<"'";
+            // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
+            // '"<<uart_buf.str()<<"'";
+            std::cout << uart_buf.str();
             uart_buf.str("");
-        } else if(((char)data[0]) != '\r')
+        }
-            uart_buf << (char)data[0];
         break;
+    case 0x10008000: { // HFROSC base, hfrosccfg reg
+        mem_type::page_type &p = mem(paddr.val / mem.page_size);
+        size_t offs = paddr.val & mem.page_addr_mask;
+        std::copy(data, data + length, p.data() + offs);
+        uint8_t &x = *(p.data() + offs + 3);
+        if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
+    } break;
+    case 0x10008008: { // HFROSC base, pllcfg reg
+        mem_type::page_type &p = mem(paddr.val / mem.page_size);
+        size_t offs = paddr.val & mem.page_addr_mask;
+        std::copy(data, data + length, p.data() + offs);
+        uint8_t &x = *(p.data() + offs + 3);
+        x |= 0x80; // set pll lock upon writing
+    } break;
     default: {
         mem_type::page_type &p = mem(paddr.val / mem.page_size);
         std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
@@ -1141,45 +960,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
     return iss::Ok;
 }
 
-template<typename BASE, features_e FEAT>
-iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length, uint8_t *const data) {
-    if(addr==cfg.clic_base) { // cliccfg
-        *data=clic_cfg_reg;
-        for(auto i=1; i<length; ++i) *(data+i)=0;
-    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
-        auto offset = ((addr&0x7fff)-0x40)/4;
-        read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
-    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
-        auto offset = ((addr&0x7fff)-0x1000)/4;
-        read_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
-    } else {
-        for(auto i = 0U; i<length; ++i) *(data+i)=0;
-    }
-    return iss::Ok;
-}
-
-template<typename BASE, features_e FEAT>
-iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
-    if(addr==cfg.clic_base) { // cliccfg
-        clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
-    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
-        auto offset = ((addr&0x7fff)-0x40)/4;
-        write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
-    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
-        auto offset = ((addr&0x7fff)-0x1000)/4;
-        write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
-        clic_int_reg[offset].raw &= 0xf0c70101; // clicIntCtlBits->0xf0, clicintattr->0xc7, clicintie->0x1, clicintip->0x1
-    }
-    return iss::Ok;
-}
-
 template <typename BASE, features_e FEAT> inline void riscv_hart_m_p<BASE, FEAT>::reset(uint64_t address) {
     BASE::reset(address);
     state.mstatus = hart_state_type::mstatus_reset_val;
 }
 
 template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check_interrupt() {
-    //TODO: Implement CLIC functionality
     //auto ideleg = csr[mideleg];
     // Multiple simultaneous interrupts and traps at the same privilege level are
     // handled in the following decreasing priority order:
@@ -1187,8 +973,8 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
     // any synchronous traps.
     auto ena_irq = csr[mip] & csr[mie];
 
-    bool mstatus_mie = state.mstatus.MIE;
+    bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.PRIV < PRIV_M || mstatus_mie;
+    auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
     auto enabled_interrupts = m_enabled ? ena_irq : 0;
 
     if (enabled_interrupts != 0) {
@@ -1204,10 +990,9 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
 template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
     // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
     // calculate and write mcause val
-    auto const trap_id = bit_sub<0, 16>(flags);
+    auto trap_id = bit_sub<0, 16>(flags);
     auto cause = bit_sub<16, 15>(flags);
     // calculate effective privilege level
-    unsigned new_priv = PRIV_M;
     if (trap_id == 0) { // exception
         if (cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
         // store ret addr in xepc register
@@ -1224,16 +1009,13 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
             csr[mtval] = static_cast<reg_t>(addr);
             break;
         case 2:
-            csr[mtval] = (!has_compressed() || (instr & 0x3)==3)?instr:instr&0xffff;
+            csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
             break;
         case 3:
-            if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) {
+            //TODO: implement debug mode behavior
-                this->reg.DPC = addr;
+            // csr[dpc] = addr;
-                csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
+            // csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
-                new_priv = this->reg.PRIV | PRIV_D;
+            csr[mtval] = 0;
-            } else {
-                csr[mtval] = addr;
-            }
             break;
         case 4:
         case 6:
@@ -1247,7 +1029,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
         csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
         this->reg.pending_trap = 0;
     }
-    csr[mcause] = (trap_id << (traits<BASE>::XLEN-1)) + cause;
+    csr[mcause] = (trap_id << 31) + cause;
     // update mstatus
     // xPP field of mstatus is written with the active privilege mode at the time
     // of the trap; the x PIE field of mstatus
@@ -1260,21 +1042,13 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
     state.mstatus.MIE = false;
 
     // get trap vector
-    auto xtvec = csr[mtvec];
+    auto ivec = csr[mtvec];
-    // calculate adds// set NEXT_PC to trap addressess to jump to based on MODE
+    // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
-    if((FEAT & features_e::FEAT_CLIC) && trap_id!=0 && (xtvec & 0x3UL)==3UL) {
+    // bits in mtvec
-        reg_t data;
+    this->reg.NEXT_PC = ivec & ~0x3UL;
-        auto ret = read(address_type::LOGICAL, access_type::READ, 0, csr[mtvt], sizeof(reg_t), reinterpret_cast<uint8_t*>(&data));
+    if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-        if(ret == iss::Err)
-            return this->reg.PC;
-        this->reg.NEXT_PC = data;
-    } else {
-        // bits in mtvec
-        this->reg.NEXT_PC = xtvec & ~0x3UL;
-        if ((xtvec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
-    }
     // reset trap state
-    this->reg.PRIV = new_priv;
+    this->reg.PRIV = PRIV_M;
     this->reg.trap_state = 0;
     std::array<char, 32> buffer;
 #if defined(_MSC_VER)
@@ -1296,7 +1070,6 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::l
     this->reg.NEXT_PC = csr[mepc] & get_pc_mask();
     CLOG(INFO, disass) << "Executing xRET";
     check_interrupt();
-    this->reg.trap_state = this->reg.pending_trap;
     return this->reg.NEXT_PC;
 }
 

incl/iss/arch/riscv_hart_msu_vp.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
+ * Copyright (C) 2017, 2018, 2021 MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -293,32 +293,37 @@ public:
 
     std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
 
-    phys_addr_t virt2phys(const iss::addr_t &addr) override;
+    virtual phys_addr_t virt2phys(const iss::addr_t &addr) override;
 
     iss::status read(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, uint8_t *const data) override;
     iss::status write(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
-    uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
+    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
-    uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
+    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    uint64_t leave_trap(uint64_t flags) override;
+    virtual uint64_t leave_trap(uint64_t flags) override;
     void wait_until(uint64_t flags) override;
 
     void disass_output(uint64_t pc, const std::string instr) override {
         CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]",
-                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount + cycle_offset);
+                pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.ccount);
     };
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
 
+    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
+        mem_read_cb = memReadCb;
+    }
+
+    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
+        mem_write_cb = memWriteCb;
+    }
+
     void set_csr(unsigned addr, reg_t val){
         csr[addr & csr.page_addr_mask] = val;
     }
 
-    void set_irq_num(unsigned i) {
-        mcause_max_irq=1<<util::ilog2(i);
-    }
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
@@ -331,21 +336,11 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        uint64_t get_pc() override { return arch.reg.PC; };
+        virtual uint64_t get_pc() { return arch.get_pc(); };
 
-        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
+        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
 
-        uint64_t get_instr_word() override { return arch.reg.instruction; }
+        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
-
-        uint64_t get_instr_count() override { return arch.reg.icount; }
-
-        uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
-
-        uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
-
-        void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
-
-        bool is_branch_taken() override { return arch.reg.last_branch; };
 
         riscv_hart_msu_vp<BASE> &arch;
     };
@@ -384,17 +379,16 @@ protected:
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
     std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
 
-    std::vector<uint8_t> tcm;
+private:
-
+    iss::status read_reg(unsigned addr, reg_t &val);
-    iss::status read_csr_reg(unsigned addr, reg_t &val);
+    iss::status write_reg(unsigned addr, reg_t val);
-    iss::status write_csr_reg(unsigned addr, reg_t val);
     iss::status read_null(unsigned addr, reg_t &val);
     iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
     iss::status read_cycle(unsigned addr, reg_t &val);
     iss::status write_cycle(unsigned addr, reg_t val);
     iss::status read_instret(unsigned addr, reg_t &val);
     iss::status write_instret(unsigned addr, reg_t val);
-    iss::status read_tvec(unsigned addr, reg_t &val);
+    iss::status read_mtvec(unsigned addr, reg_t &val);
     iss::status read_time(unsigned addr, reg_t &val);
     iss::status read_status(unsigned addr, reg_t &val);
     iss::status write_status(unsigned addr, reg_t val);
@@ -402,8 +396,7 @@ protected:
     iss::status read_ie(unsigned addr, reg_t &val);
     iss::status write_ie(unsigned addr, reg_t val);
     iss::status read_ip(unsigned addr, reg_t &val);
-    iss::status write_ideleg(unsigned addr, reg_t val);
+    iss::status write_ip(unsigned addr, reg_t val);
-    iss::status write_edeleg(unsigned addr, reg_t val);
     iss::status read_hartid(unsigned addr, reg_t &val);
     iss::status write_epc(unsigned addr, reg_t val);
     iss::status read_satp(unsigned addr, reg_t &val);
@@ -411,18 +404,11 @@ protected:
     iss::status read_fcsr(unsigned addr, reg_t &val);
     iss::status write_fcsr(unsigned addr, reg_t val);
 
-    virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;};
-    virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;};
-
-    void register_custom_csr_rd(unsigned addr){
-        csr_rd_cb[addr] = &this_class::read_custom_csr_reg;
-    }
-    void register_custom_csr_wr(unsigned addr){
-        csr_wr_cb[addr] = &this_class::write_custom_csr_reg;
-    }
-
     reg_t mhartid_reg{0x0};
+    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
+    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
 
+protected:
     void check_interrupt();
 };
 
@@ -439,22 +425,22 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
     uart_buf.str("");
     for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_reg;
     }
     for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_reg;
     }
     for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
-        csr_wr_cb[addr] = &this_class::write_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_reg;
     }
     for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
     }
     for (unsigned addr = cycleh; addr <= hpmcounter31h; ++addr){
         csr_rd_cb[addr] = &this_class::read_null;
-        //csr_wr_cb[addr] = &this_class::write_csr_reg;
+        //csr_wr_cb[addr] = &this_class::write_reg;
     }
     // common regs
     const std::array<unsigned, 22> addrs{{
@@ -464,25 +450,25 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
         uepc, utvec, uscratch, ucause, utval, uscratch
     }};
     for(auto addr: addrs) {
-        csr_rd_cb[addr] = &this_class::read_csr_reg;
+        csr_rd_cb[addr] = &this_class::read_reg;
-        csr_wr_cb[addr] = &this_class::write_csr_reg;
+        csr_wr_cb[addr] = &this_class::write_reg;
     }
     // special handling & overrides
     csr_rd_cb[time] = &this_class::read_time;
-    if(traits<BASE>::XLEN==32)  csr_rd_cb[timeh] = &this_class::read_time;
+    csr_rd_cb[timeh] = &this_class::read_time;
     csr_rd_cb[cycle] = &this_class::read_cycle;
-    if(traits<BASE>::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle;
+    csr_rd_cb[cycleh] = &this_class::read_cycle;
     csr_rd_cb[instret] = &this_class::read_instret;
-    if(traits<BASE>::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret;
+    csr_rd_cb[instreth] = &this_class::read_instret;
 
     csr_rd_cb[mcycle] = &this_class::read_cycle;
     csr_wr_cb[mcycle] = &this_class::write_cycle;
-    if(traits<BASE>::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle;
+    csr_rd_cb[mcycleh] = &this_class::read_cycle;
-    if(traits<BASE>::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle;
+    csr_wr_cb[mcycleh] = &this_class::write_cycle;
     csr_rd_cb[minstret] = &this_class::read_instret;
     csr_wr_cb[minstret] = &this_class::write_instret;
-    if(traits<BASE>::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret;
+    csr_rd_cb[minstreth] = &this_class::read_instret;
-    if(traits<BASE>::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret;
+    csr_wr_cb[minstreth] = &this_class::write_instret;
     csr_rd_cb[mstatus] = &this_class::read_status;
     csr_wr_cb[mstatus] = &this_class::write_status;
     csr_wr_cb[mcause] = &this_class::write_cause;
@@ -499,11 +485,11 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
     csr_wr_cb[sepc] = &this_class::write_epc;
     csr_wr_cb[uepc] = &this_class::write_epc;
     csr_rd_cb[mip] = &this_class::read_ip;
-    csr_wr_cb[mip] = &this_class::write_null;
+    csr_wr_cb[mip] = &this_class::write_ip;
     csr_rd_cb[sip] = &this_class::read_ip;
-    csr_wr_cb[sip] = &this_class::write_null;
+    csr_wr_cb[sip] = &this_class::write_ip;
     csr_rd_cb[uip] = &this_class::read_ip;
-    csr_wr_cb[uip] = &this_class::write_null;
+    csr_wr_cb[uip] = &this_class::write_ip;
     csr_rd_cb[mie] = &this_class::read_ie;
     csr_wr_cb[mie] = &this_class::write_ie;
     csr_rd_cb[sie] = &this_class::read_ie;
@@ -532,10 +518,10 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
     if (fp) {
         std::array<char, 5> buf;
         auto n = fread(buf.data(), 1, 4, fp);
-        fclose(fp);
         if (n != 4) throw std::runtime_error("input file has insufficient size");
         buf[4] = 0;
         if (strcmp(buf.data() + 1, "ELF") == 0) {
+            fclose(fp);
             // Create elfio reader
             ELFIO::elfio reader;
             // Load ELF data
@@ -554,7 +540,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
                             traits<BASE>::MEM, pseg->get_physical_address(),
                             fsize, reinterpret_cast<const uint8_t *const>(seg_data));
                     if (res != iss::Ok)
-                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
+                        LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
                                    << pseg->get_physical_address();
                 }
             }
@@ -588,9 +574,9 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
+        throw std::runtime_error("memory load file is not a valid elf file");
     }
-    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    throw std::runtime_error("memory load file not found");
 }
 
 template <typename BASE>
@@ -608,19 +594,13 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
     try {
         switch (space) {
         case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access)? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
+            if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
-            if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
                 if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
                 this->reg.trap_state = (1 << 31); // issue trap 0
                 return iss::Err;
             }
             try {
-                if(!is_debug(access)  && (addr&(alignment-1))){
-                    this->reg.trap_state = 1<<31 | 4<<16;
-                    fault_data=addr;
-                    return iss::Err;
-                }
                 if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
                     vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp);
                     if (vm.levels != 0) { // VM is active
@@ -678,7 +658,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        this->reg.trap_state = (1 << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }
@@ -735,12 +715,12 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                         write_mem(phys_addr_t{access, space, addr}, length, data):
                         write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
                 if (unlikely(res != iss::Ok)) {
-                    this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
+                    this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->reg.trap_state = (1UL << 31) | ta.id;
+                this->reg.trap_state = (1 << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -805,7 +785,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->reg.trap_state = (1UL << 31) | ta.id;
+        this->reg.trap_state = (1 << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }
@@ -850,7 +830,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_reg(unsigned
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
     auto cycle_val = this->reg.icount + cycle_offset;
     if (addr == mcycle) {
         val = static_cast<reg_t>(cycle_val);
@@ -861,8 +841,10 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigne
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cycle(unsigned addr, reg_t val) {
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) {
     if (sizeof(typename traits<BASE>::reg_t) != 4) {
+        if (addr == mcycleh)
+            return iss::Err;
         mcycle_csr = static_cast<uint64_t>(val);
     } else {
         if (addr == mcycle) {
@@ -875,17 +857,20 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_cycle(unsign
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_instret(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) {
     if ((addr&0xff) == (minstret&0xff)) {
         val = static_cast<reg_t>(this->reg.instret);
     } else if ((addr&0xff) == (minstreth&0xff)) {
+        if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
         val = static_cast<reg_t>(this->reg.instret >> 32);
     }
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_instret(unsigned addr, reg_t val) {
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) {
     if (sizeof(typename traits<BASE>::reg_t) != 4) {
+        if ((addr&0xff) == (minstreth&0xff))
+            return iss::Err;
         this->reg.instret = static_cast<uint64_t>(val);
     } else {
         if ((addr&0xff) == (minstret&0xff)) {
@@ -898,7 +883,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_instret(unsi
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
     uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
     if (addr == time) {
         val = static_cast<reg_t>(time_val);
@@ -909,7 +894,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned
     return iss::Ok;
 }
 
-template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_tvec(unsigned addr, reg_t &val) {
+template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) {
     val = csr[addr] & ~2;
     return iss::Ok;
 }
@@ -960,6 +945,15 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ip(unsigned a
     return iss::Ok;
 }
 
+template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ip(unsigned addr, reg_t val) {
+    auto req_priv_lvl = (addr >> 8) & 0x3;
+    auto mask = get_irq_mask(req_priv_lvl);
+    mask &= ~(1 << 7); // MTIP is read only
+    csr[mip] = (csr[mip] & ~mask) | (val & mask);
+    check_interrupt();
+    return iss::Ok;
+}
+
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_epc(unsigned addr, reg_t val) {
     csr[addr] = val & get_pc_mask();
     return iss::Ok;
@@ -1023,7 +1017,20 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_fcsr(unsigne
 
 template <typename BASE>
 iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
+    if(mem_read_cb) return mem_read_cb(paddr, length, data);
     switch (paddr.val) {
+    case 0x0200BFF8: { // CLINT base, mtime reg
+        if (sizeof(reg_t) < length) return iss::Err;
+        reg_t time_val;
+        this->read_csr(time, time_val);
+        std::copy((uint8_t *)&time_val, ((uint8_t *)&time_val) + length, data);
+    } break;
+    case 0x10008000: {
+        const mem_type::page_type &p = mem(paddr.val / mem.page_size);
+        uint64_t offs = paddr.val & mem.page_addr_mask;
+        std::copy(p.data() + offs, p.data() + offs + length, data);
+        if (this->reg.icount > 30000) data[3] |= 0x80;
+    } break;
     default: {
         for(auto offs=0U; offs<length; ++offs) {
             *(data + offs)=mem[(paddr.val+offs)%mem.size()];
@@ -1035,14 +1042,32 @@ iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length
 
 template <typename BASE>
 iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
+    if(mem_write_cb) return mem_write_cb(paddr, length, data);
     switch (paddr.val) {
-    case 0xFFFF0000: // UART0 base, TXFIFO reg
+    case 0x10013000: // UART0 base, TXFIFO reg
+    case 0x10023000: // UART1 base, TXFIFO reg
+        uart_buf << (char)data[0];
         if (((char)data[0]) == '\n' || data[0] == 0) {
-            LOG(INFO)<<"UART"<<((paddr.val>>12)&0x3)<<" send '"<<uart_buf.str()<<"'";
+            // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
+            // '"<<uart_buf.str()<<"'";
+            std::cout << uart_buf.str();
             uart_buf.str("");
-        } else if(((char)data[0]) != '\r')
+        }
-            uart_buf << (char)data[0];
         break;
+    case 0x10008000: { // HFROSC base, hfrosccfg reg
+        mem_type::page_type &p = mem(paddr.val / mem.page_size);
+        size_t offs = paddr.val & mem.page_addr_mask;
+        std::copy(data, data + length, p.data() + offs);
+        uint8_t &x = *(p.data() + offs + 3);
+        if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
+    } break;
+    case 0x10008008: { // HFROSC base, pllcfg reg
+        mem_type::page_type &p = mem(paddr.val / mem.page_size);
+        size_t offs = paddr.val & mem.page_addr_mask;
+        std::copy(data, data + length, p.data() + offs);
+        uint8_t &x = *(p.data() + offs + 3);
+        x |= 0x80; // set pll lock upon writing
+    } break;
     default: {
         mem_type::page_type &p = mem(paddr.val / mem.page_size);
         std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
@@ -1234,7 +1259,6 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
     auto cur_priv = this->reg.PRIV;
     // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
     // calculate and write mcause val
-    if(flags==std::numeric_limits<uint64_t>::max()) flags=this->reg.trap_state;
     auto trap_id = bit_sub<0, 16>(flags);
     auto cause = bit_sub<16, 15>(flags);
     if (trap_id == 0 && cause == 11) cause = 0x8 + cur_priv; // adjust environment call cause
@@ -1252,27 +1276,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
          * access, or page-fault exception occurs, mtval is written with the
          * faulting effective address.
          */
-        switch(cause){
+        csr[utval | (new_priv << 8)] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data;
-        case 0:
-            csr[utval | (new_priv << 8)] = static_cast<reg_t>(addr);
-            break;
-        case 2:
-            csr[utval | (new_priv << 8)] = (instr & 0x3)==3?instr:instr&0xffff;
-            break;
-        case 3:
-            //TODO: implement debug mode behavior
-            // csr[dpc] = addr;
-            // csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
-            csr[utval | (new_priv << 8)] = addr;
-            break;
-        case 4:
-        case 6:
-        case 7:
-            csr[utval | (new_priv << 8)] = fault_data;
-            break;
-        default:
-            csr[utval | (new_priv << 8)] = 0;
-        }
         fault_data = 0;
     } else {
         if (cur_priv != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0)

incl/iss/arch/tgc_c.h

@@ -53,12 +53,17 @@ template <> struct traits<tgc_c> {
     static constexpr std::array<const char*, 36> reg_aliases{
         {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
 
-    enum constants {MISA_VAL=1073746180, MARCHID_VAL=2147483651, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
+    enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 
     enum reg_e {
-        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH
+        X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS,
+        TRAP_STATE=NUM_REGS,
+        PENDING_TRAP,
+        ICOUNT,
+        CYCLE,
+        INSTRET
     };
 
     using reg_t = uint32_t;
@@ -71,19 +76,19 @@ template <> struct traits<tgc_c> {
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
 
-    static constexpr std::array<const uint32_t, 43> reg_bit_widths{
+    static constexpr std::array<const uint32_t, 41> reg_bit_widths{
-        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}};
+        {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64}};
 
-    static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
+    static constexpr std::array<const uint32_t, 41> reg_byte_offsets{
-        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
+        {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165}};
 
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, FENCE, RES, CSR };
+    enum mem_type_e { MEM, CSR, FENCE, RES };
     
-    enum class opcode_e {
+    enum class opcode_e : unsigned short {
         LUI = 0,
         AUIPC = 1,
         JAL = 2,
@@ -124,53 +129,56 @@ template <> struct traits<tgc_c> {
         FENCE = 37,
         ECALL = 38,
         EBREAK = 39,
-        MRET = 40,
+        URET = 40,
-        WFI = 41,
+        SRET = 41,
-        CSRRW = 42,
+        MRET = 42,
-        CSRRS = 43,
+        WFI = 43,
-        CSRRC = 44,
+        DRET = 44,
-        CSRRWI = 45,
+        CSRRW = 45,
-        CSRRSI = 46,
+        CSRRS = 46,
-        CSRRCI = 47,
+        CSRRC = 47,
-        FENCE_I = 48,
+        CSRRWI = 48,
-        MUL = 49,
+        CSRRSI = 49,
-        MULH = 50,
+        CSRRCI = 50,
-        MULHSU = 51,
+        FENCE_I = 51,
-        MULHU = 52,
+        MUL = 52,
-        DIV = 53,
+        MULH = 53,
-        DIVU = 54,
+        MULHSU = 54,
-        REM = 55,
+        MULHU = 55,
-        REMU = 56,
+        DIV = 56,
-        CADDI4SPN = 57,
+        DIVU = 57,
-        CLW = 58,
+        REM = 58,
-        CSW = 59,
+        REMU = 59,
-        CADDI = 60,
+        CADDI4SPN = 60,
-        CNOP = 61,
+        CLW = 61,
-        CJAL = 62,
+        CSW = 62,
-        CLI = 63,
+        CADDI = 63,
-        CLUI = 64,
+        CNOP = 64,
-        CADDI16SP = 65,
+        CJAL = 65,
-        __reserved_clui = 66,
+        CLI = 66,
-        CSRLI = 67,
+        CLUI = 67,
-        CSRAI = 68,
+        CADDI16SP = 68,
-        CANDI = 69,
+        __reserved_clui = 69,
-        CSUB = 70,
+        CSRLI = 70,
-        CXOR = 71,
+        CSRAI = 71,
-        COR = 72,
+        CANDI = 72,
-        CAND = 73,
+        CSUB = 73,
-        CJ = 74,
+        CXOR = 74,
-        CBEQZ = 75,
+        COR = 75,
-        CBNEZ = 76,
+        CAND = 76,
-        CSLLI = 77,
+        CJ = 77,
-        CLWSP = 78,
+        CBEQZ = 78,
-        CMV = 79,
+        CBNEZ = 79,
-        CJR = 80,
+        CSLLI = 80,
-        __reserved_cmv = 81,
+        CLWSP = 81,
-        CADD = 82,
+        CMV = 82,
-        CJALR = 83,
+        CJR = 83,
-        CEBREAK = 84,
+        __reserved_cmv = 84,
-        CSWSP = 85,
+        CADD = 85,
-        DII = 86,
+        CJALR = 86,
+        CEBREAK = 87,
+        CSWSP = 88,
+        DII = 89,
         MAX_OPCODE
     };
 };
@@ -209,7 +217,7 @@ struct tgc_c: public arch_if {
 
     inline uint32_t get_last_branch() { return reg.last_branch; }
 
-
+protected:
 #pragma pack(push, 1)
     struct TGC_C_regs { 
         uint32_t X0 = 0; 
@@ -252,8 +260,7 @@ struct tgc_c: public arch_if {
         uint64_t icount = 0;
         uint64_t cycle = 0;
         uint64_t instret = 0;
-        uint32_t instruction = 0;
+        uint32_t last_branch;
-        uint32_t last_branch = 0;
     } reg;
 #pragma pack(pop)
     std::array<address_type, 4> addr_mode;

incl/iss/debugger/riscv_target_adapter.h

@@ -85,7 +85,7 @@ public:
      corresponding bytes in avail_buf are 0, otherwise
      avail buf is 1 */
     status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
-            std::vector<uint8_t> &avail_buf) override;
+                                std::vector<uint8_t> &avail_buf) override;
 
     /* Write one register. buf is 4-byte aligned and it is in target byte
      order */
@@ -104,7 +104,7 @@ public:
     status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
 
     status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
-            size_t &num, bool &done) override;
+                             size_t &num, bool &done) override;
 
     status current_thread_query(rp_thread_ref &thread) override;
 
@@ -120,12 +120,12 @@ public:
 
     status packetsize_query(std::string &out_buf) override;
 
-    status add_break(break_type type, uint64_t addr, unsigned int length) override;
+    status add_break(int type, uint64_t addr, unsigned int length) override;
 
-    status remove_break(break_type type, uint64_t addr, unsigned int length) override;
+    status remove_break(int type, uint64_t addr, unsigned int length) override;
 
     status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
-            std::function<void(unsigned)> stop_callback) override;
+                            std::function<void(unsigned)> stop_callback) override;
 
     status target_xml_query(std::string &out_buf) override;
 
@@ -159,8 +159,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
  */
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
-        std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
+                                                     std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
-        bool &done) {
+                                                     bool &done) {
     if (first == 0) {
         result.clear();
         result.push_back(thread_idx);
@@ -193,20 +193,20 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
         }
     }
     // work around fill with F type registers
-    //    if (arch::traits<ARCH>::NUM_REGS < 65) {
+//    if (arch::traits<ARCH>::NUM_REGS < 65) {
-    //        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
+//        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
-    //        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
+//        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
-    //            for (size_t j = 0; j < reg_width; ++j) {
+//            for (size_t j = 0; j < reg_width; ++j) {
-    //                data.push_back(0x0);
+//                data.push_back(0x0);
-    //                avail.push_back(0x00);
+//                avail.push_back(0x00);
-    //            }
+//            }
-    //            // if(arch::traits<ARCH>::XLEN < 64)
+//            // if(arch::traits<ARCH>::XLEN < 64)
-    //            //     for(unsigned j=0; j<4; ++j){
+//            //     for(unsigned j=0; j<4; ++j){
-    //            //         data.push_back(0x0);
+//            //         data.push_back(0x0);
-    //            //         avail.push_back(0x00);
+//            //         avail.push_back(0x00);
-    //            //     }
+//            //     }
-    //        }
+//        }
-    //    }
+//    }
     return Ok;
 }
 
@@ -214,33 +214,19 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
     auto start_reg=arch::traits<ARCH>::X0;
     auto *reg_base = core->get_regs_base_ptr();
     auto iter = data.data();
-    bool e_ext = arch::traits<ARCH>::PC<32;
     for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
-        if(e_ext && reg_no>15){
+        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
-            if(reg_no==32){
+        auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
-                auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
+        std::copy(iter, iter + reg_width, reg_base);
-                auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
+        iter += 4;
-                std::copy(iter, iter + reg_width, reg_base);
+        reg_base += offset;
-            } else {
-                const uint64_t zero_val=0;
-                auto reg_width = arch::traits<ARCH>::reg_bit_widths[15] / 8;
-                auto iter = (uint8_t*)&zero_val;
-                std::copy(iter, iter + reg_width, reg_base);
-            }
-        } else {
-            auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
-            auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
-            std::copy(iter, iter + reg_width, reg_base);
-            iter += 4;
-            reg_base += offset;
-        }
     }
     return Ok;
 }
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
-        std::vector<uint8_t> &avail) {
+                                                        std::vector<uint8_t> &avail) {
     if (reg_no < 65) {
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
@@ -331,48 +317,34 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
+template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
-    switch(type) {
+    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
-    default:
+    auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
-        return Err;
+    target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
-    case SW_EXEC:
+    LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
-    case HW_EXEC: {
+               << saddr.val << std::dec;
-        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-        auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
+    return Ok;
-        target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
+}
-        LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
+
-                << saddr.val << std::dec;
+template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
+    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+    unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
+    if (handle) {
+        LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
+                   << std::dec;
+        // TODO: check length of addr range
+        target_adapter_base::bp_lut.removeEntry(handle);
         LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
-    }
+    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-}
+    return Err;
-
-template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
-    switch(type) {
-    default:
-        return Err;
-    case SW_EXEC:
-    case HW_EXEC: {
-        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
-        unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
-        if (handle) {
-            LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
-                    << std::dec;
-            // TODO: check length of addr range
-            target_adapter_base::bp_lut.removeEntry(handle);
-            LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-            return Ok;
-        }
-        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-        return Err;
-    }
-    }
 }
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
-        std::function<void(unsigned)> stop_callback) {
+                                                    std::function<void(unsigned)> stop_callback) {
     auto *reg_base = core->get_regs_base_ptr();
     auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
     auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
@@ -383,42 +355,42 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
     const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
-        "<target><architecture>riscv:rv32</architecture>"
+                          "<target><architecture>riscv:rv32</architecture>"
-        //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
+                          //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
-        //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
-        //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
+                          //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
-        //"  </feature>\n"
+                          //"  </feature>\n"
-        "</target>"};
+                          "</target>"};
     out_buf = res;
     return Ok;
 }

incl/iss/factory.h

@@ -34,12 +34,6 @@
 #define _ISS_FACTORY_H_
 
 #include <iss/iss.h>
-#include <memory>
-#include <unordered_map>
-#include <functional>
-#include <string>
-#include <algorithm>
-#include <vector>
 
 namespace iss {
 
@@ -56,55 +50,13 @@ std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_
     if(backend == "llvm")
         return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};
 #endif
-#ifdef WITH_TCC
+#ifdef WITH_LLVM
     if(backend == "tcc")
         return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
 #endif
     return {nullptr, nullptr};
 }
 
-
-class core_factory {
-    using cpu_ptr = std::unique_ptr<iss::arch_if>;
-    using vm_ptr= std::unique_ptr<iss::vm_if>;
-    using base_t = std::tuple<cpu_ptr, vm_ptr>;
-    using create_fn = std::function<base_t(unsigned, void*) >;
-    using registry_t = std::unordered_map<std::string, create_fn> ;
-
-    registry_t registry;
-
-    core_factory() = default;
-    core_factory(const core_factory &) = delete;
-    core_factory & operator=(const core_factory &) = delete;
-
-public:
-    static core_factory & instance() { static core_factory bf; return bf; }
-
-    bool register_creator(const std::string &, create_fn const&);
-
-    base_t create(const std::string &, unsigned gdb_port=0, void* init_data=nullptr) const;
-
-    std::vector<std::string> get_names() {
-        std::vector<std::string> keys{registry.size()};
-        std::transform(std::begin(registry), std::end(registry), std::begin(keys), [](std::pair<std::string, create_fn> const& p){
-            return p.first;
-        });
-        return keys;
-    }
-};
-
-inline bool core_factory::register_creator(const std::string & className, create_fn const& fn) {
-    registry[className] = fn;
-    return true;
-}
-
-inline core_factory::base_t core_factory::create(const std::string &className, unsigned gdb_port, void* data) const {
-    registry_t::const_iterator regEntry = registry.find(className);
-    if (regEntry != registry.end())
-        return regEntry->second(gdb_port, data);
-    return {nullptr, nullptr};
-}
-
 }
 
 #endif /* _ISS_FACTORY_H_ */

incl/iss/plugin/cycle_estimate.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
+ * Copyright (C) 2017, 2018, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -37,25 +37,23 @@
 
 #include "iss/instrumentation_if.h"
 #include "iss/vm_plugin.h"
+#include <json/json.h>
 #include <string>
 #include <unordered_map>
-#include <vector>
 
 namespace iss {
 
 namespace plugin {
 
-class cycle_estimate: public vm_plugin {
+class cycle_estimate: public iss::vm_plugin {
 	BEGIN_BF_DECL(instr_desc, uint32_t)
 		BF_FIELD(taken, 24, 8)
 		BF_FIELD(not_taken, 16, 8)
-        BF_FIELD(is_branch, 8, 8)
+		BF_FIELD(size, 0, 16)
-        BF_FIELD(size, 0, 8)
+		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
-		instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
 			this->size=size;
 			this->taken=taken;
 			this->not_taken=not_taken;
-			this->is_branch=branch;
 		}
 	END_BF_DECL();
 
@@ -66,7 +64,7 @@ public:
 
     cycle_estimate(const cycle_estimate &&) = delete;
 
-    cycle_estimate(std::string const& config_file_name);
+    cycle_estimate(std::string config_file_name);
 
     virtual ~cycle_estimate();
 
@@ -78,10 +76,10 @@ public:
 
     sync_type get_sync() override { return POST_SYNC; };
 
-    void callback(instr_info_t instr_info) override;
+    void callback(instr_info_t instr_info, exec_info const&) override;
 
 private:
-    iss::instrumentation_if *instr_if;
+    iss::instrumentation_if *arch_instr;
     std::vector<instr_desc> delays;
     struct pair_hash {
         size_t operator()(const std::pair<uint64_t, uint64_t> &p) const {
@@ -90,7 +88,7 @@ private:
         }
     };
     std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
-    std::string config_file_name;
+    Json::Value root;
 };
 }
 }

incl/iss/plugin/instruction_count.h

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
+ * Copyright (C) 2017, 2018, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -69,7 +69,7 @@ public:
 
     sync_type get_sync() override { return POST_SYNC; };
 
-    void callback(instr_info_t) override;
+    void callback(instr_info_t, exec_info const&) override;
 
 private:
     Json::Value root;

incl/sysc/core_complex.h

@@ -40,10 +40,8 @@
 #include <tlm/scc/scv/tlm_rec_initiator_socket.h>
 #ifdef CWR_SYSTEMC
 #include <scmlinc/scml_property.h>
-#define SOCKET_WIDTH 32
 #else
 #include <cci_configuration>
-#define SOCKET_WIDTH scc::LT
 #endif
 #include <tlm>
 #include <tlm_utils/tlm_quantumkeeper.h>
@@ -71,13 +69,11 @@ struct core_trace;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> ibus{"ibus"};
+    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
-
-    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<SOCKET_WIDTH>> dbus{"dbus"};
 
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
-    sc_core::sc_in<bool> ext_irq_i{"ext_irq_i"};
+    sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
 
     sc_core::sc_in<bool> timer_irq_i{"timer_irq_i"};
 
@@ -88,7 +84,7 @@ public:
 #ifndef CWR_SYSTEMC
 	sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 
-    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};
+    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
 
     cci::cci_param<std::string> elf_file{"elf_file", ""};
 
@@ -144,8 +140,6 @@ public:
     , gdb_server_port{"gdb_server_port", 0}
     , dump_ir{"dump_ir", false}
     , mhartid{"mhartid", 0}
-    , plugins{"plugins", ""}
-    , fetch_lut(tlm_dmi_ext())
     , read_lut(tlm_dmi_ext())
     , write_lut(tlm_dmi_ext())
     {
@@ -157,16 +151,13 @@ public:
     ~core_complex();
 
     inline void sync(uint64_t cycle) {
-        auto core_inc = curr_clk * (cycle - last_sync_cycle);
+        auto time = curr_clk * (cycle - last_sync_cycle);
-        auto incr = std::max(core_inc, std::max(ibus_inc, dbus_inc));
+        quantum_keeper.inc(time);
-        quantum_keeper.inc(incr);
         if (quantum_keeper.need_sync()) {
             wait(quantum_keeper.get_local_time());
             quantum_keeper.reset();
         }
         last_sync_cycle = cycle;
-        ibus_inc = sc_core::SC_ZERO_TIME;
-        dbus_inc = sc_core::SC_ZERO_TIME;
     }
 
     bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
@@ -190,15 +181,13 @@ protected:
     void rst_cb();
     void sw_irq_cb();
     void timer_irq_cb();
-    void ext_irq_cb();
+    void global_irq_cb();
-    void local_irq_cb();
     uint64_t last_sync_cycle = 0;
-    util::range_lut<tlm_dmi_ext> fetch_lut, read_lut, write_lut;
+    util::range_lut<tlm_dmi_ext> read_lut, write_lut;
     tlm_utils::tlm_quantumkeeper quantum_keeper;
     std::vector<uint8_t> write_buf;
     core_wrapper* cpu{nullptr};
     sc_core::sc_signal<sc_core::sc_time> curr_clk;
-    sc_core::sc_time ibus_inc, dbus_inc;
     core_trace* trc{nullptr};
     std::unique_ptr<scc::tick2time> t2t;
 private:
@@ -206,7 +195,7 @@ private:
     std::vector<iss::vm_plugin *> plugin_list;
 
 };
-} /* namespace tgfs */
+} /* namespace SiFive */
 } /* namespace sysc */
 
 #endif /* _SYSC_CORE_COMPLEX_H_ */

softfloat/CMakeLists.txt

@@ -8,7 +8,7 @@ project("sotfloat" VERSION 3.0.0)
 # Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
 set(VERSION "3e")
 
-#include(Common)
+include(Common)
 include(GNUInstallDirs)
 
 set(SPECIALIZATION RISCV)

src-gen/.gitignore

@@ -1,2 +0,0 @@
-/iss
-/vm

src/iss/arch/hwl.h

@@ -1,100 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2022 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       eyck@minres.com - initial implementation
- ******************************************************************************/
-
-#ifndef _RISCV_HART_M_P_HWL_H
-#define _RISCV_HART_M_P_HWL_H
-
-#include <iss/vm_types.h>
-
-namespace iss {
-namespace arch {
-
-template <typename BASE> class hwl : public BASE {
-public:
-    using base_class = BASE;
-    using this_class = hwl<BASE>;
-    using reg_t = typename BASE::reg_t;
-
-    hwl();
-    virtual ~hwl() = default;
-
-protected:
-    iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override;
-    iss::status write_custom_csr_reg(unsigned addr, reg_t val) override;
-};
-
-
-template<typename BASE>
-inline hwl<BASE>::hwl() {
-    for (unsigned addr = 0x800; addr < 0x803; ++addr){
-        this->register_custom_csr_rd(addr);
-        this->register_custom_csr_wr(addr);
-    }
-    for (unsigned addr = 0x804; addr < 0x807; ++addr){
-        this->register_custom_csr_rd(addr);
-        this->register_custom_csr_wr(addr);
-    }
-}
-
-template<typename BASE>
-inline iss::status iss::arch::hwl<BASE>::read_custom_csr_reg(unsigned addr, reg_t &val) {
-    switch(addr){
-    case 0x800: val = this->reg.lpstart0; break;
-    case 0x801: val = this->reg.lpend0;   break;
-    case 0x802: val = this->reg.lpcount0; break;
-    case 0x804: val = this->reg.lpstart1; break;
-    case 0x805: val = this->reg.lpend1;   break;
-    case 0x806: val = this->reg.lpcount1; break;
-    }
-    return iss::Ok;
-}
-
-template<typename BASE>
-inline iss::status iss::arch::hwl<BASE>::write_custom_csr_reg(unsigned addr, reg_t val) {
-    switch(addr){
-    case 0x800: this->reg.lpstart0 = val; break;
-    case 0x801: this->reg.lpend0   = val; break;
-    case 0x802: this->reg.lpcount0 = val; break;
-    case 0x804: this->reg.lpstart1 = val; break;
-    case 0x805: this->reg.lpend1   = val; break;
-    case 0x806: this->reg.lpcount1 = val; break;
-    }
-    return iss::Ok;
-}
-
-} // namespace arch
-} // namespace iss
-
-
-#endif /* _RISCV_HART_M_P_H */

src/iss/arch/tgc_c_decoder.cpp

@@ -1,175 +0,0 @@
-#include "tgc_c.h"
-#include <vector>
-#include <array>
-#include <cstdlib>
-#include <algorithm>
-
-namespace iss {
-namespace arch {
-namespace {
-// according to
-// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
-#ifdef __GCC__
-constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
-#elif __cplusplus < 201402L
-constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
-constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
-#else
-constexpr size_t bit_count(uint32_t u) {
-    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
-    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
-}
-#endif
-
-using opcode_e = traits<tgc_c>::opcode_e;
-
-/****************************************************************************
- * start opcode definitions
- ****************************************************************************/
-struct instruction_desriptor {
-    size_t length;
-    uint32_t value;
-    uint32_t mask;
-    opcode_e op;
-};
-
-const std::array<instruction_desriptor, 90> instr_descr = {{
-     /* entries are: size, valid value, valid mask, function ptr */
-    {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, opcode_e::LUI},
-    {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, opcode_e::AUIPC},
-    {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, opcode_e::JAL},
-    {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, opcode_e::JALR},
-    {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, opcode_e::BEQ},
-    {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, opcode_e::BNE},
-    {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, opcode_e::BLT},
-    {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, opcode_e::BGE},
-    {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, opcode_e::BLTU},
-    {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, opcode_e::BGEU},
-    {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, opcode_e::LB},
-    {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, opcode_e::LH},
-    {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, opcode_e::LW},
-    {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, opcode_e::LBU},
-    {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, opcode_e::LHU},
-    {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, opcode_e::SB},
-    {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, opcode_e::SH},
-    {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, opcode_e::SW},
-    {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, opcode_e::ADDI},
-    {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, opcode_e::SLTI},
-    {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, opcode_e::SLTIU},
-    {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, opcode_e::XORI},
-    {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, opcode_e::ORI},
-    {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, opcode_e::ANDI},
-    {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, opcode_e::SLLI},
-    {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRLI},
-    {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRAI},
-    {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::ADD},
-    {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::SUB},
-    {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::SLL},
-    {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::SLT},
-    {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::SLTU},
-    {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::XOR},
-    {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRL},
-    {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRA},
-    {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::OR},
-    {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::AND},
-    {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE},
-    {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, opcode_e::ECALL},
-    {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, opcode_e::EBREAK},
-    {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::URET},
-    {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::SRET},
-    {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::MRET},
-    {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, opcode_e::WFI},
-    {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::DRET},
-    {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRW},
-    {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRS},
-    {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRC},
-    {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRWI},
-    {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRSI},
-    {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRCI},
-    {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE_I},
-    {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::MUL},
-    {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::MULH},
-    {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::MULHSU},
-    {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::MULHU},
-    {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::DIV},
-    {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::DIVU},
-    {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::REM},
-    {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::REMU},
-    {16, 0b0000000000000000, 0b1110000000000011, opcode_e::CADDI4SPN},
-    {16, 0b0100000000000000, 0b1110000000000011, opcode_e::CLW},
-    {16, 0b1100000000000000, 0b1110000000000011, opcode_e::CSW},
-    {16, 0b0000000000000001, 0b1110000000000011, opcode_e::CADDI},
-    {16, 0b0000000000000001, 0b1110111110000011, opcode_e::CNOP},
-    {16, 0b0010000000000001, 0b1110000000000011, opcode_e::CJAL},
-    {16, 0b0100000000000001, 0b1110000000000011, opcode_e::CLI},
-    {16, 0b0110000000000001, 0b1110000000000011, opcode_e::CLUI},
-    {16, 0b0110000100000001, 0b1110111110000011, opcode_e::CADDI16SP},
-    {16, 0b0110000000000001, 0b1111000001111111, opcode_e::__reserved_clui},
-    {16, 0b1000000000000001, 0b1111110000000011, opcode_e::CSRLI},
-    {16, 0b1000010000000001, 0b1111110000000011, opcode_e::CSRAI},
-    {16, 0b1000100000000001, 0b1110110000000011, opcode_e::CANDI},
-    {16, 0b1000110000000001, 0b1111110001100011, opcode_e::CSUB},
-    {16, 0b1000110000100001, 0b1111110001100011, opcode_e::CXOR},
-    {16, 0b1000110001000001, 0b1111110001100011, opcode_e::COR},
-    {16, 0b1000110001100001, 0b1111110001100011, opcode_e::CAND},
-    {16, 0b1010000000000001, 0b1110000000000011, opcode_e::CJ},
-    {16, 0b1100000000000001, 0b1110000000000011, opcode_e::CBEQZ},
-    {16, 0b1110000000000001, 0b1110000000000011, opcode_e::CBNEZ},
-    {16, 0b0000000000000010, 0b1111000000000011, opcode_e::CSLLI},
-    {16, 0b0100000000000010, 0b1110000000000011, opcode_e::CLWSP},
-    {16, 0b1000000000000010, 0b1111000000000011, opcode_e::CMV},
-    {16, 0b1000000000000010, 0b1111000001111111, opcode_e::CJR},
-    {16, 0b1000000000000010, 0b1111111111111111, opcode_e::__reserved_cmv},
-    {16, 0b1001000000000010, 0b1111000000000011, opcode_e::CADD},
-    {16, 0b1001000000000010, 0b1111000001111111, opcode_e::CJALR},
-    {16, 0b1001000000000010, 0b1111111111111111, opcode_e::CEBREAK},
-    {16, 0b1100000000000010, 0b1110000000000011, opcode_e::CSWSP},
-    {16, 0b0000000000000000, 0b1111111111111111, opcode_e::DII},
-}};
-
-}
-
-template<>
-struct instruction_decoder<tgc_c> {
-    using opcode_e = traits<tgc_c>::opcode_e;
-    using code_word_t=traits<tgc_c>::code_word_t;
-
-    struct instruction_pattern {
-        uint32_t value;
-        uint32_t mask;
-        opcode_e id;
-    };
-
-    std::array<std::vector<instruction_pattern>, 4> qlut;
-
-    template<typename T>
-    unsigned decode_instruction(T);
-
-    instruction_decoder() {
-        for (auto instr : instr_descr) {
-            auto quadrant = instr.value & 0x3;
-            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
-        }
-        for(auto& lut: qlut){
-            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
-                return bit_count(a.mask) > bit_count(b.mask);
-            });
-        }
-    }
-};
-
-template<>
-unsigned instruction_decoder<tgc_c>::decode_instruction<traits<tgc_c>::code_word_t>(traits<tgc_c>::code_word_t instr){
-    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
-        return !((instr&e.mask) ^ e.value );
-    });
-    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
-}
-
-
-std::unique_ptr<instruction_decoder<tgc_c>> traits<tgc_c>::get_decoder(){
-    return std::make_unique<instruction_decoder<tgc_c>>();
-}
-
-}
-}

src/iss/arch/tgc_mapper.h

@@ -1,50 +0,0 @@
-#ifndef _ISS_ARCH_TGC_MAPPER_H
-#define _ISS_ARCH_TGC_MAPPER_H
-
-#include "riscv_hart_m_p.h"
-#include "tgc_c.h"
-using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
-#ifdef CORE_TGC_A
-#include "riscv_hart_m_p.h"
-#include <iss/arch/tgc_a.h>
-using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
-#endif
-#ifdef CORE_TGC_B
-#include "riscv_hart_m_p.h"
-#include <iss/arch/tgc_b.h>
-using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
-#endif
-#ifdef CORE_TGC_C_XRB_NN
-#include "riscv_hart_m_p.h"
-#include "hwl.h"
-#include <iss/arch/tgc_c_xrb_nn.h>
-using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
-#endif
-#ifdef CORE_TGC_D
-#include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_d.h>
-using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-#endif
-#ifdef CORE_TGC_D_XRB_MAC
-#include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_d_xrb_mac.h>
-using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-#endif
-#ifdef CORE_TGC_D_XRB_NN
-#include "riscv_hart_mu_p.h"
-#include "hwl.h"
-#include <iss/arch/tgc_d_xrb_nn.h>
-using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
-#endif
-#ifdef CORE_TGC_E
-#include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_e.h>
-using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-#endif
-#ifdef CORE_TGC_X
-#include "riscv_hart_mu_p.h"
-#include <iss/arch/tgc_x.h>
-using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
-#endif
-
-#endif

src/iss/arch/wt_cache.h

@@ -1,172 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2023 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       eyck@minres.com - initial implementation
- ******************************************************************************/
-
-#ifndef _RISCV_HART_M_P_WT_CACHE_H
-#define _RISCV_HART_M_P_WT_CACHE_H
-
-#include <iss/vm_types.h>
-#include <util/ities.h>
-#include <vector>
-#include <map>
-#include <memory>
-
-namespace iss {
-namespace arch {
-namespace cache {
-
-enum class state { INVALID, VALID};
-struct line {
-    uint64_t tag_addr{0};
-    state st{state::INVALID};
-    std::vector<uint8_t> data;
-    line(unsigned line_sz):  data(line_sz) {}
-};
-struct set {
-    std::vector<line> ways;
-    set(unsigned ways_count, line const& l): ways(ways_count, l) {}
-};
-struct cache {
-    std::vector<set> sets;
-
-    cache(unsigned size, unsigned line_sz, unsigned ways) {
-        line const ref_line{line_sz};
-        set const ref_set{ways, ref_line};
-        sets.resize(size/(ways*line_sz), ref_set);
-    }
-};
-
-struct wt_policy {
-    bool is_cacheline_hit(cache& c );
-};
-}
-
-// write thru, allocate on read, direct mapped or set-associative with round-robin replacement policy
-template <typename BASE> class wt_cache : public BASE {
-public:
-    using base_class = BASE;
-    using this_class = wt_cache<BASE>;
-    using reg_t = typename BASE::reg_t;
-    using mem_read_f = typename BASE::mem_read_f;
-    using mem_write_f = typename BASE::mem_write_f;
-    using phys_addr_t = typename BASE::phys_addr_t;
-
-    wt_cache();
-    virtual ~wt_cache() = default;
-
-    unsigned size{4096};
-    unsigned line_sz{32};
-    unsigned ways{1};
-    uint64_t io_address{0xf0000000};
-    uint64_t io_addr_mask{0xf0000000};
-protected:
-    iss::status read_cache(phys_addr_t addr, unsigned, uint8_t *const);
-    iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const *const);
-    std::function<mem_read_f> cache_mem_rd_delegate;
-    std::function<mem_write_f> cache_mem_wr_delegate;
-    std::unique_ptr<cache::cache> dcache_ptr;
-    std::unique_ptr<cache::cache> icache_ptr;
-    size_t get_way_select() {
-        return 0;
-    }
-};
-
-
-template<typename BASE>
-inline wt_cache<BASE>::wt_cache() {
-    auto cb = base_class::replace_mem_access(
-            [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);},
-            [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);});
-    cache_mem_rd_delegate = cb.first;
-    cache_mem_wr_delegate = cb.second;
-}
-
-template<typename BASE>
-iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) {
-    if(!icache_ptr) {
-        icache_ptr.reset(new cache::cache(size, line_sz, ways));
-        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
-    }
-    if((a.val&io_addr_mask) != io_address) {
-        auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
-        auto tag_addr=a.val>>util::ilog2(line_sz);
-        auto& set = (is_fetch(a.access)?icache_ptr:dcache_ptr)->sets[set_addr];
-        for(auto& cl: set.ways) {
-            if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
-                auto start_addr = a.val&(line_sz-1);
-                for(auto i = 0U; i<l; ++i)
-                    d[i] = cl.data[start_addr+i];
-                return iss::Ok;
-            }
-        }
-        auto& cl = set.ways[get_way_select()];
-        phys_addr_t cl_addr{a};
-        cl_addr.val=tag_addr<<util::ilog2(line_sz);
-        cache_mem_rd_delegate(cl_addr, line_sz, cl.data.data());
-        cl.tag_addr=tag_addr;
-        cl.st=cache::state::VALID;
-        auto start_addr = a.val&(line_sz-1);
-        for(auto i = 0U; i<l; ++i)
-            d[i] = cl.data[start_addr+i];
-        return iss::Ok;
-    } else
-        return cache_mem_rd_delegate(a, l, d);
-}
-
-template<typename BASE>
-iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) {
-    if(!dcache_ptr)
-        dcache_ptr.reset(new cache::cache(size, line_sz, ways));
-    auto res = cache_mem_wr_delegate(a, l, d);
-    if(res == iss::Ok && ((a.val&io_addr_mask) != io_address)) {
-        auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
-        auto tag_addr=a.val>>util::ilog2(line_sz);
-        auto& set = dcache_ptr->sets[set_addr];
-        for(auto& cl: set.ways) {
-            if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
-                auto start_addr = a.val&(line_sz-1);
-                for(auto i = 0U; i<l; ++i)
-                    cl.data[start_addr+i] = d[i];
-                break;
-            }
-        }
-    }
-    return res;
-}
-
-
-
-} // namespace arch
-} // namespace iss
-
-#endif /* _RISCV_HART_M_P_H */

src/iss/plugin/cycle_estimate.cpp

@@ -1,118 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       eyck@minres.com - initial API and implementation
- ******************************************************************************/
-
-#include "cycle_estimate.h"
-
-#include <iss/arch_if.h>
-#include <util/logging.h>
-#include <rapidjson/document.h>
-#include <rapidjson/istreamwrapper.h>
-#include <rapidjson/writer.h>
-#include <rapidjson/stringbuffer.h>
-#include <rapidjson/ostreamwrapper.h>
-#include <rapidjson/error/en.h>
-#include <fstream>
-
-using namespace rapidjson;
-using namespace std;
-
-iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name)
-: instr_if(nullptr)
-, config_file_name(config_file_name)
-{
-}
-
-iss::plugin::cycle_estimate::~cycle_estimate() {
-}
-
-bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
-    instr_if = vm.get_arch()->get_instrumentation_if();
-    if(!instr_if) return false;
-    const string  core_name = instr_if->core_type_name();
-    if (config_file_name.length() > 0) {
-        ifstream is(config_file_name);
-        if (is.is_open()) {
-            try {
-                IStreamWrapper isw(is);
-                Document d;
-                ParseResult ok = d.ParseStream(isw);
-                if(ok) {
-                    Value& val = d[core_name.c_str()];
-                    if(val.IsArray()){
-                        delays.reserve(val.Size());
-                        for (auto it = val.Begin(); it != val.End(); ++it) {
-                            auto& name = (*it)["name"];
-                            auto& size = (*it)["size"];
-                            auto& delay = (*it)["delay"];
-                            auto& branch = (*it)["branch"];
-                            if(delay.IsArray()) {
-                                auto dt = delay[0].Get<unsigned>();
-                                auto dnt = delay[1].Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
-                            } else if(delay.Is<unsigned>()) {
-                                auto d = delay.Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
-                            } else
-                                throw runtime_error("JSON parse error");
-                       }
-                    } else {
-                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
-                        return false;
-                   }
-                } else {
-                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
-                    return false;
-               }
-            } catch (runtime_error &e) {
-                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
-                return false;
-            }
-        } else {
-            LOG(ERR) << "Could not open input file " << config_file_name;
-            return false;
-        }
-    }
-    return true;
-
-}
-
-void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
-    assert(instr_if && "No instrumentation interface available but callback executed");
-    auto entry = delays[instr_info.instr_id];
-    bool taken = instr_if->is_branch_taken();
-    if (taken && (entry.taken > 1))
-        instr_if->update_last_instr_cycles(entry.taken);
-    else if (entry.not_taken > 1)
-        instr_if->update_last_instr_cycles(entry.not_taken);
-}

src/iss/plugin/pctrace.cpp

@@ -1,214 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       alex.com - initial implementation
- ******************************************************************************/
-
-#include <iss/arch_if.h>
-#include <iss/plugin/pctrace.h>
-#include <util/logging.h>
-#include <util/ities.h>
-#include <rapidjson/document.h>
-#include <rapidjson/istreamwrapper.h>
-#include <rapidjson/writer.h>
-#include <rapidjson/stringbuffer.h>
-#include <rapidjson/ostreamwrapper.h>
-#include <rapidjson/error/en.h>
-#include <fstream>
-#include <iostream>
-#ifdef WITH_LZ4
-#include <lz4frame.h>
-#endif
-
-namespace iss {
-namespace plugin {
-
-using namespace rapidjson;
-using namespace std;
-
-#ifdef WITH_LZ4
-class lz4compress_steambuf: public std::streambuf {
-public:
-    lz4compress_steambuf(const lz4compress_steambuf&) = delete;
-    lz4compress_steambuf& operator=(const lz4compress_steambuf&) = delete;
-    lz4compress_steambuf(std::ostream &sink, size_t buf_size)
-    : sink(sink)
-    , src_buf(buf_size)
-    , dest_buf(LZ4F_compressBound(buf_size, nullptr))
-    {
-        auto errCode = LZ4F_createCompressionContext(&ctx, LZ4F_VERSION);
-        if (LZ4F_isError(errCode) != 0)
-            throw std::runtime_error(std::string("Failed to create LZ4 context: ") + LZ4F_getErrorName(errCode));
-        size_t ret = LZ4F_compressBegin(ctx, &dest_buf.front(), dest_buf.capacity(), nullptr);
-        if (LZ4F_isError(ret) != 0)
-            throw std::runtime_error(std::string("Failed to start LZ4 compression: ") + LZ4F_getErrorName(ret));
-        setp(src_buf.data(), src_buf.data() + src_buf.size() - 1);
-        sink.write(dest_buf.data(), ret);
-    }
-
-    ~lz4compress_steambuf() {
-        close();
-    }
-
-    void close() {
-        if (closed)
-            return;
-        sync();
-        auto ret = LZ4F_compressEnd(ctx, dest_buf.data(), dest_buf.capacity(), nullptr);
-        if (LZ4F_isError(ret) != 0)
-            throw std::runtime_error(std::string("Failed to finish LZ4 compression: ") + LZ4F_getErrorName(ret));
-        sink.write(dest_buf.data(), ret);
-        LZ4F_freeCompressionContext(ctx);
-        closed = true;
-    }
-
-private:
-    int_type overflow(int_type ch) override {
-        compress_and_write();
-        *pptr() = static_cast<char_type>(ch);
-        pbump(1);
-        return ch;
-    }
-
-    int_type sync() override {
-        compress_and_write();
-        return 0;
-    }
-
-    void compress_and_write() {
-        if (closed)
-            throw std::runtime_error("Cannot write to closed stream");
-        if(auto orig_size = pptr() - pbase()){
-            auto ret = LZ4F_compressUpdate(ctx, dest_buf.data(), dest_buf.capacity(), pbase(), orig_size, nullptr);
-            if (LZ4F_isError(ret) != 0)
-                throw std::runtime_error(std::string("LZ4 compression failed: ") + LZ4F_getErrorName(ret));
-            if(ret) sink.write(dest_buf.data(), ret);
-            pbump(-orig_size);
-        }
-    }
-
-    std::ostream &sink;
-    std::vector<char> src_buf;
-    std::vector<char> dest_buf;
-    LZ4F_compressionContext_t ctx{ nullptr };
-    bool closed{ false };
-};
-#endif
-
-pctrace::pctrace(std::string const &filename)
-: instr_if(nullptr)
-, filename(filename)
-, output("output.trc")
-#ifdef WITH_LZ4
-, strbuf(new lz4compress_steambuf(output, 4096))
-, ostr(strbuf.get())
-#endif
-{ }
-
-pctrace::~pctrace() { }
-
-bool pctrace::registration(const char *const version, vm_if& vm) {
-    instr_if = vm.get_arch()->get_instrumentation_if();
-    if(!instr_if) return false;
-    const string  core_name = instr_if->core_type_name();
-    if (filename.length() > 0) {
-        ifstream is(filename);
-        if (is.is_open()) {
-            try {
-                IStreamWrapper isw(is);
-                Document d;
-                ParseResult ok = d.ParseStream(isw);
-                if(ok) {
-                    Value& val = d[core_name.c_str()];
-                    if(val.IsArray()){
-                        delays.reserve(val.Size());
-                        for (auto it = val.Begin(); it != val.End(); ++it) {
-                            auto& name = (*it)["name"];
-                            auto& size = (*it)["size"];
-                            auto& delay = (*it)["delay"];
-                            auto& branch = (*it)["branch"];
-                            if(delay.IsArray()) {
-                                auto dt = delay[0].Get<unsigned>();
-                                auto dnt = delay[1].Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), dt, dnt, branch.Get<bool>()});
-                            } else if(delay.Is<unsigned>()) {
-                                auto d = delay.Get<unsigned>();
-                                delays.push_back(instr_desc{size.Get<unsigned>(), d, d, branch.Get<bool>()});
-                            } else
-                                throw runtime_error("JSON parse error");
-
-                        }
-                    } else {
-                        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<endl;
-                        return false;
-                    }
-                } else {
-                    LOG(ERR)<<"plugin cycle_estimate: could not parse in JSON file at "<< ok.Offset()<<": "<<GetParseError_En(ok.Code())<<endl;
-                    return false;
-                }
-            } catch (runtime_error &e) {
-                LOG(ERR) << "Could not parse input file " << filename << ", reason: " << e.what();
-                return false;
-            }
-        } else {
-            LOG(ERR) << "Could not open input file " << filename;
-            return false;
-        }
-    }
-    return true;
-}
-
-void pctrace::callback(instr_info_t iinfo) {
-    auto delay = 0;
-    size_t id = iinfo.instr_id;
-    auto entry = delays[id];
-    auto instr = instr_if->get_instr_word();
-    auto call = id==65 || id ==86 || ((id==2 || id==3) && bit_sub<7,5>(instr)!=0) ;//not taking care of tail calls (jalr with loading x6)
-    bool taken = instr_if->is_branch_taken();
-    bool compressed = (instr&0x3)!=0x3;
-    if (taken) {
-        delay = entry.taken;
-        if(entry.taken > 1)
-            instr_if->update_last_instr_cycles(entry.taken);
-    } else {
-        delay = entry.not_taken;
-        if (entry.not_taken > 1)
-            instr_if->update_last_instr_cycles(entry.not_taken);
-    }
-#ifndef WITH_LZ4
-    output<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
-#else
-    auto rdbuf=ostr.rdbuf();
-    ostr<<std::hex <<"0x" << instr_if->get_pc() <<"," << delay <<"," << call<<","<<(compressed?2:4) <<"\n";
-#endif
-}
-}
-}

src/iss/plugin/pctrace.h

@@ -1,102 +0,0 @@
-/*******************************************************************************
- * Copyright (C) 2017 - 2023, MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * Contributors:
- *       eyck@minres.com - initial API and implementation
- ******************************************************************************/
-
-#ifndef _ISS_PLUGIN_COV_H_
-#define _ISS_PLUGIN_COV_H_
-
-#include <iss/vm_plugin.h>
-#include "iss/instrumentation_if.h"
-#include <json/json.h>
-#include <string>
-#include <fstream>
-
-
-namespace iss {
-namespace plugin {
-class lz4compress_steambuf;
-class pctrace : public iss::vm_plugin {
-    struct instr_delay {
-        std::string instr_name;
-        size_t size;
-        size_t not_taken_delay;
-        size_t taken_delay;
-    };
-    BEGIN_BF_DECL(instr_desc, uint32_t)
-        BF_FIELD(taken, 24, 8)
-        BF_FIELD(not_taken, 16, 8)
-        BF_FIELD(is_branch, 8, 8)
-        BF_FIELD(size, 0, 8)
-        instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken, bool branch): instr_desc() {
-            this->size=size;
-            this->taken=taken;
-            this->not_taken=not_taken;
-            this->is_branch=branch;
-        }
-    END_BF_DECL();
-
-public:
-
-    pctrace(const pctrace &) = delete;
-
-    pctrace(const pctrace &&) = delete;
-
-    pctrace(std::string const &);
-
-    virtual ~pctrace();
-
-    pctrace &operator=(const pctrace &) = delete;
-
-    pctrace &operator=(const pctrace &&) = delete;
-
-    bool registration(const char *const version, vm_if &arch) override;
-
-    sync_type get_sync() override { return POST_SYNC; };
-
-    void callback(instr_info_t) override;
-
-private:
-    iss::instrumentation_if *instr_if  {nullptr};
-    std::ofstream output;
-#ifdef WITH_LZ4
-    std::unique_ptr<lz4compress_steambuf> strbuf;
-    std::ostream ostr;
-#endif
-    std::string filename;
-    std::vector<instr_desc> delays;
-    bool jumped{false}, first{true};
-};
-}
-}
-
-#endif /* _ISS_PLUGIN_COV_H_ */

src/iss/tgc_c.cpp

@@ -30,9 +30,9 @@
  *
  *******************************************************************************/
 
-#include "tgc_c.h"
 #include "util/ities.h"
 #include <util/logging.h>
+#include <iss/arch/tgc_c.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>
@@ -41,10 +41,12 @@ using namespace iss::arch;
 
 constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_names;
 constexpr std::array<const char*, 36>    iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
+constexpr std::array<const uint32_t, 41> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
-constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
+constexpr std::array<const uint32_t, 41> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
 
-tgc_c::tgc_c()  = default;
+tgc_c::tgc_c() {
+    reg.icount = 0;
+}
 
 tgc_c::~tgc_c() = default;
 

src/main.cpp

@@ -1,222 +1,231 @@
-/*******************************************************************************
+/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
+ * All rights reserved.
- *
+ *
- * Redistribution and use in source and binary forms, with or without
+ * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+ * modification, are permitted provided that the following conditions are met:
- *
+ *
- * 1. Redistributions of source code must retain the above copyright notice,
+ * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
+ *    this list of conditions and the following disclaimer.
- *
+ *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
+ *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
+ *    and/or other materials provided with the distribution.
- *
+ *
- * 3. Neither the name of the copyright holder nor the names of its contributors
+ * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
+ *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+ *    without specific prior written permission.
- *
+ *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * POSSIBILITY OF SUCH DAMAGE.
- *
+ *
- *******************************************************************************/
+ *******************************************************************************/
-
+
-#include <iostream>
+#include <iostream>
-#include <vector>
+#include <iss/factory.h>
-#include <array>
+
-#include <iss/factory.h>
+#include <boost/lexical_cast.hpp>
-
+#include <boost/program_options.hpp>
-#include <boost/lexical_cast.hpp>
+#include <iss/arch/riscv_hart_m_p.h>
-#include <boost/program_options.hpp>
+#include "iss/arch/riscv_hart_m_p.h"
-#include "iss/arch/tgc_mapper.h"
+#include "iss/arch/tgc_c.h"
-#ifdef WITH_LLVM
+using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
-#include <iss/llvm/jit_helper.h>
+#ifdef CORE_TGC_B
-#endif
+#include "iss/arch/riscv_hart_m_p.h"
-#include <iss/log_categories.h>
+#include "iss/arch/tgc_b.h"
-#include "iss/plugin/cycle_estimate.h"
+using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
-#include "iss/plugin/instruction_count.h"
+#endif
-#include "iss/plugin/pctrace.h"
+#ifdef CORE_TGC_D
-#ifndef WIN32
+#include "iss/arch/riscv_hart_mu_p.h"
-#include <iss/plugin/loader.h>
+#include "iss/arch/tgc_d.h"
-#endif
+using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-#if defined(HAS_LUA)
+#endif
-#include <iss/plugin/lua.h>
+#ifdef CORE_TGC_D_XRB_MAC
-#endif
+#include "iss/arch/riscv_hart_mu_p.h"
-
+#include "iss/arch/tgc_d_xrb_mac.h"
-namespace po = boost::program_options;
+using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
-
+#endif
-int main(int argc, char *argv[]) {
+#ifdef WITH_LLVM
-    /*
+#include <iss/llvm/jit_helper.h>
-     *  Define and parse the program options
+#endif
-     */
+#include <iss/log_categories.h>
-    po::variables_map clim;
+#include <iss/plugin/cycle_estimate.h>
-    po::options_description desc("Options");
+#include <iss/plugin/instruction_count.h>
-    // clang-format off
+#include <iss/plugin/loader.h>
-    desc.add_options()
+#if defined(HAS_LUA)
-        ("help,h", "Print help message")
+#include <iss/plugin/lua.h>
-        ("verbose,v", po::value<int>()->default_value(4), "Sets logging verbosity")
+#endif
-        ("logfile,l", po::value<std::string>(), "Sets default log file.")
+
-        ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
+namespace po = boost::program_options;
-        ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
+
-        ("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
+int main(int argc, char *argv[]) {
-        ("reset,r", po::value<std::string>(), "reset address")
+    /*
-        ("dump-ir", "dump the intermediate representation")
+     *  Define and parse the program options
-        ("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
+     */
-        ("mem,m", po::value<std::string>(), "the memory input file")
+    po::variables_map clim;
-        ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
+    po::options_description desc("Options");
-        ("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, tcc")
+    // clang-format off
-        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
+    desc.add_options()
-    // clang-format on
+        ("help,h", "Print help message")
-    auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
+        ("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
-    try {
+        ("logfile,f", po::value<std::string>(), "Sets default log file.")
-        po::store(parsed, clim); // can throw
+        ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
-        // --help option
+        ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
-        if (clim.count("help")) {
+        ("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
-            std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
+        ("reset,r", po::value<std::string>(), "reset address")
-            return 0;
+        ("dump-ir", "dump the intermediate representation")
-        }
+        ("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
-        po::notify(clim); // throws on error, so do after help in case
+        ("mem,m", po::value<std::string>(), "the memory input file")
-    } catch (po::error &e) {
+        ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
-        // there are problems
+        ("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
-        std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
+        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
-        std::cerr << desc << std::endl;
+    // clang-format on
-        return 1;
+    auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
-    }
+    try {
-    std::vector<std::string> args = collect_unrecognized(parsed.options, po::include_positional);
+        po::store(parsed, clim); // can throw
-
+        // --help option
-    LOGGER(DEFAULT)::print_time() = false;
+        if (clim.count("help")) {
-    LOGGER(connection)::print_time() = false;
+            std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
-    auto l = logging::as_log_level(clim["verbose"].as<int>());
+            return 0;
-    LOGGER(DEFAULT)::reporting_level() = l;
+        }
-    LOGGER(connection)::reporting_level() = l;
+        po::notify(clim); // throws on error, so do after help in case
-    if (clim.count("logfile")) {
+    } catch (po::error &e) {
-        // configure the connection logger
+        // there are problems
-        auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
+        std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
-        LOG_OUTPUT(DEFAULT)::stream() = f;
+        std::cerr << desc << std::endl;
-        LOG_OUTPUT(connection)::stream() = f;
+        return 1;
-    }
+    }
-
+    std::vector<std::string> args = collect_unrecognized(parsed.options, po::include_positional);
-    std::vector<iss::vm_plugin *> plugin_list;
+
-    auto res = 0;
+    LOGGER(DEFAULT)::print_time() = false;
-    try {
+    LOGGER(connection)::print_time() = false;
-#ifdef WITH_LLVM
+    if (clim.count("verbose")) {
-        // application code comes here //
+        auto l = logging::as_log_level(clim["verbose"].as<int>());
-        iss::init_jit_debug(argc, argv);
+        LOGGER(DEFAULT)::reporting_level() = l;
-#endif
+        LOGGER(connection)::reporting_level() = l;
-        bool dump = clim.count("dump-ir");
+    }
-        auto & f = iss::core_factory::instance();
+    if (clim.count("logfile")) {
-        // instantiate the simulator
+        // configure the connection logger
-        iss::vm_ptr vm{nullptr};
+        auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
-        iss::cpu_ptr cpu{nullptr};
+        LOG_OUTPUT(DEFAULT)::stream() = f;
-        std::string isa_opt(clim["isa"].as<std::string>());
+        LOG_OUTPUT(connection)::stream() = f;
-        if(isa_opt.size()==0 || isa_opt == "?") {
+    }
-            std::cout<<"Available cores: "<<util::join(f.get_names(), ", ")<<std::endl;
+
-            return 0;
+    std::vector<iss::vm_plugin *> plugin_list;
-        } else if (isa_opt.find('|') != std::string::npos) {
+    auto res = 0;
-            std::tie(cpu, vm) = f.create(isa_opt+"|"+clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+    try {
-        } else {
+#ifdef WITH_LLVM
-            auto base_isa = isa_opt.substr(0, 5);
+        // application code comes here //
-            if(base_isa=="tgc_d" || base_isa=="tgc_e") {
+        iss::init_jit_debug(argc, argv);
-                isa_opt += "|mu_p_clic_pmp|"+clim["backend"].as<std::string>();
+#endif
-            } else {
+        bool dump = clim.count("dump-ir");
-                isa_opt += "|m_p|"+clim["backend"].as<std::string>();
+        // instantiate the simulator
-            }
+        iss::vm_ptr vm{nullptr};
-            std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as<unsigned>());
+        iss::cpu_ptr cpu{nullptr};
-        }
+        std::string isa_opt(clim["isa"].as<std::string>());
-        if(!cpu ){
+        if (isa_opt == "tgc_c") {
-            LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " <<clim["backend"].as<std::string>()<< std::endl;
+            std::tie(cpu, vm) =
-            return 127;
+                iss::create_cpu<tgc_c_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        }
+        } else
-        if(!vm ){
+#ifdef CORE_TGC_B
-            LOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " <<clim["backend"].as<std::string>()<< std::endl;
+        if (isa_opt == "tgc_b") {
-            return 127;
+            std::tie(cpu, vm) =
-        }
+                iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        if (clim.count("plugin")) {
+        } else
-            for (std::string const& opt_val : clim["plugin"].as<std::vector<std::string>>()) {
+#endif
-                std::string plugin_name=opt_val;
+#ifdef CORE_TGC_D
-                std::string arg{""};
+        if (isa_opt == "tgc_d") {
-                std::size_t found = opt_val.find('=');
+            std::tie(cpu, vm) =
-                if (found != std::string::npos) {
+                iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-                    plugin_name = opt_val.substr(0, found);
+        } else
-                    arg = opt_val.substr(found + 1, opt_val.size());
+#endif
-                }
+#ifdef CORE_TGC_D_XRB_MAC
-                if (plugin_name == "ic") {
+        if (isa_opt == "tgc_d_xrb_mac") {
-                    auto *ic_plugin = new iss::plugin::instruction_count(arg);
+            std::tie(cpu, vm) =
-                    vm->register_plugin(*ic_plugin);
+                iss::create_cpu<tgc_d_xrb_mac_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-                    plugin_list.push_back(ic_plugin);
+        } else
-                } else if (plugin_name == "ce") {
+#endif
-                    auto *ce_plugin = new iss::plugin::cycle_estimate(arg);
+        {
-                    vm->register_plugin(*ce_plugin);
+            LOG(ERR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
-                    plugin_list.push_back(ce_plugin);
+            return 127;
-                } else if (plugin_name == "pctrace") {
+        }
-                    auto *plugin = new iss::plugin::pctrace(arg);
+        if (clim.count("plugin")) {
-                    vm->register_plugin(*plugin);
+            for (std::string const& opt_val : clim["plugin"].as<std::vector<std::string>>()) {
-                    plugin_list.push_back(plugin);
+                std::string plugin_name=opt_val;
-               } else {
+                std::string filename{"cycles.txt"};
-#ifndef WIN32
+                std::size_t found = opt_val.find('=');
-                    std::vector<char const*> a{};
+                if (found != std::string::npos) {
-                    if(arg.length())
+                    plugin_name = opt_val.substr(0, found);
-                        a.push_back({arg.c_str()});
+                    filename = opt_val.substr(found + 1, opt_val.size());
-                    iss::plugin::loader l(plugin_name, {{"initPlugin"}});
+                }
-                    auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
+                if (plugin_name == "ic") {
-                    if(plugin){
+                    auto *ic_plugin = new iss::plugin::instruction_count(filename);
-                        vm->register_plugin(*plugin);
+                    vm->register_plugin(*ic_plugin);
-                        plugin_list.push_back(plugin);
+                    plugin_list.push_back(ic_plugin);
-                    } else
+                } else if (plugin_name == "ce") {
-#endif
+                    auto *ce_plugin = new iss::plugin::cycle_estimate(filename);
-                    {
+                    vm->register_plugin(*ce_plugin);
+                    plugin_list.push_back(ce_plugin);
+                } else {
+                    std::array<char const*, 1> a{{filename.c_str()}};
+                    iss::plugin::loader l(plugin_name, {{"initPlugin"}});
+                    auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
+                    if(plugin){
+                        vm->register_plugin(*plugin);
+                        plugin_list.push_back(plugin);
+                    } else {
                         LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
-                        return 127;
+                        return 127;
-                    }
+                    }
-                }
+                }
-            }
+            }
-        }
+        }
-        if (clim.count("disass")) {
+        if (clim.count("disass")) {
-            vm->setDisassEnabled(true);
+            vm->setDisassEnabled(true);
-            LOGGER(disass)::reporting_level() = logging::INFO;
+            LOGGER(disass)::reporting_level() = logging::INFO;
-            LOGGER(disass)::print_time() = false;
+            LOGGER(disass)::print_time() = false;
-            auto file_name = clim["disass"].as<std::string>();
+            auto file_name = clim["disass"].as<std::string>();
-            if (file_name.length() > 0) {
+            if (file_name.length() > 0) {
-                LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
+                LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
-                LOGGER(disass)::print_severity() = false;
+                LOGGER(disass)::print_severity() = false;
-            }
+            }
-        }
+        }
-        uint64_t start_address = 0;
+        uint64_t start_address = 0;
-        if (clim.count("mem"))
+        if (clim.count("mem"))
-            vm->get_arch()->load_file(clim["mem"].as<std::string>());
+            vm->get_arch()->load_file(clim["mem"].as<std::string>());
-        if (clim.count("elf"))
+        if (clim.count("elf"))
-            for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
+            for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
-                auto start_addr = vm->get_arch()->load_file(input);
+                auto start_addr = vm->get_arch()->load_file(input);
-                if (start_addr.second) start_address = start_addr.first;
+                if (start_addr.second) start_address = start_addr.first;
-            }
+            }
-        for (std::string input : args) {
+        for (std::string input : args) {
-            auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
+            auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
-            if (start_addr.second) start_address = start_addr.first;
+            if (start_addr.second) start_address = start_addr.first;
-        }
+        }
-        if (clim.count("reset")) {
+        if (clim.count("reset")) {
-            auto str = clim["reset"].as<std::string>();
+            auto str = clim["reset"].as<std::string>();
-            start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10);
+            start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10);
-        }
+        }
-        vm->reset(start_address);
+        vm->reset(start_address);
-        auto cycles = clim["instructions"].as<uint64_t>();
+        auto cycles = clim["instructions"].as<uint64_t>();
-        res = vm->start(cycles, dump);
+        res = vm->start(cycles, dump);
-    } catch (std::exception &e) {
+    } catch (std::exception &e) {
         LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
-                   << std::endl;
+                   << std::endl;
-        res = 2;
+        res = 2;
-    }
+    }
-    // cleanup to let plugins report of needed
+    // cleanup to let plugins report of needed
-    for (auto *p : plugin_list) {
+    for (auto *p : plugin_list) {
-        delete p;
+        delete p;
-    }
+    }
-    return res;
+    return res;
-}
+}

src/plugin/cycle_estimate.cpp

@@ -0,0 +1,94 @@
+/*******************************************************************************
+ * Copyright (C) 2017, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
+
+#include "iss/plugin/cycle_estimate.h"
+
+#include <iss/arch_if.h>
+#include <util/logging.h>
+#include <fstream>
+
+iss::plugin::cycle_estimate::cycle_estimate(std::string config_file_name)
+: arch_instr(nullptr)
+{
+    if (config_file_name.length() > 0) {
+        std::ifstream is(config_file_name);
+        if (is.is_open()) {
+            try {
+                is >> root;
+            } catch (Json::RuntimeError &e) {
+                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+            }
+        } else {
+            LOG(ERR) << "Could not open input file " << config_file_name;
+        }
+    }
+}
+
+iss::plugin::cycle_estimate::~cycle_estimate() {
+}
+
+bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& vm) {
+	arch_instr = vm.get_arch()->get_instrumentation_if();
+	if(!arch_instr) return false;
+	const std::string  core_name = arch_instr->core_type_name();
+    Json::Value &val = root[core_name];
+    if(!val.isNull() && val.isArray()){
+    	delays.reserve(val.size());
+    	for(auto it:val){
+    		auto name = it["name"];
+    		auto size = it["size"];
+    		auto delay = it["delay"];
+    		if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
+    		if(delay.isUInt()){
+				delays.push_back(instr_desc{size.asUInt(), delay.asUInt(), 0});
+    		} else {
+				delays.push_back(instr_desc{size.asUInt(), delay[0].asUInt(), delay[1].asUInt()});
+    		}
+    	}
+    } else {
+        LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
+    }
+	return true;
+
+}
+
+void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info const&) {
+    assert(arch_instr && "No instrumentation interface available but callback executed");
+	auto entry = delays[instr_info.instr_id];
+	bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
+    if (taken && entry.taken > 1)
+        arch_instr->set_curr_instr_cycles(entry.taken);
+    else if (entry.not_taken > 1)
+        arch_instr->set_curr_instr_cycles(entry.not_taken);
+}

src/plugin/instruction_count.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (C) 2017 - 2023 MINRES Technologies GmbH
+ * Copyright (C) 2017, MINRES Technologies GmbH
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -32,8 +32,8 @@
  *       eyck@minres.com - initial API and implementation
  ******************************************************************************/
 
-#include "instruction_count.h"
+#include "iss/plugin/instruction_count.h"
-#include <iss/instrumentation_if.h>
+#include "iss/instrumentation_if.h"
 
 #include <iss/arch_if.h>
 #include <util/logging.h>
@@ -90,6 +90,6 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
 	return true;
 }
 
-void iss::plugin::instruction_count::callback(instr_info_t instr_info) {
+void iss::plugin::instruction_count::callback(instr_info_t instr_info, exec_info const&) {
 	rep_counts[instr_info.instr_id]++;
 }

src/sysc/core_complex.cpp

@@ -30,18 +30,33 @@
  *
  *******************************************************************************/
 
-// clang-format off
+// clang-format off
-#include <iss/debugger/gdb_session.h>
+#include "iss/debugger/gdb_session.h"
-#include <iss/debugger/encoderdecoder.h>
+#include "iss/debugger/encoderdecoder.h"
-#include <iss/debugger/server.h>
+#include "iss/debugger/server.h"
-#include <iss/debugger/target_adapter_if.h>
+#include "iss/debugger/target_adapter_if.h"
-#include <iss/iss.h>
+#include "iss/iss.h"
-#include <iss/vm_types.h>
+#include "iss/vm_types.h"
-#ifndef WIN32
+#include <iss/plugin/loader.h>
-#include <iss/plugin/loader.h>
+#include "sysc/core_complex.h"
+#ifdef CORE_TGC_B
+#include "iss/arch/riscv_hart_m_p.h"
+#include "iss/arch/tgc_b.h"
+using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
+#endif
+#include "iss/arch/riscv_hart_m_p.h"
+#include "iss/arch/tgc_c.h"
+using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
+#ifdef CORE_TGC_D
+#include "iss/arch/riscv_hart_mu_p.h"
+#include "iss/arch/tgc_d.h"
+using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
+#endif
+#ifdef CORE_TGC_D_XRB_MAC
+#include "iss/arch/riscv_hart_mu_p.h"
+#include "iss/arch/tgc_d_xrb_mac.h"
+using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, iss::arch::FEAT_PMP>;
 #endif
-#include "core_complex.h"
-#include <iss/arch/tgc_mapper.h>
 #include <scc/report.h>
 #include <util/ities.h>
 #include <iostream>
@@ -49,9 +64,7 @@
 #include <array>
 #include <iss/plugin/cycle_estimate.h>
 #include <iss/plugin/instruction_count.h>
-#include <iss/plugin/pctrace.h>
+// clang-format on
-
-// clang-format on
 
 #define STR(X) #X
 #define CREATE_CORE(CN) \
@@ -70,12 +83,12 @@ using namespace scv_tr;
 #define GET_PROP_VALUE(P) P.getValue()
 #endif
 
-#ifdef _MSC_VER
+#ifdef _MSC_VER
-// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
+// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
-#define strncasecmp _strnicmp
+#define strncasecmp _strnicmp
-#define strcasecmp _stricmp
+#define strcasecmp _stricmp
-#endif
+#endif
-
+
 namespace sysc {
 namespace tgfs {
 using namespace std;
@@ -107,8 +120,7 @@ public:
     heart_state_t &get_state() { return this->state; }
 
     void notify_phase(iss::arch_if::exec_phase p) override {
-        if (p == iss::arch_if::ISTART)
+        if (p == iss::arch_if::ISTART) owner->sync(this->reg.icount);
-            owner->sync(this->instr_if.get_total_cycles());
     }
 
     sync_type needed_sync() const override { return PRE_SYNC; }
@@ -117,8 +129,7 @@ public:
         if (!owner->disass_output(pc, instr)) {
             std::stringstream s;
             s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
-              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
+              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
-              << this->reg.icount + this->cycle_offset << "]";
             SCCDEBUG(owner->name())<<"disass: "
                 << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
                 << std::setfill(' ') << std::left << instr << s.str();
@@ -129,7 +140,7 @@ public:
         if (addr.access && access_type::DEBUG)
             return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
         else {
-            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? Ok : Err;
+            return owner->read_mem(addr.val, length, data, addr.access && access_type::FETCH) ? Ok : Err;
         }
     }
 
@@ -178,26 +189,26 @@ public:
 
     void wait_until(uint64_t flags) override {
         SCCDEBUG(owner->name()) << "Sleeping until interrupt";
-        while(this->reg.pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) {
+        do {
             sc_core::wait(wfi_evt);
-        }
+        } while (this->reg.pending_trap == 0);
         PLAT::wait_until(flags);
     }
 
     void local_irq(short id, bool value) {
         reg_t mask = 0;
         switch (id) {
-        case 3: // SW
+        case 16: // SW
             mask = 1 << 3;
             break;
-        case 7: // timer
+        case 17: // timer
             mask = 1 << 7;
             break;
-        case 11: // external
+        case 18: // external
             mask = 1 << 11;
             break;
         default:
-            if(id>15) mask = 1 << id;
+            /* do nothing*/
             break;
         }
         if (value) {
@@ -292,14 +303,11 @@ public:
 #ifdef CORE_TGC_D
         CREATE_CORE(tgc_d)
 #endif
-#ifdef CORE_TGC_D_XRB_MAC
+#ifdef CORE_TGC_D_XRB_MACD
         CREATE_CORE(tgc_d_xrb_mac)
-#endif
-#ifdef CORE_TGC_D_XRB_NN
-        CREATE_CORE(tgc_d_xrb_nn)
 #endif
         {
-            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
+            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
         }
         auto *srv = debugger::server<debugger::gdb_session>::get();
         if (srv) tgt_adapter = srv->get_target();
@@ -331,7 +339,6 @@ SC_HAS_PROCESS(core_complex);// NOLINT
 #ifndef CWR_SYSTEMC
 core_complex::core_complex(sc_module_name const& name)
 : sc_module(name)
-, fetch_lut(tlm_dmi_ext())
 , read_lut(tlm_dmi_ext())
 , write_lut(tlm_dmi_ext())
 {
@@ -341,13 +348,7 @@ core_complex::core_complex(sc_module_name const& name)
 
 void core_complex::init(){
 	trc=new core_trace();
-    ibus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
+    initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
-        auto lut_entry = fetch_lut.getEntry(start);
-        if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
-            fetch_lut.removeEntry(lut_entry);
-        }
-    });
-    dbus.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
         auto lut_entry = read_lut.getEntry(start);
         if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && end <= lut_entry.get_end_address() + 1) {
             read_lut.removeEntry(lut_entry);
@@ -365,11 +366,8 @@ void core_complex::init(){
     sensitive << sw_irq_i;
     SC_METHOD(timer_irq_cb);
     sensitive << timer_irq_i;
-    SC_METHOD(ext_irq_cb);
+    SC_METHOD(global_irq_cb);
-    sensitive << ext_irq_i;
+    sensitive << global_irq_i;
-    SC_METHOD(local_irq_cb);
-    for(auto pin:local_irq_i)
-        sensitive << pin;
     trc->m_db=scv_tr_db::get_default_db();
 
 	SC_METHOD(forward);
@@ -417,12 +415,7 @@ void core_complex::before_end_of_elaboration() {
                 auto *plugin = new iss::plugin::cycle_estimate(filename);
                 cpu->vm->register_plugin(*plugin);
                 plugin_list.push_back(plugin);
-            } else if (plugin_name == "pctrace") {
-                auto *plugin = new iss::plugin::pctrace(filename);
-                cpu->vm->register_plugin(*plugin);
-                plugin_list.push_back(plugin);
             } else {
-#ifndef WIN32
                 std::array<char const*, 1> a{{filename.c_str()}};
                 iss::plugin::loader l(plugin_name, {{"initPlugin"}});
                 auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
@@ -430,7 +423,6 @@ void core_complex::before_end_of_elaboration() {
                     cpu->vm->register_plugin(*plugin);
                     plugin_list.push_back(plugin);
                 } else
-#endif
                     SCCERR(SCMOD) << "Unknown plugin '" << plugin_name << "' or plugin not found";
             }
         }
@@ -439,7 +431,7 @@ void core_complex::before_end_of_elaboration() {
 }
 
 void core_complex::start_of_simulation() {
-    // quantum_keeper.reset();
+    quantum_keeper.reset();
     if (GET_PROP_VALUE(elf_file).size() > 0) {
         istringstream is(GET_PROP_VALUE(elf_file));
         string s;
@@ -491,24 +483,15 @@ void core_complex::rst_cb() {
     if (rst_i.read()) cpu->set_interrupt_execution(true);
 }
 
-void core_complex::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
+void core_complex::sw_irq_cb() { cpu->local_irq(16, sw_irq_i.read()); }
 
-void core_complex::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
+void core_complex::timer_irq_cb() { cpu->local_irq(17, timer_irq_i.read()); }
 
-void core_complex::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
+void core_complex::global_irq_cb() { cpu->local_irq(18, global_irq_i.read()); }
-
-void core_complex::local_irq_cb() {
-    for(auto i=0U; i<local_irq_i.size(); ++i) {
-        if(local_irq_i[i].event()) {
-            cpu->local_irq(16+i, local_irq_i[i].read());
-        }
-    }
-}
 
 void core_complex::run() {
     wait(SC_ZERO_TIME); // separate from elaboration phase
     do {
-        wait(SC_ZERO_TIME);
         if (rst_i.read()) {
             cpu->reset(GET_PROP_VALUE(reset_address));
             wait(rst_i.negedge_event());
@@ -516,7 +499,6 @@ void core_complex::run() {
         while (curr_clk.read() == SC_ZERO_TIME) {
             wait(curr_clk.value_changed_event());
         }
-        quantum_keeper.reset();
         cpu->set_interrupt_execution(false);
         cpu->start();
     } while (cpu->get_interrupt_execution());
@@ -524,15 +506,14 @@ void core_complex::run() {
 }
 
 bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
-    auto& dmi_lut = is_fetch?fetch_lut:read_lut;
+    auto lut_entry = read_lut.getEntry(addr);
-    auto lut_entry = dmi_lut.getEntry(addr);
+    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
+        addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
         std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
         quantum_keeper.inc(lut_entry.get_read_latency());
         return true;
     } else {
-        auto& sckt = is_fetch? ibus : dbus;
         tlm::tlm_generic_payload gp;
         gp.set_command(tlm::TLM_READ_COMMAND);
         gp.set_address(addr);
@@ -547,13 +528,8 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
             auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-        sckt->b_transport(gp, delay);
+        initiator->b_transport(gp, delay);
-        auto incr = delay-quantum_keeper.get_local_time();
+        SCCTRACE(this->name()) << "read_mem(0x" << std::hex << addr << ") : " << data;
-        if(is_fetch)
-            ibus_inc+=incr;
-        else
-            dbus_inc+=incr;
-        SCCTRACE(this->name()) << "[local time: "<<delay<<"]: finish read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
@@ -561,10 +537,13 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
-            if (sckt->get_direct_mem_ptr(gp, dmi_data)) {
+            if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
                 if (dmi_data.is_read_allowed())
-                    dmi_lut.addEntry(dmi_data, dmi_data.get_start_address(),
+                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
+                if (dmi_data.is_write_allowed())
+                    write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
+                                       dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
             }
         }
         return true;
@@ -593,9 +572,9 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
             auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-        dbus->b_transport(gp, delay);
+        initiator->b_transport(gp, delay);
-        dbus_inc+=delay-quantum_keeper.get_local_time();
+        quantum_keeper.set(delay);
-        SCCTRACE() << "[local time: "<<delay<<"]: finish write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
+        SCCTRACE() << "write_mem(0x" << std::hex << addr << ") : " << data;
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
         }
@@ -603,7 +582,10 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
             gp.set_command(tlm::TLM_READ_COMMAND);
             gp.set_address(addr);
             tlm_dmi_ext dmi_data;
-            if (dbus->get_direct_mem_ptr(gp, dmi_data)) {
+            if (initiator->get_direct_mem_ptr(gp, dmi_data)) {
+                if (dmi_data.is_read_allowed())
+                    read_lut.addEntry(dmi_data, dmi_data.get_start_address(),
+                                      dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
                 if (dmi_data.is_write_allowed())
                     write_lut.addEntry(dmi_data, dmi_data.get_start_address(),
                                        dmi_data.get_end_address() - dmi_data.get_start_address() + 1);
@@ -614,25 +596,43 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
 }
 
 bool core_complex::read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data) {
-    tlm::tlm_generic_payload gp;
+    auto lut_entry = read_lut.getEntry(addr);
-    gp.set_command(tlm::TLM_READ_COMMAND);
+    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-    gp.set_address(addr);
+        addr + length <= lut_entry.get_end_address() + 1) {
-    gp.set_data_ptr(data);
+        auto offset = addr - lut_entry.get_start_address();
-    gp.set_data_length(length);
+        std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-    gp.set_streaming_width(length);
+        quantum_keeper.inc(lut_entry.get_read_latency());
-    return dbus->transport_dbg(gp) == length;
+        return true;
+    } else {
+        tlm::tlm_generic_payload gp;
+        gp.set_command(tlm::TLM_READ_COMMAND);
+        gp.set_address(addr);
+        gp.set_data_ptr(data);
+        gp.set_data_length(length);
+        gp.set_streaming_width(length);
+        return initiator->transport_dbg(gp) == length;
+    }
 }
 
 bool core_complex::write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data) {
-    write_buf.resize(length);
+    auto lut_entry = write_lut.getEntry(addr);
-    std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
+    if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
-    tlm::tlm_generic_payload gp;
+        addr + length <= lut_entry.get_end_address() + 1) {
-    gp.set_command(tlm::TLM_WRITE_COMMAND);
+        auto offset = addr - lut_entry.get_start_address();
-    gp.set_address(addr);
+        std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-    gp.set_data_ptr(write_buf.data());
+        quantum_keeper.inc(lut_entry.get_read_latency());
-    gp.set_data_length(length);
+        return true;
-    gp.set_streaming_width(length);
+    } else {
-    return dbus->transport_dbg(gp) == length;
+        write_buf.resize(length);
+        std::copy(data, data + length, write_buf.begin()); // need to copy as TLM does not guarantee data integrity
+        tlm::tlm_generic_payload gp;
+        gp.set_command(tlm::TLM_WRITE_COMMAND);
+        gp.set_address(addr);
+        gp.set_data_ptr(write_buf.data());
+        gp.set_data_length(length);
+        gp.set_streaming_width(length);
+        return initiator->transport_dbg(gp) == length;
+    }
 }
 } /* namespace SiFive */
 } /* namespace sysc */

src/sysc/register_tgc_c.cpp

@@ -1,33 +0,0 @@
-/*
- * register_tgc_c.cpp
- *
- *  Created on: Jul 5, 2023
- *      Author: eyck
- */
-
-
-
-
-#include <iss/factory.h>
-#include <iss/arch/tgc_c.h>
-#include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_mu_p.h>
-#include "sc_core_adapter.h"
-#include "core_complex.h"
-
-namespace iss {
-namespace {
-volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
-            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
-        }),
-        core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
-            arch::tgc_c* lcpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
-            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
-        })
-};
-}
-}

src/sysc/sc_core_adapter.h

@@ -1,148 +0,0 @@
-/*
- * sc_core_adapter.h
- *
- *  Created on: Jul 5, 2023
- *      Author: eyck
- */
-
-#ifndef _SYSC_SC_CORE_ADAPTER_H_
-#define _SYSC_SC_CORE_ADAPTER_H_
-
-
-#include <scc/report.h>
-#include <util/ities.h>
-#include "core_complex.h"
-#include <iss/iss.h>
-#include <iss/vm_types.h>
-#include <iostream>
-
-
-template<typename PLAT>
-class sc_core_adapter : public PLAT {
-public:
-    using reg_t       = typename iss::arch::traits<typename PLAT::core>::reg_t;
-    using phys_addr_t = typename iss::arch::traits<typename PLAT::core>::phys_addr_t;
-    using heart_state_t = typename PLAT::hart_state_type;
-    sc_core_adapter(sysc::tgfs::core_complex *owner)
-    : owner(owner) { }
-
-    uint32_t get_mode() { return this->reg.PRIV; }
-
-    inline void set_interrupt_execution(bool v) { this->interrupt_sim = v?1:0; }
-
-    inline bool get_interrupt_execution() { return this->interrupt_sim; }
-
-    heart_state_t &get_state() { return this->state; }
-
-    void notify_phase(iss::arch_if::exec_phase p) override {
-        if (p == iss::arch_if::ISTART)
-            owner->sync(this->instr_if.get_total_cycles());
-    }
-
-    iss::sync_type needed_sync() const override { return iss::PRE_SYNC; }
-
-    void disass_output(uint64_t pc, const std::string instr) override {
-        static constexpr std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
-        if (!owner->disass_output(pc, instr)) {
-            std::stringstream s;
-            s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
-              << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
-              << this->reg.icount + this->cycle_offset << "]";
-            SCCDEBUG(owner->name())<<"disass: "
-                << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
-                << std::setfill(' ') << std::left << instr << s.str();
-        }
-    };
-
-    iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) override {
-        if (addr.access && iss::access_type::DEBUG)
-            return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
-        else {
-            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? iss::Ok : iss::Err;
-        }
-    }
-
-    iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) override {
-        if (addr.access && iss::access_type::DEBUG)
-            return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
-        else {
-            auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
-            // clear MTIP on mtimecmp write
-            if (addr.val == 0x2004000) {
-                reg_t val;
-                this->read_csr(iss::arch::mip, val);
-                if (val & (1ULL << 7)) this->write_csr(iss::arch::mip, val & ~(1ULL << 7));
-            }
-            return res;
-        }
-    }
-
-    iss::status read_csr(unsigned addr, reg_t &val) override {
-#ifndef CWR_SYSTEMC
-        if((addr==iss::arch::time || addr==iss::arch::timeh) && owner->mtime_o.get_interface(0)){
-            uint64_t time_val;
-            bool ret = owner->mtime_o->nb_peek(time_val);
-            if (addr == iss::arch::time) {
-                val = static_cast<reg_t>(time_val);
-            } else if (addr == iss::arch::timeh) {
-                if (sizeof(reg_t) != 4) return iss::Err;
-                val = static_cast<reg_t>(time_val >> 32);
-            }
-            return ret?iss::Ok:iss::Err;
-#else
-        if((addr==iss::arch::time || addr==iss::arch::timeh)){
-            uint64_t time_val = owner->mtime_i.read();
-            if (addr == iss::arch::time) {
-                val = static_cast<reg_t>(time_val);
-            } else if (addr == iss::arch::timeh) {
-                if (sizeof(reg_t) != 4) return iss::Err;
-                val = static_cast<reg_t>(time_val >> 32);
-            }
-            return iss::Ok;
-#endif
-        } else {
-            return PLAT::read_csr(addr, val);
-        }
-    }
-
-    void wait_until(uint64_t flags) override {
-        SCCDEBUG(owner->name()) << "Sleeping until interrupt";
-        while(this->reg.pending_trap == 0 && (this->csr[iss::arch::mip] & this->csr[iss::arch::mie]) == 0) {
-            sc_core::wait(wfi_evt);
-        }
-        PLAT::wait_until(flags);
-    }
-
-    void local_irq(short id, bool value) {
-        reg_t mask = 0;
-        switch (id) {
-        case 3: // SW
-            mask = 1 << 3;
-            break;
-        case 7: // timer
-            mask = 1 << 7;
-            break;
-        case 11: // external
-            mask = 1 << 11;
-            break;
-        default:
-            if(id>15) mask = 1 << id;
-            break;
-        }
-        if (value) {
-            this->csr[iss::arch::mip] |= mask;
-            wfi_evt.notify();
-        } else
-            this->csr[iss::arch::mip] &= ~mask;
-        this->check_interrupt();
-        if(value)
-            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
-    }
-
-private:
-    sysc::tgfs::core_complex *const owner;
-    sc_core::sc_event wfi_evt;
-};
-
-
-#endif /* _SYSC_SC_CORE_ADAPTER_H_ */

src/vm/interp/.gitignore

@@ -0,0 +1 @@
+/vm_tgc_*.cpp

src/vm/llvm/vm_tgf_c.cpp

@@ -30,7 +30,7 @@
  *
  *******************************************************************************/
 
-#include <iss/arch/tgc_c.h>
+#include <iss/arch/tgf_c.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -52,7 +52,7 @@ namespace fp_impl {
 void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
 }
 
-namespace tgc_c {
+namespace tgf_c {
 using namespace ::llvm;
 using namespace iss::arch;
 using namespace iss::debugger;
@@ -4151,11 +4151,11 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *b
                           bb, this->trap_blk, 1);
 }
 
-} // namespace tgc_c
+} // namespace tgf_c
 
 template <>
-std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
+std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
-    auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
+    auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }