extends factory to support SystemC core wrapper

.project

@@ -23,5 +23,6 @@
 		<nature>org.eclipse.cdt.core.ccnature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
 	</natures>
 </projectDescription>

gen_input/templates/CORENAME.h.gtl

@@ -111,7 +111,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
     
-    enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
+    enum class opcode_e : unsigned short {<%instructions.eachWithIndex{instr, index -> %>
         ${instr.instruction.name} = ${index},<%}%>
         MAX_OPCODE
     };

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -320,24 +320,15 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 #include <iss/arch/riscv_hart_mu_p.h>
 namespace iss {
 namespace {
-std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|m_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* lcpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()>();
+            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
         }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|mu_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* lcpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()>();
+            return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};
         })
 };
 }
 }
-extern "C" {
-	bool* get_${coreDef.name.toLowerCase()}_interp_creators() {
-		return iss::dummy.data();
-	}
-}

gen_input/templates/tcc/CORENAME.cpp.gtl

@@ -206,7 +206,7 @@ private:
             ${it}<%}%>
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc=pc+ ${instr.length/8};
+        pc=pc+4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();<%instr.behavior.eachLine{%>
         ${it}<%}%>
@@ -317,24 +317,15 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 #include <iss/arch/riscv_hart_mu_p.h>
 namespace iss {
 namespace {
-std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|m_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* lcpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()>();
+            return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
         }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()|mu_p|interp", [](unsigned gdb_port) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* lcpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()>();
+            return {cpu_ptr{lcpu}, vm_ptr{iss::tcc::create(lcpu, gdb_port)}};
         })
 };
 }
 }
-extern "C" {
-	bool* get_${coreDef.name.toLowerCase()}_tcc_creators() {
-		return iss::dummy.data();
-	}
-}

src/iss/arch/riscv_hart_m_p.h

@@ -619,9 +619,9 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
+        throw std::runtime_error("memory load file is not a valid elf file");
     }
-    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    throw std::runtime_error("memory load file not found");
 }
 
 template<typename BASE, features_e FEAT>

src/iss/arch/riscv_hart_msu_vp.h

@@ -588,9 +588,9 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
+        throw std::runtime_error("memory load file is not a valid elf file");
     }
-    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    throw std::runtime_error("memory load file not found");
 }
 
 template <typename BASE>

src/iss/arch/riscv_hart_mu_p.h

@@ -690,9 +690,9 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
             }
             return std::make_pair(entry, true);
         }
-        throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name));
+        throw std::runtime_error("memory load file is not a valid elf file");
     }
-    throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    throw std::runtime_error("memory load file not found");
 }
 
 template<typename BASE, features_e FEAT>

src/iss/arch/tgc_c.h

@@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
     static constexpr std::array<const char*, 36> reg_aliases{
         {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
 
-    enum constants {MISA_VAL=1073746180, MARCHID_VAL=2147483651, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
+    enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 
@@ -83,7 +83,7 @@ template <> struct traits<tgc_c> {
 
     enum mem_type_e { MEM, FENCE, RES, CSR };
     
-    enum class opcode_e {
+    enum class opcode_e : unsigned short {
         LUI = 0,
         AUIPC = 1,
         JAL = 2,

src/sysc/sc_core_adapter.h

@@ -88,7 +88,7 @@ public:
                 if (sizeof(reg_t) != 4) return iss::Err;
                 val = static_cast<reg_t>(time_val >> 32);
             }
-            return ret?iss::Ok:iss::Err;
+            return ret?Ok:Err;
 #else
         if((addr==iss::arch::time || addr==iss::arch::timeh)){
             uint64_t time_val = owner->mtime_i.read();
@@ -141,7 +141,7 @@ public:
 
 private:
     sysc::tgfs::core_complex *const owner;
-    sc_core::sc_event wfi_evt;
+    sc_event wfi_evt;
 };
 
 

src/vm/interp/vm_tgc_c.cpp

@@ -388,7 +388,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (uint32_t)(*PC + (int32_t)imm);
+                                        *(X+rd) = *PC + (int32_t)imm;
                                     }
                                 }
                             }
@@ -418,9 +418,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     }
                                     else {
                                         if(rd !=  0) {
-                                            *(X+rd) = (uint32_t)(*PC +  4);
+                                            *(X+rd) = *PC +  4;
                                         }
-                                        *NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm));
+                                        *NEXT_PC = *PC + (int32_t)sext<21>(imm);
                                         this->core.reg.last_branch = 1;
                                     }
                                 }
@@ -447,13 +447,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1);
+                                    uint32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 0x1;
                                     if(new_pc % traits::INSTR_ALIGNMENT) {
                                         raise(0,  0);
                                     }
                                     else {
                                         if(rd !=  0) {
-                                            *(X+rd) = (uint32_t)(*PC +  4);
+                                            *(X+rd) = *PC +  4;
                                         }
                                         *NEXT_PC = new_pc & ~ 0x1;
                                         this->core.reg.last_branch = 1;
@@ -487,7 +487,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -520,7 +520,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -553,7 +553,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -586,7 +586,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -619,7 +619,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -652,7 +652,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                             raise(0,  0);
                                         }
                                         else {
-                                            *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                            *NEXT_PC = *PC + (int16_t)sext<13>(imm);
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -680,7 +680,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
                                     int8_t read_res = super::template read_mem<int8_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LB;
                                     int8_t res = (int8_t)read_res;
@@ -711,7 +711,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
                                     int16_t read_res = super::template read_mem<int16_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LH;
                                     int16_t res = (int16_t)read_res;
@@ -742,7 +742,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
                                     int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LW;
                                     int32_t res = (int32_t)read_res;
@@ -773,10 +773,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
                                     uint8_t read_res = super::template read_mem<uint8_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LBU;
-                                    uint8_t res = read_res;
+                                    uint8_t res = (uint8_t)read_res;
                                     if(rd !=  0) {
                                         *(X+rd) = (uint32_t)res;
                                     }
@@ -804,10 +804,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                    uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
                                     uint16_t read_res = super::template read_mem<uint16_t>(traits::MEM, load_address);
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_LHU;
-                                    uint16_t res = read_res;
+                                    uint16_t res = (uint16_t)read_res;
                                     if(rd !=  0) {
                                         *(X+rd) = (uint32_t)res;
                                     }
@@ -835,8 +835,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
-                                    super::template write_mem<uint8_t>(traits::MEM, store_address, (uint8_t)*(X+rs2));
+                                    uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    super::template write_mem<uint8_t>(traits::MEM, store_address, (int8_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SB;
                                 }
                             }
@@ -862,8 +862,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
-                                    super::template write_mem<uint16_t>(traits::MEM, store_address, (uint16_t)*(X+rs2));
+                                    uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    super::template write_mem<uint16_t>(traits::MEM, store_address, (int16_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SH;
                                 }
                             }
@@ -889,8 +889,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
-                                    super::template write_mem<uint32_t>(traits::MEM, store_address, (uint32_t)*(X+rs2));
+                                    uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
+                                    super::template write_mem<uint32_t>(traits::MEM, store_address, (int32_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_SW;
                                 }
                             }
@@ -917,7 +917,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                        *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm);
                                     }
                                 }
                             }
@@ -1133,7 +1133,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt);
+                                        *(X+rd) = (int32_t)*(X+rs1) >> shamt;
                                     }
                                 }
                             }
@@ -1160,7 +1160,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2));
+                                        *(X+rd) = *(X+rs1) + *(X+rs2);
                                     }
                                 }
                             }
@@ -1187,7 +1187,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2));
+                                        *(X+rd) = *(X+rs1) - *(X+rs2);
                                     }
                                 }
                             }
@@ -1349,7 +1349,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN -  1)));
+                                        *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN -  1));
                                     }
                                 }
                             }
@@ -1426,7 +1426,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
-                                super::template write_mem<uint32_t>(traits::FENCE, traits::fence, (uint8_t)pred <<  4 | succ);
+                                super::template write_mem<uint8_t>(traits::FENCE, traits::fence, pred <<  4 | succ);
                                 if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_FENCE;
                             }
                 TRAP_FENCE:break;
@@ -1705,7 +1705,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 4;
                 // execute instruction
                 {
-                                super::template write_mem<uint32_t>(traits::FENCE, traits::fencei, imm);
+                                super::template write_mem<uint16_t>(traits::FENCE, traits::fencei, imm);
                                 if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_FENCE_I;
                             }
                 TRAP_FENCE_I:break;
@@ -1730,7 +1730,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2));
+                                    int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)res;
                                     }
@@ -1758,7 +1758,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2));
+                                    int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                     }
@@ -1786,7 +1786,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2));
+                                    int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                     }
@@ -1814,7 +1814,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint64_t res = (uint64_t)((uint64_t)*(X+rs1) * (uint64_t)*(X+rs2));
+                                    uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
                                     if(rd != 0) {
                                         *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                     }
@@ -1851,11 +1851,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                                 *(X+rd) = MMIN;
                                             }
                                             else {
-                                                *(X+rd) = (uint32_t)(dividend / divisor);
+                                                *(X+rd) = dividend / divisor;
                                             }
                                         }
                                         else {
-                                            *(X+rd) = (uint32_t)- 1;
+                                            *(X+rd) = (int32_t)- 1;
                                         }
                                     }
                                 }
@@ -1884,12 +1884,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 else {
                                     if(*(X+rs2) !=  0) {
                                         if(rd != 0) {
-                                            *(X+rd) = (uint32_t)(*(X+rs1) / *(X+rs2));
+                                            *(X+rd) = *(X+rs1) / *(X+rs2);
                                         }
                                     }
                                     else {
                                         if(rd != 0) {
-                                            *(X+rd) = (uint32_t)- 1;
+                                            *(X+rd) = (int32_t)- 1;
                                         }
                                     }
                                 }
@@ -1925,7 +1925,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         }
                                         else {
                                             if(rd != 0) {
-                                                *(X+rd) = (uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2));
+                                                *(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2);
                                             }
                                         }
                                     }
@@ -1979,7 +1979,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     /* generate console output when executing the command */
                     auto mnemonic = fmt::format(
                         "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"),
-                        fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
+                        fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
                     this->core.disass_output(pc.val, mnemonic);
                 }
                 // used registers
@@ -1988,7 +1988,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(imm) {
-                                    *(X+rd +  8) = (uint32_t)(*(X+2) + imm);
+                                    *(X+rd +  8) = *(X+2) + imm;
                                 }
                                 else {
                                     raise(0,  2);
@@ -2012,10 +2012,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    uint32_t offs = (uint32_t)(*(X+rs1 +  8) + uimm);
-                    int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
+                    uint32_t load_address = *(X+rs1 +  8) + uimm;
+                    int32_t read_res = super::template read_mem<int32_t>(traits::MEM, load_address);
                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CLW;
-                    *(X+rd +  8) = (uint32_t)(int32_t)read_res;
+                    *(X+rd +  8) = (int32_t)read_res;
                 }
                 TRAP_CLW:break;
             }// @suppress("No break at end of case")
@@ -2035,8 +2035,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    uint32_t offs = (uint32_t)(*(X+rs1 +  8) + uimm);
-                    super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2 +  8));
+                    uint32_t load_address = *(X+rs1 +  8) + uimm;
+                    super::template write_mem<uint32_t>(traits::MEM, load_address, (int32_t)*(X+rs2 +  8));
                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CSW;
                 }
                 TRAP_CSW:break;
@@ -2061,7 +2061,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rs1 !=  0) {
-                                        *(X+rs1) = (uint32_t)(*(X+rs1) + (int8_t)sext<6>(imm));
+                                        *(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
                                     }
                                 }
                             }
@@ -2094,8 +2094,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    *(X+1) = (uint32_t)(*PC +  2);
-                    *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm));
+                    *(X+1) = *PC +  2;
+                    *NEXT_PC = *PC + (int16_t)sext<12>(imm);
                     this->core.reg.last_branch = 1;
                 }
                 TRAP_CJAL:break;
@@ -2120,7 +2120,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (uint32_t)((int8_t)sext<6>(imm));
+                                        *(X+rd) = (int8_t)sext<6>(imm);
                                     }
                                 }
                             }
@@ -2145,7 +2145,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         raise(0,  2);
                     }
                     if(rd !=  0) {
-                        *(X+rd) = (uint32_t)((int32_t)sext<18>(imm));
+                        *(X+rd) = (int32_t)sext<18>(imm);
                     }
                 }
                 TRAP_CLUI:break;
@@ -2165,7 +2165,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(nzimm) {
-                                    *(X+2) = (uint32_t)(*(X+2) + (int16_t)sext<10>(nzimm));
+                                    *(X+2) = *(X+2) + (int16_t)sext<10>(nzimm);
                                 }
                                 else {
                                     raise(0,  2);
@@ -2222,11 +2222,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                     if(shamt) {
-                        *(X+rs1 +  8) = (uint32_t)(((int32_t)*(X+rs1 +  8)) >> shamt);
+                        *(X+rs1 +  8) = ((int32_t)*(X+rs1 +  8)) >> shamt;
                     }
                     else {
                         if(traits::XLEN ==  128) {
-                            *(X+rs1 +  8) = (uint32_t)(((int32_t)*(X+rs1 +  8)) >>  64);
+                            *(X+rs1 +  8) = ((int32_t)*(X+rs1 +  8)) >>  64;
                         }
                     }
                 }
@@ -2247,7 +2247,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    *(X+rs1 +  8) = (uint32_t)(*(X+rs1 +  8) & (int8_t)sext<6>(imm));
+                    *(X+rs1 +  8) = *(X+rs1 +  8) & (int8_t)sext<6>(imm);
                 }
                 TRAP_CANDI:break;
             }// @suppress("No break at end of case")
@@ -2266,7 +2266,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                    *(X+rd +  8) = (uint32_t)(*(X+rd +  8) - *(X+rs2 +  8));
+                    *(X+rd +  8) = *(X+rd +  8) - *(X+rs2 +  8);
                 }
                 TRAP_CSUB:break;
             }// @suppress("No break at end of case")
@@ -2340,7 +2340,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 *NEXT_PC = *PC + 2;
                 // execute instruction
                 {
-                                *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm));
+                                *NEXT_PC = *PC + (int16_t)sext<12>(imm);
                                 this->core.reg.last_branch = 1;
                             }
                 TRAP_CJ:break;
@@ -2361,7 +2361,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(*(X+rs1 +  8) ==  0) {
-                                    *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm));
+                                    *NEXT_PC = *PC + (int16_t)sext<9>(imm);
                                     this->core.reg.last_branch = 1;
                                 }
                             }
@@ -2383,7 +2383,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                 // execute instruction
                 {
                                 if(*(X+rs1 +  8) !=  0) {
-                                    *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm));
+                                    *NEXT_PC = *PC + (int16_t)sext<9>(imm);
                                     this->core.reg.last_branch = 1;
                                 }
                             }
@@ -2434,10 +2434,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                         raise(0,  2);
                     }
                     else {
-                        uint32_t offs = (uint32_t)(*(X+2) + uimm);
-                        int32_t read_res = super::template read_mem<int32_t>(traits::MEM, offs);
+                        int32_t read_res = super::template read_mem<int32_t>(traits::MEM, *(X+2) + uimm);
                         if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CLWSP;
-                        *(X+rd) = (uint32_t)(int32_t)read_res;
+                        int32_t res = read_res;
+                        *(X+rd) = (int32_t)res;
                     }
                 }
                 TRAP_CLWSP:break;
@@ -2525,7 +2525,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     if(rd !=  0) {
-                                        *(X+rd) = (uint32_t)(*(X+rd) + *(X+rs2));
+                                        *(X+rd) = *(X+rd) + *(X+rs2);
                                     }
                                 }
                             }
@@ -2550,7 +2550,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                 }
                                 else {
                                     uint32_t new_pc = *(X+rs1);
-                                    *(X+1) = (uint32_t)(*PC +  2);
+                                    *(X+1) = *PC +  2;
                                     *NEXT_PC = new_pc & ~ 0x1;
                                     this->core.reg.last_branch = 1;
                                 }
@@ -2589,7 +2589,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                     raise(0,  2);
                                 }
                                 else {
-                                    uint32_t offs = (uint32_t)(*(X+2) + uimm);
+                                    uint32_t offs = *(X+2) + uimm;
                                     super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2));
                                     if(this->core.reg.trap_state>=0x80000000UL) goto TRAP_CSWSP;
                                 }
@@ -2651,24 +2651,15 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
 #include <iss/arch/riscv_hart_mu_p.h>
 namespace iss {
 namespace {
-std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
-		    auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
+volatile std::array<bool, 2> dummy = {
+        core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            arch::tgc_c* lcpu = new arch::riscv_hart_m_p<arch::tgc_c>();
+            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
         }),
-        core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
-		    auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+            arch::tgc_c* lcpu = new arch::riscv_hart_mu_p<arch::tgc_c>();
+            return {cpu_ptr{lcpu}, vm_ptr{interp::create(lcpu, gdb_port)}};
         })
 };
 }
 }
-extern "C" {
-	bool* get_tgc_c_interp_creators() {
-		return iss::dummy.data();
-	}
-}