fixes WFI miss of interrupt

.gitignore

@@ -30,6 +30,5 @@ language.settings.xml
 /.gdbinit
 /*.out
 /dump.json
-/src-gen/
 /*.yaml
 /*.json

CMakeLists.txt

@@ -8,6 +8,7 @@ include(GNUInstallDirs)
 
 find_package(elfio QUIET)
 find_package(Boost COMPONENTS coroutine)
+find_package(jsoncpp)
 
 if(WITH_LLVM)
     if(DEFINED ENV{LLVM_HOME})
@@ -29,32 +30,34 @@ endif()
 add_subdirectory(softfloat)
 
 # library files
-FILE(GLOB TGC_SOURCES    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp) 
-FILE(GLOB TGC_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp)
+FILE(GLOB GEN_SOURCES
+    ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
+	${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
+)
 
 set(LIB_SOURCES 
-    src/vm/fp_functions.cpp
-    src/plugin/instruction_count.cpp
-    
-    ${TGC_SOURCES}
-    ${TGC_VM_SOURCES}
+    src/iss/plugin/instruction_count.cpp
+	src/iss/arch/tgc_c.cpp
+	src/vm/interp/vm_tgc_c.cpp
+	src/vm/fp_functions.cpp
+    ${GEN_SOURCES}
 )
-if(TARGET RapidJSON)
-    list(APPEND LIB_SOURCES src/plugin/cycle_estimate.cpp src/plugin/pctrace.cpp)
+if(TARGET RapidJSON OR TARGET RapidJSON::RapidJSON)
+    list(APPEND LIB_SOURCES src/iss/plugin/cycle_estimate.cpp src/iss/plugin/pctrace.cpp)
 endif()
 
 if(WITH_LLVM)
-	FILE(GLOB TGC_LLVM_SOURCES
-	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/llvm/vm_*.cpp
+	FILE(GLOB LLVM_GEN_SOURCES
+	    ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp
 	)
-	list(APPEND LIB_SOURCES ${TGC_LLVM_SOURCES})
+	list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
 endif()
 
 if(WITH_TCC)
-	FILE(GLOB TGC_TCC_SOURCES
+	FILE(GLOB TCC_GEN_SOURCES
 	    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
 	)
-	list(APPEND LIB_SOURCES ${TGC_TCC_SOURCES})
+	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
 endif()
 
 # Define the library
@@ -69,16 +72,20 @@ if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
 elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
     target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
 endif()
-target_include_directories(${PROJECT_NAME} PUBLIC incl)
-target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp Boost::coroutine)
-if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
+target_include_directories(${PROJECT_NAME} PUBLIC src)
+target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
+target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util Boost::coroutine)
+if(TARGET jsoncpp::jsoncpp)
+	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp::jsoncpp)
+else()
+	target_link_libraries(${PROJECT_NAME} PUBLIC jsoncpp)
+endif()
+if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" AND BUILD_SHARED_LIBS)
     target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-rise-core -Wl,--no-whole-archive)
 else()
     target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-core)
 endif()
-if(TARGET CONAN_PKG::elfio)
-    target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
-elseif(TARGET elfio::elfio)
+if(TARGET elfio::elfio)
     target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio)
 else()
     message(FATAL_ERROR "No elfio library found, maybe a find_package() call is missing")
@@ -87,7 +94,9 @@ if(TARGET lz4::lz4)
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_LZ4)
     target_link_libraries(${PROJECT_NAME} PUBLIC lz4::lz4)
 endif()
-if(TARGET RapidJSON)
+if(TARGET RapidJSON::RapidJSON)
+    target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON::RapidJSON)
+elseif(TARGET RapidJSON)
     target_link_libraries(${PROJECT_NAME} PUBLIC RapidJSON)
 endif()
 
@@ -117,6 +126,7 @@ project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)
 
 add_executable(${PROJECT_NAME} src/main.cpp)
+FILE(GLOB TGC_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp) 
 foreach(F IN LISTS TGC_SOURCES)
     string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
     string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
@@ -168,7 +178,7 @@ if(SystemC_FOUND)
         target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
     endif()
     
-	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/core_complex.h)
+	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
     set_target_properties(${PROJECT_NAME} PROPERTIES
       VERSION ${PROJECT_VERSION}
       FRAMEWORK FALSE

gen_input/templates/CORENAME.cpp.gtl

@@ -37,9 +37,9 @@ def getRegisterSizes(){
     return regs
 }
 %>
+#include "${coreDef.name.toLowerCase()}.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>

gen_input/templates/CORENAME_decoder.cpp.gtl

@@ -0,0 +1,86 @@
+#include "${coreDef.name.toLowerCase()}.h"
+#include <vector>
+#include <array>
+#include <cstdlib>
+#include <algorithm>
+
+namespace iss {
+namespace arch {
+namespace {
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
+
+/****************************************************************************
+ * start opcode definitions
+ ****************************************************************************/
+struct instruction_desriptor {
+    size_t length;
+    uint32_t value;
+    uint32_t mask;
+    opcode_e op;
+};
+
+const std::array<instruction_desriptor, ${instructions.size}> instr_descr = {{
+     /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
+    {${instr.length}, ${instr.encoding}, ${instr.mask}, opcode_e::${instr.instruction.name}},<%}%>
+}};
+
+}
+
+template<>
+struct instruction_decoder<${coreDef.name.toLowerCase()}> {
+    using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e;
+    using code_word_t=traits<${coreDef.name.toLowerCase()}>::code_word_t;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    template<typename T>
+    unsigned decode_instruction(T);
+
+    instruction_decoder() {
+        for (auto instr : instr_descr) {
+            auto quadrant = instr.value & 0x3;
+            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+        }
+        for(auto& lut: qlut){
+            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+                return bit_count(a.mask) < bit_count(b.mask);
+            });
+        }
+    }
+};
+
+template<>
+unsigned instruction_decoder<${coreDef.name.toLowerCase()}>::decode_instruction<traits<${coreDef.name.toLowerCase()}>::code_word_t>(traits<${coreDef.name.toLowerCase()}>::code_word_t instr){
+    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
+        return !((instr&e.mask) ^ e.value );
+    });
+    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
+}
+
+
+std::unique_ptr<instruction_decoder<${coreDef.name.toLowerCase()}>> traits<${coreDef.name.toLowerCase()}>::get_decoder(){
+    return std::make_unique<instruction_decoder<${coreDef.name.toLowerCase()}>>();
+}
+
+}
+}

gen_input/templates/CORENAME_instr.yaml.gtl

@@ -12,5 +12,6 @@
 ${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
   - ${it.instruction.name}:
     encoding: ${it.encoding}
-    mask: ${it.mask}<%}}%>
+    mask: ${it.mask}<%if(it.attributes.size) {%>
+    attributes: ${it.attributes}<%}}}%>
 

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -36,11 +36,10 @@ def nativeTypeSize(int size){
     if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
 }
 %>
-#include "../fp_functions.h"
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/iss.h>
 #include <iss/interp/vm_base.h>
 #include <util/logging.h>
@@ -73,6 +72,7 @@ public:
     using addr_t      = typename super::addr_t;
     using reg_t       = typename traits::reg_t;
     using mem_type_e  = typename traits::mem_type_e;
+    using opcode_e    = typename traits::opcode_e;
     
     vm_impl();
 
@@ -137,44 +137,6 @@ protected:
     using coro_t = boost::coroutines2::coroutine<void>::pull_type;
     std::vector<coro_t> spawn_blocks;
 
-    template<typename T>
-    T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
-    inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint8_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint16_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint32_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
-        auto ret = super::template read_mem<uint64_t>(space, addr);
-        if(this->core.trap_state) throw 0;
-        return ret;
-    }
-    inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
-    inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
-        super::write_mem(space, addr, data);
-        if(this->core.trap_state) throw 0;
-    }
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
@@ -183,12 +145,15 @@ protected:
     }
     
     inline void process_spawn_blocks() {
+        if(spawn_blocks.size()==0) return;
+        std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
         for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
              if(*it){
                  (*it)();
                  ++it;
              } else
                  spawn_blocks.erase(it);
+        std::swap(super::ex_info.branch_taken, super::ex_info.hw_branch_taken);
     }
 <%functions.each{ it.eachLine { %>
     ${it}<%}%>
@@ -301,22 +266,21 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
             switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
             case arch::traits<ARCH>::opcode_e::${instr.name}: {
-		        <%instr.fields.eachLine{%>${it}
-		        <%}%>if(this->disass_enabled){
-		            /* generate console output when executing the command */
-		            <%instr.disass.eachLine{%>${it}
-		            <%}%>
-		        }
-		        // used registers<%instr.usedVariables.each{ k,v->
-		        if(v.isArray) {%>
-		        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
-		        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
-		        <%}}%>// calculate next pc value
-		        *NEXT_PC = *PC + ${instr.length/8};
-		        // execute instruction
-		        <%instr.behavior.eachLine{%>${it}
-		        <%}%>TRAP_${instr.name}:break;
-	    	}// @suppress("No break at end of case")<%}%>
+                <%instr.fields.eachLine{%>${it}
+                <%}%>if(this->disass_enabled){
+                    /* generate console output when executing the command */<%instr.disass.eachLine{%>
+                    ${it}<%}%>
+                }
+                // used registers<%instr.usedVariables.each{ k,v->
+                if(v.isArray) {%>
+                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
+                auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
+                <%}}%>// calculate next pc value
+                *NEXT_PC = *PC + ${instr.length/8};
+                // execute instruction<%instr.behavior.eachLine{%>
+                ${it}<%}%>
+                TRAP_${instr.name}:break;
+            }// @suppress("No break at end of case")<%}%>
             default: {
                 *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
                 raise(0,  2);
@@ -325,6 +289,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             // post execution stuff
             process_spawn_blocks();
             if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
+            // if(!this->core.trap_state) // update trap state if there is a pending interrupt
+            //    this->core.trap_state = this->core.pending_trap;
             // trap check
             if(trap_state!=0){
                 super::core.enter_trap(trap_state, pc.val, instr);

gen_input/templates/llvm/vm-vm_CORENAME.cpp.gtl

@@ -30,10 +30,10 @@
  *
  *******************************************************************************/
 
-#include <iss/arch/${coreDef.name.toLowerCase()}.h>
-#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
+#include <iss/arch/${coreDef.name.toLowerCase()}.h>
+#include <iss/arch/riscv_hart_m_p.h>
 #include <iss/iss.h>
 #include <iss/llvm/vm_base.h>
 #include <util/logging.h>

incl/iss/arch/.gitignore

@@ -1 +0,0 @@
-/tgc_*.h

src-gen/.gitignore

@@ -0,0 +1,2 @@
+/iss
+/vm

src/iss/arch/riscv_hart_m_p.h

@@ -182,7 +182,7 @@ public:
         return traits<BASE>::MISA_VAL&0b0100?~1:~3;
     }
 
-    riscv_hart_m_p();
+    riscv_hart_m_p(feature_config cfg = feature_config{});
     virtual ~riscv_hart_m_p() = default;
 
     void reset(uint64_t address) override;
@@ -194,9 +194,9 @@ public:
     iss::status write(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    virtual uint64_t leave_trap(uint64_t flags) override;
+    uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); }
+    uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
+    uint64_t leave_trap(uint64_t flags) override;
 
     const reg_t& get_mhartid() const { return mhartid_reg;	}
 	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
@@ -208,14 +208,6 @@ public:
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
 
-    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
-        mem_read_cb = memReadCb;
-    }
-
-    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
-        mem_write_cb = memWriteCb;
-    }
-
     void set_csr(unsigned addr, reg_t val){
         csr[addr & csr.page_addr_mask] = val;
     }
@@ -337,8 +329,6 @@ protected:
     }
 
     reg_t mhartid_reg{0x0};
-    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
-    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
 
     void check_interrupt();
     bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
@@ -346,23 +336,22 @@ protected:
     std::vector<std::function<mem_read_f>> memfn_read;
     std::vector<std::function<mem_write_f>> memfn_write;
     void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
-    uint64_t clic_base_addr{0};
-    unsigned clic_num_irq{0};
-    unsigned clic_num_trigger{0};
+    feature_config cfg;
     unsigned mcause_max_irq{16};
     inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
 };
 
 template <typename BASE, features_e FEAT>
-riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
+riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
 : state()
-, instr_if(*this) {
+, instr_if(*this)
+, cfg(cfg) {
     // reset values
     csr[misa] = traits<BASE>::MISA_VAL;
     csr[mvendorid] = 0x669;
     csr[marchid] = traits<BASE>::MARCHID_VAL;
     csr[mimpid] = 1;
-    csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file
+    csr[mclicbase] = cfg.clic_base; // TODO: should be taken from YAML file
 
     uart_buf.str("");
     for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
@@ -385,7 +374,10 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
+    const std::array<unsigned, 9> addrs{{
+    	misa, mvendorid, marchid, mimpid,
+    	mepc, mtvec, mscratch, mcause, mtval
+    }};
     for(auto addr: addrs) {
         csr_rd_cb[addr] = &this_class::read_csr_reg;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
@@ -436,29 +428,27 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
         csr_rd_cb[mclicbase] = &this_class::read_csr_reg;
         csr_wr_cb[mclicbase] = &this_class::write_null;
 
-        clic_base_addr=0xC0000000;
-        clic_num_irq=16;
-        clic_int_reg.resize(clic_num_irq);
+        clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
         clic_cfg_reg=0x20;
-        clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq;
-        mcause_max_irq=clic_num_irq+16;
-        insert_mem_range(clic_base_addr, 0x5000UL,
+        clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
+        mcause_max_irq=cfg.clic_num_irq+16;
+        insert_mem_range(cfg.clic_base, 0x5000UL,
                 [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
                 [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);});
     }
     if(FEAT & FEAT_TCM) {
-        tcm.resize(0x8000);
+        tcm.resize(cfg.tcm_size);
         std::function<mem_read_f> read_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t * const data) {
-            auto offset=addr.val-0x10000000;
+            auto offset=addr.val-this->cfg.tcm_base;
             std::copy(tcm.data() + offset, tcm.data() + offset + length, data);
             return iss::Ok;
         };
         std::function<mem_write_f> write_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {
-            auto offset=addr.val-0x10000000;
+            auto offset=addr.val-this->cfg.tcm_base;
             std::copy(data, data + length, tcm.data() + offset);
             return iss::Ok;
         };
-        insert_mem_range(0x10000000, 0x8000UL, read_clic_cb, write_clic_cb);
+        insert_mem_range(cfg.tcm_base, cfg.tcm_size, read_clic_cb, write_clic_cb);
     }
     if(FEAT & FEAT_DEBUG){
         csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
@@ -477,10 +467,10 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
     if (fp) {
         std::array<char, 5> buf;
         auto n = fread(buf.data(), 1, 4, fp);
+        fclose(fp);
         if (n != 4) throw std::runtime_error("input file has insufficient size");
         buf[4] = 0;
         if (strcmp(buf.data() + 1, "ELF") == 0) {
-            fclose(fp);
             // Create elfio reader
             ELFIO::elfio reader;
             // Load ELF data
@@ -571,18 +561,18 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
             if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
                 if (is_debug(access)) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
             try {
                 if(!is_debug(access) && (addr&(alignment-1))){
-                    this->trap_state = 1<<31 | 4<<16;
+                    this->trap_state = (1UL << 31) | 4<<16;
                     fault_data=addr;
                     return iss::Err;
                 }
                 auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
                 auto res = iss::Err;
-                if(!is_fetch(access) && memfn_range.size()){
+                if(access != access_type::FETCH && memfn_range.size()){
                     auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
                         return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
                     });
@@ -595,12 +585,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                     res = read_mem( phys_addr, length, data);
                 }
                 if (unlikely(res != iss::Ok)){
-                    this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                    this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -626,7 +616,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }
@@ -664,12 +654,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
             if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                 fault_data = addr;
                 if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
             try {
                 if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
-                    this->trap_state = 1<<31 | 6<<16;
+                    this->trap_state = (1UL << 31) | 6<<16;
                     fault_data=addr;
                     return iss::Err;
                 }
@@ -688,12 +678,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                     res = write_mem( phys_addr, length, data);
                 }
                 if (unlikely(res != iss::Ok)) {
-                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -753,7 +743,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }
@@ -863,7 +853,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
-    val = csr[mtvec] & ~2;
+    val = csr[addr] & ~2;
     return iss::Ok;
 }
 
@@ -879,7 +869,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
-    csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))| (mcause_max_irq-1));
+    csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1))| (mcause_max_irq-1));
     return iss::Ok;
 }
 
@@ -959,7 +949,6 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val
 
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
-    if(mem_read_cb) return mem_read_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x0200BFF8: { // CLINT base, mtime reg
         if (sizeof(reg_t) < length) return iss::Err;
@@ -984,14 +973,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned len
 
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if(mem_write_cb) return mem_write_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x10013000: // UART0 base, TXFIFO reg
     case 0x10023000: // UART1 base, TXFIFO reg
         uart_buf << (char)data[0];
         if (((char)data[0]) == '\n' || data[0] == 0) {
-            // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
-            // '"<<uart_buf.str()<<"'";
+            LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send '"<<uart_buf.str()<<"'";
             std::cout << uart_buf.str();
             uart_buf.str("");
         }
@@ -1062,15 +1049,15 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
 
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length, uint8_t *const data) {
-    if(addr==clic_base_addr) { // cliccfg
+    if(addr==cfg.clic_base) { // cliccfg
         *data=clic_cfg_reg;
         for(auto i=1; i<length; ++i) *(data+i)=0;
-    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+8)){ // clicinfo
+    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+8)){ // clicinfo
         read_reg_uint32(addr, clic_info_reg, data, length);
-    } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0x40+clic_num_trigger*4)){ // clicinttrig
+    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
-    } else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
+    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
         auto offset = ((addr&0x7fff)-0x1000)/4;
         read_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
     } else {
@@ -1081,17 +1068,18 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length
 
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
-    if(addr==clic_base_addr) { // cliccfg
+    if(addr==cfg.clic_base) { // cliccfg
         clic_cfg_reg = *data;
         clic_cfg_reg&= 0x7e;
-//    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
+//    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
 //        write_uint32(addr, clic_info_reg, data, length);
-    } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0xC0)){ // clicinttrig
+    } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
-    } else if(addr>=(clic_base_addr+0x1000) && (addr+length)<=(clic_base_addr+clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
+    } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
         auto offset = ((addr&0x7fff)-0x1000)/4;
         write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
+        clic_int_reg[offset].raw &= 0xf0c70101; // clicIntCtlBits->0xf0, clicintattr->0xc7, clicintie->0x1, clicintip->0x1
     }
     return iss::Ok;
 }
@@ -1109,8 +1097,8 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
     // any synchronous traps.
     auto ena_irq = csr[mip] & csr[mie];
 
-    bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie);
+    bool mstatus_mie = state.mstatus.MIE;
+    auto m_enabled = this->reg.PRIV < PRIV_M || mstatus_mie;
     auto enabled_interrupts = m_enabled ? ena_irq : 0;
 
     if (enabled_interrupts != 0) {
@@ -1210,6 +1198,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::l
     this->reg.NEXT_PC = csr[mepc] & get_pc_mask();
     CLOG(INFO, disass) << "Executing xRET";
     check_interrupt();
+    this->trap_state = this->pending_trap;
     return this->reg.NEXT_PC;
 }
 

src/iss/arch/riscv_hart_msu_vp.h

@@ -312,14 +312,6 @@ public:
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
 
-    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
-        mem_read_cb = memReadCb;
-    }
-
-    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
-        mem_write_cb = memWriteCb;
-    }
-
     void set_csr(unsigned addr, reg_t val){
         csr[addr & csr.page_addr_mask] = val;
     }
@@ -422,8 +414,6 @@ private:
     }
 
     reg_t mhartid_reg{0x0};
-    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
-    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
 
 protected:
     void check_interrupt();
@@ -1031,7 +1021,6 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_fcsr(unsigne
 
 template <typename BASE>
 iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
-    if(mem_read_cb) return mem_read_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x0200BFF8: { // CLINT base, mtime reg
         if (sizeof(reg_t) < length) return iss::Err;
@@ -1056,7 +1045,6 @@ iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length
 
 template <typename BASE>
 iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if(mem_write_cb) return mem_write_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x10013000: // UART0 base, TXFIFO reg
     case 0x10023000: // UART1 base, TXFIFO reg

src/iss/arch/riscv_hart_mu_p.h

@@ -223,14 +223,6 @@ public:
 
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
 
-    void setMemReadCb(std::function<iss::status(phys_addr_t, unsigned, uint8_t* const)> const& memReadCb) {
-        mem_read_cb = memReadCb;
-    }
-
-    void setMemWriteCb(std::function<iss::status(phys_addr_t, unsigned, const uint8_t* const)> const& memWriteCb) {
-        mem_write_cb = memWriteCb;
-    }
-
     void set_csr(unsigned addr, reg_t val){
         csr[addr & csr.page_addr_mask] = val;
     }
@@ -250,26 +242,24 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        virtual uint64_t get_pc() { return arch.get_pc(); };
+        uint64_t get_pc() override { return arch.reg.PC; };
 
-        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
+        uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
 
         uint64_t get_instr_word() override { return arch.instruction; }
 
-        uint64_t get_instr_count() { return arch.icount; }
+        uint64_t get_instr_count() override { return arch.icount; }
 
         uint64_t get_pendig_traps() override { return arch.trap_state; }
 
         uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
 
-        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
+        void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
 
         riscv_hart_mu_p<BASE, FEAT> &arch;
     };
 
     friend struct riscv_instrumentation_if;
-    addr_t get_pc() { return this->reg.PC; }
-    addr_t get_next_pc() { return this->reg.NEXT_PC; }
 
     virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
     virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
@@ -357,8 +347,6 @@ protected:
     }
 
     reg_t mhartid_reg{0x0};
-    std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
-    std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
 
     void check_interrupt();
     bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
@@ -487,7 +475,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         csr_rd_cb[mclicbase] = &this_class::read_csr_reg;
         csr_wr_cb[mclicbase] = &this_class::write_null;
 
-        clic_int_reg.resize(cfg.clic_num_irq);
+        clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
         clic_cfg_reg=0x20;
         clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
         mcause_max_irq=cfg.clic_num_irq+16;
@@ -526,10 +514,10 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
     if (fp) {
         std::array<char, 5> buf;
         auto n = fread(buf.data(), 1, 4, fp);
+        fclose(fp);
         if (n != 4) throw std::runtime_error("input file has insufficient size");
         buf[4] = 0;
         if (strcmp(buf.data() + 1, "ELF") == 0) {
-            fclose(fp);
             // Create elfio reader
             ELFIO::elfio reader;
             // Load ELF data
@@ -708,7 +696,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                 if(!pmp_check(access, addr, length) && !is_debug(access)) {
                     fault_data = addr;
                     if (is_debug(access)) throw trap_access(0, addr);
-                    this->trap_state = (1 << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
+                    this->trap_state = (1UL << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
                     return iss::Err;
                 }
             }
@@ -716,12 +704,12 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
             if (unlikely(is_fetch(access) && (addr&(alignment-1)))) {
                 fault_data = addr;
                 if (is_debug(access)) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
             try {
                 if(!is_debug(access)  && (addr&(alignment-1))){
-                    this->trap_state = 1<<31 | 4<<16;
+                    this->trap_state = (1UL << 31) | 4<<16;
                     fault_data=addr;
                     return iss::Err;
                 }
@@ -740,12 +728,12 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                     res = read_mem( phys_addr, length, data);
                 }
                 if (unlikely(res != iss::Ok)){
-                    this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
+                    this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -771,7 +759,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }
@@ -810,19 +798,19 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                 if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
                     fault_data = addr;
                     if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 1
+                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 1
                     return iss::Err;
                 }
             }
             if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
                 fault_data = addr;
                 if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
-                this->trap_state = (1 << 31); // issue trap 0
+                this->trap_state = (1UL << 31); // issue trap 0
                 return iss::Err;
             }
             try {
                 if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
-                    this->trap_state = 1<<31 | 6<<16;
+                    this->trap_state = (1UL << 31) | 6<<16;
                     fault_data=addr;
                     return iss::Err;
                 }
@@ -841,12 +829,12 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                     res = write_mem( phys_addr, length, data);
                 }
                 if (unlikely(res != iss::Ok)) {
-                    this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data=addr;
                 }
                 return res;
             } catch (trap_access &ta) {
-                this->trap_state = (1 << 31) | ta.id;
+                this->trap_state = (1UL << 31) | ta.id;
                 fault_data=ta.addr;
                 return iss::Err;
             }
@@ -906,7 +894,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
         }
         return iss::Ok;
     } catch (trap_access &ta) {
-        this->trap_state = (1 << 31) | ta.id;
+        this->trap_state = (1UL << 31) | ta.id;
         fault_data=ta.addr;
         return iss::Err;
     }
@@ -1020,14 +1008,12 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
     return iss::Ok;
 }
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_status(unsigned addr, reg_t &val) {
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    val = state.mstatus & hart_state_type::get_mask(req_priv_lvl);
+    val = state.mstatus & hart_state_type::get_mask((addr >> 8) & 0x3);
     return iss::Ok;
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_status(unsigned addr, reg_t val) {
-    auto req_priv_lvl = (addr >> 8) & 0x3;
-    state.write_mstatus(val, req_priv_lvl);
+    state.write_mstatus(val, (addr >> 8) & 0x3);
     check_interrupt();
     return iss::Ok;
 }
@@ -1129,7 +1115,6 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t va
 
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
-    if(mem_read_cb) return mem_read_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x0200BFF8: { // CLINT base, mtime reg
         if (sizeof(reg_t) < length) return iss::Err;
@@ -1154,7 +1139,6 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned le
 
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
-    if(mem_write_cb) return mem_write_cb(paddr, length, data);
     switch (paddr.val) {
     case 0x10013000: // UART0 base, TXFIFO reg
     case 0x10023000: // UART1 base, TXFIFO reg
@@ -1261,6 +1245,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned leng
     } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl
         auto offset = ((addr&0x7fff)-0x1000)/4;
         write_reg_uint32(addr, clic_int_reg[offset].raw, data, length);
+        clic_int_reg[offset].raw &= 0xf0c70101; // clicIntCtlBits->0xf0, clicintattr->0xc7, clicintie->0x1, clicintip->0x1
     }
     return iss::Ok;
 }
@@ -1278,8 +1263,8 @@ template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::chec
     // any synchronous traps.
     auto ena_irq = csr[mip] & csr[mie];
 
-    bool mie = state.mstatus.MIE;
-    auto m_enabled = this->reg.PRIV < PRIV_M ||  mie;
+    bool mstatus_mie = state.mstatus.MIE;
+    auto m_enabled = this->reg.PRIV < PRIV_M || mstatus_mie;
     auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0;
 
     if (enabled_interrupts != 0) {

src/iss/arch/tgc_c.cpp

@@ -30,9 +30,9 @@
  *
  *******************************************************************************/
 
+#include "tgc_c.h"
 #include "util/ities.h"
 #include <util/logging.h>
-#include <iss/arch/tgc_c.h>
 #include <cstdio>
 #include <cstring>
 #include <fstream>

src/iss/arch/tgc_c.h

@@ -53,7 +53,7 @@ template <> struct traits<tgc_c> {
     static constexpr std::array<const char*, 36> reg_aliases{
         {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
 
-    enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, RFS=32, INSTR_ALIGNMENT=2, XLEN=32, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
+    enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, INSTR_ALIGNMENT=2, RFS=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, CSR_SIZE=4096, MUL_LEN=64};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 
@@ -81,7 +81,7 @@ template <> struct traits<tgc_c> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, CSR, FENCE, RES };
+    enum mem_type_e { MEM, FENCE, RES, CSR };
     
     enum class opcode_e : unsigned short {
         LUI = 0,
@@ -124,56 +124,53 @@ template <> struct traits<tgc_c> {
         FENCE = 37,
         ECALL = 38,
         EBREAK = 39,
-        URET = 40,
-        SRET = 41,
-        MRET = 42,
-        WFI = 43,
-        DRET = 44,
-        CSRRW = 45,
-        CSRRS = 46,
-        CSRRC = 47,
-        CSRRWI = 48,
-        CSRRSI = 49,
-        CSRRCI = 50,
-        FENCE_I = 51,
-        MUL = 52,
-        MULH = 53,
-        MULHSU = 54,
-        MULHU = 55,
-        DIV = 56,
-        DIVU = 57,
-        REM = 58,
-        REMU = 59,
-        CADDI4SPN = 60,
-        CLW = 61,
-        CSW = 62,
-        CADDI = 63,
-        CNOP = 64,
-        CJAL = 65,
-        CLI = 66,
-        CLUI = 67,
-        CADDI16SP = 68,
-        __reserved_clui = 69,
-        CSRLI = 70,
-        CSRAI = 71,
-        CANDI = 72,
-        CSUB = 73,
-        CXOR = 74,
-        COR = 75,
-        CAND = 76,
-        CJ = 77,
-        CBEQZ = 78,
-        CBNEZ = 79,
-        CSLLI = 80,
-        CLWSP = 81,
-        CMV = 82,
-        CJR = 83,
-        __reserved_cmv = 84,
-        CADD = 85,
-        CJALR = 86,
-        CEBREAK = 87,
-        CSWSP = 88,
-        DII = 89,
+        MRET = 40,
+        WFI = 41,
+        CSRRW = 42,
+        CSRRS = 43,
+        CSRRC = 44,
+        CSRRWI = 45,
+        CSRRSI = 46,
+        CSRRCI = 47,
+        FENCE_I = 48,
+        MUL = 49,
+        MULH = 50,
+        MULHSU = 51,
+        MULHU = 52,
+        DIV = 53,
+        DIVU = 54,
+        REM = 55,
+        REMU = 56,
+        CADDI4SPN = 57,
+        CLW = 58,
+        CSW = 59,
+        CADDI = 60,
+        CNOP = 61,
+        CJAL = 62,
+        CLI = 63,
+        CLUI = 64,
+        CADDI16SP = 65,
+        __reserved_clui = 66,
+        CSRLI = 67,
+        CSRAI = 68,
+        CANDI = 69,
+        CSUB = 70,
+        CXOR = 71,
+        COR = 72,
+        CAND = 73,
+        CJ = 74,
+        CBEQZ = 75,
+        CBNEZ = 76,
+        CSLLI = 77,
+        CLWSP = 78,
+        CMV = 79,
+        CJR = 80,
+        __reserved_cmv = 81,
+        CADD = 82,
+        CJALR = 83,
+        CEBREAK = 84,
+        CSWSP = 85,
+        DII = 86,
         MAX_OPCODE
     };
 };

src/iss/arch/tgc_c_decoder.cpp

@@ -0,0 +1,175 @@
+#include "tgc_c.h"
+#include <vector>
+#include <array>
+#include <cstdlib>
+#include <algorithm>
+
+namespace iss {
+namespace arch {
+namespace {
+// according to
+// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation
+#ifdef __GCC__
+constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); }
+#elif __cplusplus < 201402L
+constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); }
+constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; }
+#else
+constexpr size_t bit_count(uint32_t u) {
+    size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111);
+    return ((uCount + (uCount >> 3)) & 030707070707) % 63;
+}
+#endif
+
+using opcode_e = traits<tgc_c>::opcode_e;
+
+/****************************************************************************
+ * start opcode definitions
+ ****************************************************************************/
+struct instruction_desriptor {
+    size_t length;
+    uint32_t value;
+    uint32_t mask;
+    opcode_e op;
+};
+
+const std::array<instruction_desriptor, 90> instr_descr = {{
+     /* entries are: size, valid value, valid mask, function ptr */
+    {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, opcode_e::LUI},
+    {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, opcode_e::AUIPC},
+    {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, opcode_e::JAL},
+    {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, opcode_e::JALR},
+    {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, opcode_e::BEQ},
+    {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, opcode_e::BNE},
+    {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, opcode_e::BLT},
+    {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, opcode_e::BGE},
+    {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, opcode_e::BLTU},
+    {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, opcode_e::BGEU},
+    {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, opcode_e::LB},
+    {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, opcode_e::LH},
+    {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, opcode_e::LW},
+    {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, opcode_e::LBU},
+    {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, opcode_e::LHU},
+    {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, opcode_e::SB},
+    {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, opcode_e::SH},
+    {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, opcode_e::SW},
+    {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, opcode_e::ADDI},
+    {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, opcode_e::SLTI},
+    {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, opcode_e::SLTIU},
+    {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, opcode_e::XORI},
+    {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, opcode_e::ORI},
+    {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, opcode_e::ANDI},
+    {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, opcode_e::SLLI},
+    {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRLI},
+    {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRAI},
+    {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::ADD},
+    {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::SUB},
+    {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::SLL},
+    {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::SLT},
+    {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::SLTU},
+    {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::XOR},
+    {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRL},
+    {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRA},
+    {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::OR},
+    {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::AND},
+    {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE},
+    {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, opcode_e::ECALL},
+    {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, opcode_e::EBREAK},
+    {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::URET},
+    {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::SRET},
+    {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::MRET},
+    {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, opcode_e::WFI},
+    {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::DRET},
+    {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRW},
+    {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRS},
+    {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRC},
+    {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRWI},
+    {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRSI},
+    {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRCI},
+    {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE_I},
+    {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::MUL},
+    {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::MULH},
+    {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::MULHSU},
+    {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::MULHU},
+    {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::DIV},
+    {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::DIVU},
+    {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::REM},
+    {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::REMU},
+    {16, 0b0000000000000000, 0b1110000000000011, opcode_e::CADDI4SPN},
+    {16, 0b0100000000000000, 0b1110000000000011, opcode_e::CLW},
+    {16, 0b1100000000000000, 0b1110000000000011, opcode_e::CSW},
+    {16, 0b0000000000000001, 0b1110000000000011, opcode_e::CADDI},
+    {16, 0b0000000000000001, 0b1110111110000011, opcode_e::CNOP},
+    {16, 0b0010000000000001, 0b1110000000000011, opcode_e::CJAL},
+    {16, 0b0100000000000001, 0b1110000000000011, opcode_e::CLI},
+    {16, 0b0110000000000001, 0b1110000000000011, opcode_e::CLUI},
+    {16, 0b0110000100000001, 0b1110111110000011, opcode_e::CADDI16SP},
+    {16, 0b0110000000000001, 0b1111000001111111, opcode_e::__reserved_clui},
+    {16, 0b1000000000000001, 0b1111110000000011, opcode_e::CSRLI},
+    {16, 0b1000010000000001, 0b1111110000000011, opcode_e::CSRAI},
+    {16, 0b1000100000000001, 0b1110110000000011, opcode_e::CANDI},
+    {16, 0b1000110000000001, 0b1111110001100011, opcode_e::CSUB},
+    {16, 0b1000110000100001, 0b1111110001100011, opcode_e::CXOR},
+    {16, 0b1000110001000001, 0b1111110001100011, opcode_e::COR},
+    {16, 0b1000110001100001, 0b1111110001100011, opcode_e::CAND},
+    {16, 0b1010000000000001, 0b1110000000000011, opcode_e::CJ},
+    {16, 0b1100000000000001, 0b1110000000000011, opcode_e::CBEQZ},
+    {16, 0b1110000000000001, 0b1110000000000011, opcode_e::CBNEZ},
+    {16, 0b0000000000000010, 0b1111000000000011, opcode_e::CSLLI},
+    {16, 0b0100000000000010, 0b1110000000000011, opcode_e::CLWSP},
+    {16, 0b1000000000000010, 0b1111000000000011, opcode_e::CMV},
+    {16, 0b1000000000000010, 0b1111000001111111, opcode_e::CJR},
+    {16, 0b1000000000000010, 0b1111111111111111, opcode_e::__reserved_cmv},
+    {16, 0b1001000000000010, 0b1111000000000011, opcode_e::CADD},
+    {16, 0b1001000000000010, 0b1111000001111111, opcode_e::CJALR},
+    {16, 0b1001000000000010, 0b1111111111111111, opcode_e::CEBREAK},
+    {16, 0b1100000000000010, 0b1110000000000011, opcode_e::CSWSP},
+    {16, 0b0000000000000000, 0b1111111111111111, opcode_e::DII},
+}};
+
+}
+
+template<>
+struct instruction_decoder<tgc_c> {
+    using opcode_e = traits<tgc_c>::opcode_e;
+    using code_word_t=traits<tgc_c>::code_word_t;
+
+    struct instruction_pattern {
+        uint32_t value;
+        uint32_t mask;
+        opcode_e id;
+    };
+
+    std::array<std::vector<instruction_pattern>, 4> qlut;
+
+    template<typename T>
+    unsigned decode_instruction(T);
+
+    instruction_decoder() {
+        for (auto instr : instr_descr) {
+            auto quadrant = instr.value & 0x3;
+            qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
+        }
+        for(auto& lut: qlut){
+            std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){
+                return bit_count(a.mask) > bit_count(b.mask);
+            });
+        }
+    }
+};
+
+template<>
+unsigned instruction_decoder<tgc_c>::decode_instruction<traits<tgc_c>::code_word_t>(traits<tgc_c>::code_word_t instr){
+    auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){
+        return !((instr&e.mask) ^ e.value );
+    });
+    return static_cast<unsigned>(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE);
+}
+
+
+std::unique_ptr<instruction_decoder<tgc_c>> traits<tgc_c>::get_decoder(){
+    return std::make_unique<instruction_decoder<tgc_c>>();
+}
+
+}
+}

src/iss/arch/tgc_mapper.h

@@ -4,39 +4,46 @@
 #include "riscv_hart_m_p.h"
 #include "tgc_c.h"
 using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
+#ifdef CORE_TGC_A
+#include "riscv_hart_m_p.h"
+#include <iss/arch/tgc_a.h>
+using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
+#endif
 #ifdef CORE_TGC_B
 #include "riscv_hart_m_p.h"
-#include "tgc_b.h"
+#include <iss/arch/tgc_b.h>
 using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
 #endif
 #ifdef CORE_TGC_C_XRB_NN
 #include "riscv_hart_m_p.h"
-#include "tgc_c_xrb_nn.h"
-using tgc_c_xrb_nn_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>;
+#include "hwl.h"
+#include <iss/arch/tgc_c_xrb_nn.h>
+using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
 #endif
 #ifdef CORE_TGC_D
 #include "riscv_hart_mu_p.h"
-#include "tgc_d.h"
+#include <iss/arch/tgc_d.h>
 using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
 #ifdef CORE_TGC_D_XRB_MAC
 #include "riscv_hart_mu_p.h"
-#include "tgc_d_xrb_mac.h"
+#include <iss/arch/tgc_d_xrb_mac.h>
 using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
 #ifdef CORE_TGC_D_XRB_NN
 #include "riscv_hart_mu_p.h"
-#include "tgc_d_xrb_nn.h"
-using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#include "hwl.h"
+#include <iss/arch/tgc_d_xrb_nn.h>
+using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
 #endif
 #ifdef CORE_TGC_E
 #include "riscv_hart_mu_p.h"
-#include "tgc_e.h"
+#include <iss/arch/tgc_e.h>
 using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
 #ifdef CORE_TGC_X
 #include "riscv_hart_mu_p.h"
-#include "tgc_x.h"
+#include <iss/arch/tgc_x.h>
 using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
 #endif
 

src/iss/debugger/riscv_target_adapter.h

@@ -85,7 +85,7 @@ public:
      corresponding bytes in avail_buf are 0, otherwise
      avail buf is 1 */
     status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
-                                std::vector<uint8_t> &avail_buf) override;
+            std::vector<uint8_t> &avail_buf) override;
 
     /* Write one register. buf is 4-byte aligned and it is in target byte
      order */
@@ -104,7 +104,7 @@ public:
     status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
 
     status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
-                             size_t &num, bool &done) override;
+            size_t &num, bool &done) override;
 
     status current_thread_query(rp_thread_ref &thread) override;
 
@@ -120,12 +120,12 @@ public:
 
     status packetsize_query(std::string &out_buf) override;
 
-    status add_break(int type, uint64_t addr, unsigned int length) override;
+    status add_break(break_type type, uint64_t addr, unsigned int length) override;
 
-    status remove_break(int type, uint64_t addr, unsigned int length) override;
+    status remove_break(break_type type, uint64_t addr, unsigned int length) override;
 
     status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
-                            std::function<void(unsigned)> stop_callback) override;
+            std::function<void(unsigned)> stop_callback) override;
 
     status target_xml_query(std::string &out_buf) override;
 
@@ -159,8 +159,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_t
  */
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
-                                                     std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
-                                                     bool &done) {
+        std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
+        bool &done) {
     if (first == 0) {
         result.clear();
         result.push_back(thread_idx);
@@ -193,20 +193,20 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
         }
     }
     // work around fill with F type registers
-//    if (arch::traits<ARCH>::NUM_REGS < 65) {
-//        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
-//        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
-//            for (size_t j = 0; j < reg_width; ++j) {
-//                data.push_back(0x0);
-//                avail.push_back(0x00);
-//            }
-//            // if(arch::traits<ARCH>::XLEN < 64)
-//            //     for(unsigned j=0; j<4; ++j){
-//            //         data.push_back(0x0);
-//            //         avail.push_back(0x00);
-//            //     }
-//        }
-//    }
+    //    if (arch::traits<ARCH>::NUM_REGS < 65) {
+    //        auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
+    //        for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
+    //            for (size_t j = 0; j < reg_width; ++j) {
+    //                data.push_back(0x0);
+    //                avail.push_back(0x00);
+    //            }
+    //            // if(arch::traits<ARCH>::XLEN < 64)
+    //            //     for(unsigned j=0; j<4; ++j){
+    //            //         data.push_back(0x0);
+    //            //         avail.push_back(0x00);
+    //            //     }
+    //        }
+    //    }
     return Ok;
 }
 
@@ -240,7 +240,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(cons
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
-                                                        std::vector<uint8_t> &avail) {
+        std::vector<uint8_t> &avail) {
     if (reg_no < 65) {
         // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
         // arch::traits<ARCH>::reg_e>(reg_no))/8;
@@ -331,34 +331,48 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std
     return Ok;
 }
 
-template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
-    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
-    auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
-    target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
-    LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
-               << saddr.val << std::dec;
-    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-    return Ok;
-}
-
-template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
-    auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
-    unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
-    if (handle) {
-        LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
-                   << std::dec;
-        // TODO: check length of addr range
-        target_adapter_base::bp_lut.removeEntry(handle);
+template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
+        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+        auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
+        target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
+        LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
+                << saddr.val << std::dec;
         LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
-    LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
-    return Err;
+    }
+}
+
+template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_type type, uint64_t addr, unsigned int length) {
+    switch(type) {
+    default:
+        return Err;
+    case SW_EXEC:
+    case HW_EXEC: {
+        auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
+        unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
+        if (handle) {
+            LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
+                    << std::dec;
+            // TODO: check length of addr range
+            target_adapter_base::bp_lut.removeEntry(handle);
+            LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+            return Ok;
+        }
+        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        return Err;
+    }
+    }
 }
 
 template <typename ARCH>
 status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
-                                                    std::function<void(unsigned)> stop_callback) {
+        std::function<void(unsigned)> stop_callback) {
     auto *reg_base = core->get_regs_base_ptr();
     auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
     auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
@@ -369,42 +383,42 @@ status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
     const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
-                          "<target><architecture>riscv:rv32</architecture>"
-                          //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
-                          //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
-                          //"  </feature>\n"
-                          "</target>"};
+        "<target><architecture>riscv:rv32</architecture>"
+        //"  <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
+        //"    <reg name=\"x0\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x1\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x2\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x3\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x4\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x5\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x6\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x7\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x8\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x9\"  bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
+        //"    <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
+        //"  </feature>\n"
+        "</target>"};
     out_buf = res;
     return Ok;
 }

src/iss/plugin/cycle_estimate.cpp

@@ -32,14 +32,14 @@
  *       eyck@minres.com - initial API and implementation
  ******************************************************************************/
 
-#include "iss/plugin/cycle_estimate.h"
+#include "cycle_estimate.h"
 
 #include <iss/arch_if.h>
 #include <util/logging.h>
 #include <rapidjson/document.h>
 #include <rapidjson/istreamwrapper.h>
-#include "rapidjson/writer.h"
-#include "rapidjson/stringbuffer.h"
+#include <rapidjson/writer.h>
+#include <rapidjson/stringbuffer.h>
 #include <rapidjson/ostreamwrapper.h>
 #include <rapidjson/error/en.h>
 #include <fstream>

src/iss/plugin/cycle_estimate.h

@@ -45,7 +45,7 @@ namespace iss {
 
 namespace plugin {
 
-class cycle_estimate: public iss::vm_plugin {
+class cycle_estimate: public vm_plugin {
 	BEGIN_BF_DECL(instr_desc, uint32_t)
 		BF_FIELD(taken, 24, 8)
 		BF_FIELD(not_taken, 16, 8)

src/iss/plugin/instruction_count.cpp

@@ -32,8 +32,8 @@
  *       eyck@minres.com - initial API and implementation
  ******************************************************************************/
 
-#include "iss/plugin/instruction_count.h"
-#include "iss/instrumentation_if.h"
+#include "instruction_count.h"
+#include <iss/instrumentation_if.h>
 
 #include <iss/arch_if.h>
 #include <util/logging.h>

src/iss/plugin/pctrace.cpp

@@ -4,8 +4,8 @@
 #include <util/ities.h>
 #include <rapidjson/document.h>
 #include <rapidjson/istreamwrapper.h>
-#include "rapidjson/writer.h"
-#include "rapidjson/stringbuffer.h"
+#include <rapidjson/writer.h>
+#include <rapidjson/stringbuffer.h>
 #include <rapidjson/ostreamwrapper.h>
 #include <rapidjson/error/en.h>
 #include <fstream>
@@ -89,7 +89,7 @@ private:
 };
 #endif
 
-cov::cov(std::string const &filename)
+pctrace::pctrace(std::string const &filename)
 : instr_if(nullptr)
 , filename(filename)
 , output("output.trc")
@@ -99,9 +99,9 @@ cov::cov(std::string const &filename)
 #endif
 { }
 
-cov::~cov() { }
+pctrace::~pctrace() { }
 
-bool cov::registration(const char *const version, vm_if& vm) {
+bool pctrace::registration(const char *const version, vm_if& vm) {
     instr_if = vm.get_arch()->get_instrumentation_if();
     if(!instr_if) return false;
     const string  core_name = instr_if->core_type_name();
@@ -152,7 +152,7 @@ bool cov::registration(const char *const version, vm_if& vm) {
     return true;
 }
 
-void cov::callback(instr_info_t iinfo, const exec_info& einfo) {
+void pctrace::callback(instr_info_t iinfo, const exec_info& einfo) {
     auto delay = 0;
     size_t id = iinfo.instr_id;
     auto entry = delays[id];

src/iss/plugin/pctrace.h

@@ -45,7 +45,7 @@
 namespace iss {
 namespace plugin {
 class lz4compress_steambuf;
-class cov : public iss::vm_plugin {
+class pctrace : public iss::vm_plugin {
     struct instr_delay {
         std::string instr_name;
         size_t size;
@@ -67,17 +67,17 @@ class cov : public iss::vm_plugin {
 
 public:
 
-    cov(const cov &) = delete;
+    pctrace(const pctrace &) = delete;
 
-    cov(const cov &&) = delete;
+    pctrace(const pctrace &&) = delete;
 
-    cov(std::string const &);
+    pctrace(std::string const &);
 
-    virtual ~cov();
+    virtual ~pctrace();
 
-    cov &operator=(const cov &) = delete;
+    pctrace &operator=(const pctrace &) = delete;
 
-    cov &operator=(const cov &&) = delete;
+    pctrace &operator=(const pctrace &&) = delete;
 
     bool registration(const char *const version, vm_if &arch) override;
 

src/main.cpp

@@ -1,236 +1,241 @@
-/*******************************************************************************
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *******************************************************************************/
-
-#include <iostream>
-#include <iss/factory.h>
-
-#include <boost/lexical_cast.hpp>
-#include <boost/program_options.hpp>
-#include <iss/arch/tgc_mapper.h>
-#ifdef WITH_LLVM
-#include <iss/llvm/jit_helper.h>
-#endif
-#include <iss/log_categories.h>
-#include <iss/plugin/cycle_estimate.h>
-#include <iss/plugin/instruction_count.h>
-#include <iss/plugin/pctrace.h>
-#include <iss/plugin/loader.h>
-#if defined(HAS_LUA)
-#include <iss/plugin/lua.h>
-#endif
-
-namespace po = boost::program_options;
-
-int main(int argc, char *argv[]) {
-    /*
-     *  Define and parse the program options
-     */
-    po::variables_map clim;
-    po::options_description desc("Options");
-    // clang-format off
-    desc.add_options()
-        ("help,h", "Print help message")
-        ("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
-        ("logfile,l", po::value<std::string>(), "Sets default log file.")
-        ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
-        ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
-        ("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
-        ("reset,r", po::value<std::string>(), "reset address")
-        ("dump-ir", "dump the intermediate representation")
-        ("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
-        ("mem,m", po::value<std::string>(), "the memory input file")
-        ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
-        ("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
-        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
-    // clang-format on
-    auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
-    try {
-        po::store(parsed, clim); // can throw
-        // --help option
-        if (clim.count("help")) {
-            std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
-            return 0;
-        }
-        po::notify(clim); // throws on error, so do after help in case
-    } catch (po::error &e) {
-        // there are problems
-        std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
-        std::cerr << desc << std::endl;
-        return 1;
-    }
-    std::vector<std::string> args = collect_unrecognized(parsed.options, po::include_positional);
-
-    LOGGER(DEFAULT)::print_time() = false;
-    LOGGER(connection)::print_time() = false;
-    if (clim.count("verbose")) {
-        auto l = logging::as_log_level(clim["verbose"].as<int>());
-        LOGGER(DEFAULT)::reporting_level() = l;
-        LOGGER(connection)::reporting_level() = l;
-    }
-    if (clim.count("logfile")) {
-        // configure the connection logger
-        auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
-        LOG_OUTPUT(DEFAULT)::stream() = f;
-        LOG_OUTPUT(connection)::stream() = f;
-    }
-
-    std::vector<iss::vm_plugin *> plugin_list;
-    auto res = 0;
-    try {
-#ifdef WITH_LLVM
-        // application code comes here //
-        iss::init_jit_debug(argc, argv);
-#endif
-        bool dump = clim.count("dump-ir");
-        // instantiate the simulator
-        iss::vm_ptr vm{nullptr};
-        iss::cpu_ptr cpu{nullptr};
-        std::string isa_opt(clim["isa"].as<std::string>());
-        if (isa_opt == "tgc_c") {
-            std::tie(cpu, vm) =
-                iss::create_cpu<tgc_c_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#ifdef CORE_TGC_B
-        if (isa_opt == "tgc_b") {
-            std::tie(cpu, vm) =
-                iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#endif
-#ifdef CORE_TGC_C_XRB_NN
-        if (isa_opt == "tgc_c_xrb_nn") {
-            std::tie(cpu, vm) =
-                iss::create_cpu<tgc_c_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#endif
-#ifdef CORE_TGC_D
-        if (isa_opt == "tgc_d") {
-            std::tie(cpu, vm) =
-                iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#endif
-#ifdef CORE_TGC_D_XRB_MAC
-        if (isa_opt == "tgc_d_xrb_mac") {
-            std::tie(cpu, vm) =
-                iss::create_cpu<tgc_d_xrb_mac_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#endif
-#ifdef CORE_TGC_D_XRB_NN
-        if (isa_opt == "tgc_d_xrb_nn") {
-            std::tie(cpu, vm) =
-                iss::create_cpu<tgc_d_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#endif
-#ifdef CORE_TGC_E
-        if (isa_opt == "tgc_e") {
-            std::tie(cpu, vm) =
-                iss::create_cpu<tgc_e_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
-        } else
-#endif
-        {
+/*******************************************************************************
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#include <iostream>
+#include "iss/factory.h"
+
+#include <boost/lexical_cast.hpp>
+#include <boost/program_options.hpp>
+#include "iss/arch/tgc_mapper.h"
+#ifdef WITH_LLVM
+#include <iss/llvm/jit_helper.h>
+#endif
+#include <iss/log_categories.h>
+#include "iss/plugin/cycle_estimate.h"
+#include "iss/plugin/instruction_count.h"
+#include "iss/plugin/pctrace.h"
+#ifndef WIN32
+#include <iss/plugin/loader.h>
+#endif
+#if defined(HAS_LUA)
+#include <iss/plugin/lua.h>
+#endif
+
+namespace po = boost::program_options;
+
+int main(int argc, char *argv[]) {
+    /*
+     *  Define and parse the program options
+     */
+    po::variables_map clim;
+    po::options_description desc("Options");
+    // clang-format off
+    desc.add_options()
+        ("help,h", "Print help message")
+        ("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
+        ("logfile,l", po::value<std::string>(), "Sets default log file.")
+        ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
+        ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
+        ("instructions,i", po::value<uint64_t>()->default_value(std::numeric_limits<uint64_t>::max()), "max. number of instructions to simulate")
+        ("reset,r", po::value<std::string>(), "reset address")
+        ("dump-ir", "dump the intermediate representation")
+        ("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
+        ("mem,m", po::value<std::string>(), "the memory input file")
+        ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
+        ("backend", po::value<std::string>()->default_value("interp"), "the memory input file")
+        ("isa", po::value<std::string>()->default_value("tgc_c"), "isa to use for simulation");
+    // clang-format on
+    auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
+    try {
+        po::store(parsed, clim); // can throw
+        // --help option
+        if (clim.count("help")) {
+            std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
+            return 0;
+        }
+        po::notify(clim); // throws on error, so do after help in case
+    } catch (po::error &e) {
+        // there are problems
+        std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
+        std::cerr << desc << std::endl;
+        return 1;
+    }
+    std::vector<std::string> args = collect_unrecognized(parsed.options, po::include_positional);
+
+    LOGGER(DEFAULT)::print_time() = false;
+    LOGGER(connection)::print_time() = false;
+    if (clim.count("verbose")) {
+        auto l = logging::as_log_level(clim["verbose"].as<int>());
+        LOGGER(DEFAULT)::reporting_level() = l;
+        LOGGER(connection)::reporting_level() = l;
+    }
+    if (clim.count("logfile")) {
+        // configure the connection logger
+        auto f = fopen(clim["logfile"].as<std::string>().c_str(), "w");
+        LOG_OUTPUT(DEFAULT)::stream() = f;
+        LOG_OUTPUT(connection)::stream() = f;
+    }
+
+    std::vector<iss::vm_plugin *> plugin_list;
+    auto res = 0;
+    try {
+#ifdef WITH_LLVM
+        // application code comes here //
+        iss::init_jit_debug(argc, argv);
+#endif
+        bool dump = clim.count("dump-ir");
+        // instantiate the simulator
+        iss::vm_ptr vm{nullptr};
+        iss::cpu_ptr cpu{nullptr};
+        std::string isa_opt(clim["isa"].as<std::string>());
+        if (isa_opt == "tgc_c") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_c_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#ifdef CORE_TGC_B
+        if (isa_opt == "tgc_b") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_b_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_C_XRB_NN
+        if (isa_opt == "tgc_c_xrb_nn") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_c_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_D
+        if (isa_opt == "tgc_d") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_D_XRB_MAC
+        if (isa_opt == "tgc_d_xrb_mac") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_xrb_mac_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_D_XRB_NN
+        if (isa_opt == "tgc_d_xrb_nn") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_E
+        if (isa_opt == "tgc_e") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_e_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+        {
             LOG(ERR) << "Illegal argument value for '--isa': " << isa_opt << std::endl;
-            return 127;
-        }
-        if (clim.count("plugin")) {
-            for (std::string const& opt_val : clim["plugin"].as<std::vector<std::string>>()) {
-                std::string plugin_name=opt_val;
-                std::string filename{"cycles.txt"};
-                std::size_t found = opt_val.find('=');
-                if (found != std::string::npos) {
-                    plugin_name = opt_val.substr(0, found);
-                    filename = opt_val.substr(found + 1, opt_val.size());
-                }
-                if (plugin_name == "ic") {
-                    auto *ic_plugin = new iss::plugin::instruction_count(filename);
-                    vm->register_plugin(*ic_plugin);
-                    plugin_list.push_back(ic_plugin);
-                } else if (plugin_name == "ce") {
-                    auto *ce_plugin = new iss::plugin::cycle_estimate(filename);
-                    vm->register_plugin(*ce_plugin);
-                    plugin_list.push_back(ce_plugin);
-                } else if (plugin_name == "pctrace") {
-                    auto *plugin = new iss::plugin::cov(filename);
-                    vm->register_plugin(*plugin);
-                    plugin_list.push_back(plugin);
-               } else {
-                    std::array<char const*, 1> a{{filename.c_str()}};
-                    iss::plugin::loader l(plugin_name, {{"initPlugin"}});
-                    auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
-                    if(plugin){
-                        vm->register_plugin(*plugin);
-                        plugin_list.push_back(plugin);
-                    } else {
+            return 127;
+        }
+        if (clim.count("plugin")) {
+            for (std::string const& opt_val : clim["plugin"].as<std::vector<std::string>>()) {
+                std::string plugin_name=opt_val;
+                std::string filename{"cycles.txt"};
+                std::size_t found = opt_val.find('=');
+                if (found != std::string::npos) {
+                    plugin_name = opt_val.substr(0, found);
+                    filename = opt_val.substr(found + 1, opt_val.size());
+                }
+                if (plugin_name == "ic") {
+                    auto *ic_plugin = new iss::plugin::instruction_count(filename);
+                    vm->register_plugin(*ic_plugin);
+                    plugin_list.push_back(ic_plugin);
+                } else if (plugin_name == "ce") {
+                    auto *ce_plugin = new iss::plugin::cycle_estimate(filename);
+                    vm->register_plugin(*ce_plugin);
+                    plugin_list.push_back(ce_plugin);
+                } else if (plugin_name == "pctrace") {
+                    auto *plugin = new iss::plugin::pctrace(filename);
+                    vm->register_plugin(*plugin);
+                    plugin_list.push_back(plugin);
+               } else {
+#ifndef WIN32
+                    std::array<char const*, 1> a{{filename.c_str()}};
+                    iss::plugin::loader l(plugin_name, {{"initPlugin"}});
+                    auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
+                    if(plugin){
+                        vm->register_plugin(*plugin);
+                        plugin_list.push_back(plugin);
+                    } else
+#endif
+                    {
                         LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
-                        return 127;
-                    }
-                }
-            }
-        }
-        if (clim.count("disass")) {
-            vm->setDisassEnabled(true);
-            LOGGER(disass)::reporting_level() = logging::INFO;
-            LOGGER(disass)::print_time() = false;
-            auto file_name = clim["disass"].as<std::string>();
-            if (file_name.length() > 0) {
-                LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
-                LOGGER(disass)::print_severity() = false;
-            }
-        }
-        uint64_t start_address = 0;
-        if (clim.count("mem"))
-            vm->get_arch()->load_file(clim["mem"].as<std::string>());
-        if (clim.count("elf"))
-            for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
-                auto start_addr = vm->get_arch()->load_file(input);
-                if (start_addr.second) start_address = start_addr.first;
-            }
-        for (std::string input : args) {
-            auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
-            if (start_addr.second) start_address = start_addr.first;
-        }
-        if (clim.count("reset")) {
-            auto str = clim["reset"].as<std::string>();
-            start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10);
-        }
-        vm->reset(start_address);
-        auto cycles = clim["instructions"].as<uint64_t>();
-        res = vm->start(cycles, dump);
-    } catch (std::exception &e) {
+                        return 127;
+                    }
+                }
+            }
+        }
+        if (clim.count("disass")) {
+            vm->setDisassEnabled(true);
+            LOGGER(disass)::reporting_level() = logging::INFO;
+            LOGGER(disass)::print_time() = false;
+            auto file_name = clim["disass"].as<std::string>();
+            if (file_name.length() > 0) {
+                LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
+                LOGGER(disass)::print_severity() = false;
+            }
+        }
+        uint64_t start_address = 0;
+        if (clim.count("mem"))
+            vm->get_arch()->load_file(clim["mem"].as<std::string>());
+        if (clim.count("elf"))
+            for (std::string input : clim["elf"].as<std::vector<std::string>>()) {
+                auto start_addr = vm->get_arch()->load_file(input);
+                if (start_addr.second) start_address = start_addr.first;
+            }
+        for (std::string input : args) {
+            auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
+            if (start_addr.second) start_address = start_addr.first;
+        }
+        if (clim.count("reset")) {
+            auto str = clim["reset"].as<std::string>();
+            start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10);
+        }
+        vm->reset(start_address);
+        auto cycles = clim["instructions"].as<uint64_t>();
+        res = vm->start(cycles, dump);
+    } catch (std::exception &e) {
         LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
-                   << std::endl;
-        res = 2;
-    }
-    // cleanup to let plugins report of needed
-    for (auto *p : plugin_list) {
-        delete p;
-    }
-    return res;
-}
+                   << std::endl;
+        res = 2;
+    }
+    // cleanup to let plugins report of needed
+    for (auto *p : plugin_list) {
+        delete p;
+    }
+    return res;
+}

src/sysc/core_complex.cpp

@@ -30,15 +30,17 @@
  *
  *******************************************************************************/
 
-// clang-format off
-#include <iss/debugger/gdb_session.h>
-#include <iss/debugger/encoderdecoder.h>
-#include <iss/debugger/server.h>
-#include <iss/debugger/target_adapter_if.h>
-#include <iss/iss.h>
+// clang-format off
+#include <iss/debugger/gdb_session.h>
+#include <iss/debugger/encoderdecoder.h>
+#include <iss/debugger/server.h>
+#include <iss/debugger/target_adapter_if.h>
+#include <iss/iss.h>
 #include <iss/vm_types.h>
-#include <iss/plugin/loader.h>
-#include <sysc/core_complex.h>
+#ifndef WIN32
+#include <iss/plugin/loader.h>
+#endif
+#include "core_complex.h"
 #include <iss/arch/tgc_mapper.h>
 #include <scc/report.h>
 #include <util/ities.h>
@@ -49,7 +51,7 @@
 #include <iss/plugin/instruction_count.h>
 #include <iss/plugin/pctrace.h>
 
-// clang-format on
+// clang-format on
 
 #define STR(X) #X
 #define CREATE_CORE(CN) \
@@ -68,12 +70,12 @@ using namespace scv_tr;
 #define GET_PROP_VALUE(P) P.getValue()
 #endif
 
-#ifdef _MSC_VER
-// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
-#define strncasecmp _strnicmp
-#define strcasecmp _stricmp
-#endif
-
+#ifdef _MSC_VER
+// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
+#define strncasecmp _strnicmp
+#define strcasecmp _stricmp
+#endif
+
 namespace sysc {
 namespace tgfs {
 using namespace std;
@@ -184,17 +186,17 @@ public:
     void local_irq(short id, bool value) {
         reg_t mask = 0;
         switch (id) {
-        case 16: // SW
+        case 3: // SW
             mask = 1 << 3;
             break;
-        case 17: // timer
+        case 7: // timer
             mask = 1 << 7;
             break;
-        case 18: // external
+        case 11: // external
             mask = 1 << 11;
             break;
         default:
-            /* do nothing*/
+            if(id>15) mask = 1 << id;
             break;
         }
         if (value) {
@@ -296,7 +298,7 @@ public:
         CREATE_CORE(tgc_d_xrb_nn)
 #endif
         {
-            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
+            LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
         }
         auto *srv = debugger::server<debugger::gdb_session>::get();
         if (srv) tgt_adapter = srv->get_target();
@@ -355,8 +357,11 @@ void core_complex::init(){
     sensitive << sw_irq_i;
     SC_METHOD(timer_irq_cb);
     sensitive << timer_irq_i;
-    SC_METHOD(global_irq_cb);
-    sensitive << global_irq_i;
+    SC_METHOD(ext_irq_cb);
+    sensitive << ext_irq_i;
+    SC_METHOD(local_irq_cb);
+    for(auto pin:local_irq_i)
+        sensitive << pin;
     trc->m_db=scv_tr_db::get_default_db();
 
 	SC_METHOD(forward);
@@ -405,10 +410,11 @@ void core_complex::before_end_of_elaboration() {
                 cpu->vm->register_plugin(*plugin);
                 plugin_list.push_back(plugin);
             } else if (plugin_name == "pctrace") {
-                auto *plugin = new iss::plugin::cov(filename);
+                auto *plugin = new iss::plugin::pctrace(filename);
                 cpu->vm->register_plugin(*plugin);
                 plugin_list.push_back(plugin);
             } else {
+#ifndef WIN32
                 std::array<char const*, 1> a{{filename.c_str()}};
                 iss::plugin::loader l(plugin_name, {{"initPlugin"}});
                 auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
@@ -416,6 +422,7 @@ void core_complex::before_end_of_elaboration() {
                     cpu->vm->register_plugin(*plugin);
                     plugin_list.push_back(plugin);
                 } else
+#endif
                     SCCERR(SCMOD) << "Unknown plugin '" << plugin_name << "' or plugin not found";
             }
         }
@@ -476,11 +483,19 @@ void core_complex::rst_cb() {
     if (rst_i.read()) cpu->set_interrupt_execution(true);
 }
 
-void core_complex::sw_irq_cb() { cpu->local_irq(16, sw_irq_i.read()); }
+void core_complex::sw_irq_cb() { cpu->local_irq(3, sw_irq_i.read()); }
 
-void core_complex::timer_irq_cb() { cpu->local_irq(17, timer_irq_i.read()); }
+void core_complex::timer_irq_cb() { cpu->local_irq(7, timer_irq_i.read()); }
 
-void core_complex::global_irq_cb() { cpu->local_irq(18, global_irq_i.read()); }
+void core_complex::ext_irq_cb() { cpu->local_irq(11, ext_irq_i.read()); }
+
+void core_complex::local_irq_cb() {
+    for(auto i=0U; i<local_irq_i.size(); ++i) {
+        if(local_irq_i[i].event()) {
+            cpu->local_irq(16+i, local_irq_i[i].read());
+        }
+    }
+}
 
 void core_complex::run() {
     wait(SC_ZERO_TIME); // separate from elaboration phase

src/sysc/core_complex.h

@@ -69,11 +69,11 @@ struct core_trace;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
+    tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<32>> initiator{"intor"};
 
     sc_core::sc_in<bool> rst_i{"rst_i"};
 
-    sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
+    sc_core::sc_in<bool> ext_irq_i{"ext_irq_i"};
 
     sc_core::sc_in<bool> timer_irq_i{"timer_irq_i"};
 
@@ -84,7 +84,7 @@ public:
 #ifndef CWR_SYSTEMC
 	sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 
-    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
+    sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o{"mtime_o"};
 
     cci::cci_param<std::string> elf_file{"elf_file", ""};
 
@@ -181,7 +181,8 @@ protected:
     void rst_cb();
     void sw_irq_cb();
     void timer_irq_cb();
-    void global_irq_cb();
+    void ext_irq_cb();
+    void local_irq_cb();
     uint64_t last_sync_cycle = 0;
     util::range_lut<tlm_dmi_ext> read_lut, write_lut;
     tlm_utils::tlm_quantumkeeper quantum_keeper;

src/vm/interp/.gitignore

@@ -1 +0,0 @@
-/vm_tgc_*.cpp

src/vm/llvm/vm_tgc_c.cpp

@@ -30,7 +30,7 @@
  *
  *******************************************************************************/
 
-#include <iss/arch/tgf_c.h>
+#include <iss/arch/tgc_c.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -52,7 +52,7 @@ namespace fp_impl {
 void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
 }
 
-namespace tgf_c {
+namespace tgc_c {
 using namespace ::llvm;
 using namespace iss::arch;
 using namespace iss::debugger;
@@ -4151,11 +4151,11 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *b
                           bb, this->trap_blk, 1);
 }
 
-} // namespace tgf_c
+} // namespace tgc_c
 
 template <>
-std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
-    auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
+std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
+    auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }

src/vm/tcc/vm_tgc_c.cpp

@@ -30,7 +30,7 @@
  *
  *******************************************************************************/
 
-#include <iss/arch/tgf_c.h>
+#include <iss/arch/tgc_c.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -49,7 +49,7 @@
 
 namespace iss {
 namespace tcc {
-namespace tgf_c {
+namespace tgc_c {
 using namespace iss::arch;
 using namespace iss::debugger;
 
@@ -3251,8 +3251,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
 } // namespace mnrv32
 
 template <>
-std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
-    auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
+std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
+    auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
     if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }