|
|
39d2518fdd
|
checkin: tgc5f builds and runs through
|
2024-07-31 12:30:41 +02:00 |
|
|
|
a365110054
|
fix format
|
2024-07-30 13:34:23 +02:00 |
|
|
|
d2efb23ff7
|
fixes cache behavior for fetches
|
2024-07-25 19:33:50 +02:00 |
|
|
|
04b7a09b19
|
updates date in templates
|
2024-07-25 17:25:12 +02:00 |
|
|
|
72b11beac5
|
moves decoder to dbt-rise-core
|
2024-07-25 10:13:38 +02:00 |
|
|
|
e87b7d5fd0
|
applies clang-format
|
2024-07-24 14:48:50 +02:00 |
|
|
|
5a2b96ef3e
|
adds logging categories for ISS
|
2024-07-24 12:30:07 +02:00 |
|
|
|
c6b99cd155
|
introduces new decoder to interp backend
|
2024-07-24 12:28:35 +02:00 |
|
|
|
b1306c3a47
|
improves instruction decoding by avoiding copying, replaces .size()
|
2024-07-24 08:54:37 +02:00 |
|
|
|
0d6bf924ed
|
changes jh.globals from map to vector
|
2024-07-23 15:45:51 +02:00 |
|
|
|
86de536c8f
|
changes jh globals to seperate riscv specifics
|
2024-07-23 14:35:31 +02:00 |
|
|
|
051dd5e2d3
|
updates templates for decoder in seperate class, adds again generated templates
|
2024-07-23 13:46:10 +02:00 |
|
|
|
e3942be776
|
Introduces decoder in a seperate class
|
2024-07-23 13:08:53 +02:00 |
|
|
|
6ee484a771
|
moves instruction decoder into own class
|
2024-07-23 11:30:33 +02:00 |
|
|
|
60808c8649
|
corrects template since util fns are no longer vm_base members
|
2024-07-23 11:29:56 +02:00 |
|
|
|
0432803d82
|
updates templates and vm impls for better LAST_BRANCH handling
|
2024-07-22 09:04:17 +02:00 |
|
|
|
4f5d9214ed
|
adds newly generated instr.yaml
|
2024-07-18 14:31:36 +02:00 |
|
|
|
d42d2ce533
|
corrects illegal instruction for llvm
|
2024-07-18 14:04:23 +02:00 |
|
|
|
236d12d7f5
|
integrates gen_bool for Conditions (was truncation) into llvm
|
2024-07-18 13:30:42 +02:00 |
|
|
|
e1b6cab890
|
removes setting of NEXT_PC to max when trapping in llvm and asmjit, adds default disass to llvm
|
2024-07-18 12:02:40 +02:00 |
|
|
|
8361f88718
|
removes setting of NEXT_PC to max if trap
|
2024-07-18 11:37:53 +02:00 |
|
|
|
2ec7ea4b41
|
removes leftover gen_sync in asmjit
|
2024-07-17 22:39:12 +02:00 |
|
|
|
b24965d321
|
corrects gen_sync update order, improves illegal instruction
|
2024-07-17 20:52:01 +02:00 |
|
|
|
244bf6d2f2
|
corrects gen_sync before trap check, improves illegal_instruction
|
2024-07-17 20:25:49 +02:00 |
|
|
|
1a4465a371
|
changes template: adds correct illegal instruction, reorders gen_sync to allow correct instr id eve when trapping, adds newly generated vm
|
2024-07-17 19:59:01 +02:00 |
|
|
|
fa82a50824
|
fixes typo in templates
|
2024-07-17 17:24:17 +02:00 |
|
|
|
6dc17857da
|
updates template
|
2024-07-17 15:36:08 +02:00 |
|
|
|
11a30caae8
|
integrates generator changes to canPrecompute
|
2024-07-17 15:14:13 +02:00 |
|
|
|
ac1a26a10c
|
integrates new tval changes into llvm
|
2024-07-17 14:17:02 +02:00 |
|
|
|
7a199e122d
|
integrates new tval changes into asmjit
|
2024-07-17 09:42:12 +02:00 |
|
|
|
d8c3d2e19c
|
integrates new tval changes into tcc
|
2024-07-16 17:35:23 +02:00 |
|
|
|
375755999a
|
integrates new tval changes
|
2024-07-16 15:32:35 +02:00 |
|
|
|
9996fd4833
|
change cache line size to 64
|
2024-07-11 14:03:58 +02:00 |
|
|
|
149b3136d2
|
updates generated files
|
2024-07-10 12:55:36 +02:00 |
|
|
|
ac8f8b0539
|
updates vms with fixed Zc in tgc5c.core_desc
|
2024-07-10 12:51:59 +02:00 |
|
|
|
b2cbf90d0b
|
updates generated files
|
2024-07-10 12:51:59 +02:00 |
|
|
|
373145478e
|
updats file because of generator changes
|
2024-07-10 12:51:59 +02:00 |
|
|
|
55b0cea94f
|
changes vm_base util API
|
2024-07-10 12:51:59 +02:00 |
|
|
|
5b17599aa2
|
allows usage of std::variants
|
2024-07-10 12:51:59 +02:00 |
|
|
|
4cfb15c7cd
|
Asmjit and interp working
|
2024-07-10 12:51:31 +02:00 |
|
|
|
63da7f8d57
|
applies clang-format
|
2024-07-09 13:57:11 +02:00 |
|
|
|
fb4012fbd1
|
moves likely annotation
|
2024-07-09 13:52:10 +02:00 |
|
|
|
24449f1c0f
|
fixes some elf load issue
|
2024-07-05 12:18:36 +02:00 |
|
|
|
fd303c8343
|
fixes asmjit deprecation warning
|
2024-07-05 07:51:37 +02:00 |
|
|
|
346b177a87
|
extends finishing conditions
|
2024-07-05 05:52:29 +02:00 |
|
|
|
d4ec131fa7
|
change COUNT_LIMIT to ICOUNT_LIMIT
|
2024-07-04 10:46:24 +02:00 |
|
|
|
48370a4555
|
asmjit passes backend with new CoreDSL
|
2024-06-22 09:28:26 +02:00 |
|
|
|
36b076774e
|
Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop
|
2024-06-21 13:35:30 +02:00 |
|
|
|
482a4ec253
|
fixes semihosting callbacks in templates
|
2024-06-21 13:35:25 +02:00 |
|
|
|
2fb28364c5
|
fixes remaining templates
|
2024-06-21 10:49:36 +02:00 |
|
