adds vector support to m and mu priv wrapper

This commit is contained in:
Eyck-Alexander Jentzsch 2025-03-31 10:16:01 +02:00
parent f6cdd9d07c
commit 28af695592
3 changed files with 75 additions and 6 deletions

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@ -35,19 +35,18 @@
#ifndef _RISCV_HART_COMMON
#define _RISCV_HART_COMMON
#include <iss/arch/traits.h>
#include <iss/log_categories.h>
#include <iss/mem/memory_if.h>
#include <iss/vm_types.h>
#include "mstatus.h"
#include "util/delegate.h"
#include <array>
#include <cstdint>
#include <elfio/elfio.hpp>
#include <fmt/format.h>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/log_categories.h>
#include <iss/mem/memory_if.h>
#include <iss/semihosting/semihosting.h>
#include <iss/vm_types.h>
#include <limits>
#include <sstream>
#include <string>
@ -324,6 +323,19 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
csr_rd_cb[frm] = MK_CSR_RD_CB(read_fcsr);
csr_wr_cb[frm] = MK_CSR_WR_CB(write_fcsr);
}
if(traits<BASE>::V_REGS_SIZE > 0) {
csr_rd_cb[vstart] = MK_CSR_RD_CB(read_vstart);
csr_wr_cb[vstart] = MK_CSR_WR_CB(write_vstart);
csr_rd_cb[vxsat] = MK_CSR_RD_CB(read_vxsat);
csr_wr_cb[vxsat] = MK_CSR_WR_CB(write_vxsat);
csr_rd_cb[vxrm] = MK_CSR_RD_CB(read_vxrm);
csr_wr_cb[vxrm] = MK_CSR_WR_CB(write_vxrm);
csr_rd_cb[vcsr] = MK_CSR_RD_CB(read_vcsr);
csr_wr_cb[vcsr] = MK_CSR_WR_CB(write_vcsr);
csr_rd_cb[vl] = MK_CSR_RD_CB(read_vl);
csr_rd_cb[vtype] = MK_CSR_RD_CB(read_vtype);
csr_rd_cb[vlenb] = MK_CSR_RD_CB(read_vlenb);
}
for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
csr_rd_cb[addr] = MK_CSR_RD_CB(read_null);
csr_wr_cb[addr] = MK_CSR_WR_CB(write_plain);
@ -694,6 +706,63 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
return iss::Ok;
}
iss::status read_vstart(unsigned addr, reg_t& val) {
val = this->get_vstart();
return iss::Ok;
}
iss::status write_vstart(unsigned addr, reg_t val) {
this->set_vstart(val);
return iss::Ok;
}
iss::status read_vxsat(unsigned addr, reg_t& val) {
val = csr[vxsat];
return iss::Ok;
}
iss::status write_vxsat(unsigned addr, reg_t val) {
csr[vxsat] = val & 1;
csr[vcsr] = (~1ULL & csr[vcsr]) | (val & 1);
return iss::Ok;
}
iss::status read_vxrm(unsigned addr, reg_t& val) {
val = csr[vxrm];
return iss::Ok;
}
iss::status write_vxrm(unsigned addr, reg_t val) {
csr[vxrm] = val & 0b11;
csr[vcsr] = (~0b110ULL & csr[vcsr]) | ((val & 0b11) << 1);
return iss::Ok;
}
iss::status read_vcsr(unsigned addr, reg_t& val) {
val = csr[vcsr];
return iss::Ok;
}
iss::status write_vcsr(unsigned addr, reg_t val) {
csr[vcsr] = val;
return iss::Ok;
}
iss::status read_vl(unsigned addr, reg_t& val) {
val = this->get_vl();
return iss::Ok;
}
iss::status read_vtype(unsigned addr, reg_t& val) {
val = this->get_vtype();
return iss::Ok;
}
iss::status read_vlenb(unsigned addr, reg_t& val) {
val = csr[vlenb];
return iss::Ok;
}
priv_if<reg_t> get_priv_if() {
return priv_if<reg_t>{.read_csr = [this](unsigned addr, reg_t& val) -> iss::status { return read_csr(addr, val); },
.write_csr = [this](unsigned addr, reg_t val) -> iss::status { return write_csr(addr, val); },

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@ -45,10 +45,10 @@
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <iss/mem/memory_with_htif.h>
#include <array>
#include <elfio/elfio.hpp>
#include <fmt/format.h>
#include <iss/mem/memory_with_htif.h>
#include <unordered_map>
namespace iss {

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@ -47,8 +47,8 @@
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <iss/mem/memory_with_htif.h>
#include <fmt/format.h>
#include <iss/mem/memory_with_htif.h>
#include <unordered_map>
namespace iss {