DBT-RISE/DBT-RISE-TGC
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adds the missing vector csrs to the architectural state

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Eyck-Alexander Jentzsch 2025-02-18 20:52:26 +01:00
parent 77807fec01
commit e59458aa0e
2 changed files with 14 additions and 1 deletions
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11
gen_input/templates/CORENAME.h.gtl
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@ -176,18 +176,27 @@ if(fcsr != null) {%>
def vstart = registers.find {it.name=='vstart'}
def vl = registers.find {it.name=='vl'}
def vtype = registers.find {it.name=='vtype'}
def vxsat = registers.find {it.name=='vxsat'}
def vxrm = registers.find {it.name=='vxrm'}
if(vtype != null) {%>
uint${vstart.size}_t get_vstart(){return reg.vstart;}
void set_vstart(uint${vstart.size}_t val){reg.vstart = val;}
uint${vl.size}_t get_vl(){return reg.vl;}
uint${vtype.size}_t get_vtype(){return reg.vtype;}
uint${vxsat.size}_t get_vxsat(){return reg.vxsat;}
void set_vxsat(uint${vxsat.size}_t val){reg.vxsat = val;}
uint${vxrm.size}_t get_vxrm(){return reg.vxrm;}
void set_vxrm(uint${vxrm.size}_t val){reg.vxrm = val;}
<%} else { %>
uint32_t get_vstart(){return 0;}
void set_vstart(uint32_t val){}
uint32_t get_vl(){return 0;}
uint32_t get_vtype(){return 0;}
uint32_t get_vxsat(){return 0;}
void set_vxsat(uint32_t val){}
uint32_t get_vxrm(){return 0;}
void set_vxrm(uint32_t val){}
<%}%>
};

4
src/iss/arch/tgc5c.h
View File

@ -256,6 +256,10 @@ struct tgc5c: public arch_if {
void set_vstart(uint32_t val){}
uint32_t get_vl(){return 0;}
uint32_t get_vtype(){return 0;}
uint32_t get_vxsat(){return 0;}
void set_vxsat(uint32_t val){}
uint32_t get_vxrm(){return 0;}
void set_vxrm(uint32_t val){}
};