DBT-RISE
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DBT-RISE-TGC
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Merge branch 'develop'

This commit is contained in:
Eyck Jentzsch 2021-11-11 19:34:21 +01:00
parent 09b01af3fa d31b4ef5a8
commit d5fa47ef7f
28 changed files with 1094 additions and 1698 deletions
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1
.gitignore vendored
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@ -31,3 +31,4 @@ language.settings.xml
/*.out /*.out
/dump.json /dump.json
/src-gen/ /src-gen/
/*.yaml

41
CMakeLists.txt
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@ -40,24 +40,38 @@ set(LIB_SOURCES
) )
if(WITH_LLVM) if(WITH_LLVM)
set(LIB_SOURCES ${LIB_SOURCES} FILE(GLOB TGC_LLVM_SOURCES
src/vm/llvm/fp_impl.cpp ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/llvm/vm_*.cpp
#src/vm/llvm/vm_tgf_b.cpp )
#src/vm/llvm/vm_tgf_c.cpp list(APPEND LIB_SOURCES ${TGC_LLVM_SOURCES})
) endif()
if(WITH_TCC)
FILE(GLOB TGC_TCC_SOURCES
${CMAKE_CURRENT_SOURCE_DIR}/src/vm/tcc/vm_*.cpp
)
list(APPEND LIB_SOURCES ${TGC_TCC_SOURCES})
endif() endif()
# Define the library # Define the library
add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES}) add_library(${PROJECT_NAME} ${LIB_SOURCES})
# list code gen dependencies # list code gen dependencies
if(TARGET ${CORE_NAME}_cpp) if(TARGET ${CORE_NAME}_cpp)
add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp) add_dependencies(${PROJECT_NAME} ${CORE_NAME}_cpp)
endif() endif()
target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow) if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
endif()
target_include_directories(${PROJECT_NAME} PUBLIC incl) target_include_directories(${PROJECT_NAME} PUBLIC incl)
target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp) target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive) if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
else()
target_link_libraries(${PROJECT_NAME} PUBLIC dbt-core)
endif()
if(TARGET CONAN_PKG::elfio) if(TARGET CONAN_PKG::elfio)
target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio) target_link_libraries(${PROJECT_NAME} PUBLIC CONAN_PKG::elfio)
elseif(TARGET elfio::elfio) elseif(TARGET elfio::elfio)
@ -98,16 +112,15 @@ if(WITH_LLVM)
target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs}) target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
endif() endif()
# Links the target exe against the libraries # Links the target exe against the libraries
target_link_libraries(${PROJECT_NAME} dbt-rise-tgc) target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc)
#target_link_libraries(${PROJECT_NAME} jsoncpp)
if(TARGET Boost::program_options) if(TARGET Boost::program_options)
target_link_libraries(${PROJECT_NAME} Boost::program_options Boost::thread) target_link_libraries(${PROJECT_NAME} PUBLIC Boost::program_options)
else() else()
target_link_libraries(${PROJECT_NAME} ${BOOST_program_options_LIBRARY} ${BOOST_thread_LIBRARY}) target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
endif() endif()
target_link_libraries(${PROJECT_NAME} ${CMAKE_DL_LIBS}) target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
if (Tcmalloc_FOUND) if (Tcmalloc_FOUND)
target_link_libraries(${PROJECT_NAME} ${Tcmalloc_LIBRARIES}) target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
endif(Tcmalloc_FOUND) endif(Tcmalloc_FOUND)
install(TARGETS tgc-sim install(TARGETS tgc-sim

2
gen_input/CoreDSL-Instruction-Set-Description

@ -1 +1 @@
Subproject commit 8d9a0fb1493b762014c330c71ac8cef96753d302 Subproject commit b005607fc30c4467683b6044eaca7eb378061b53

14
gen_input/TGC_B.core_desc Normal file
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@ -0,0 +1,14 @@
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_B provides RV32I, Zicsr, Zifencei {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000000000100000000;
unsigned MARCHID_VAL = 0x80000002;
}
}

13
gen_input/TGC_C.core_desc Normal file
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@ -0,0 +1,13 @@
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned MARCHID_VAL = 0x80000003;
}
}

13
gen_input/TGC_D.core_desc Normal file
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@ -0,0 +1,13 @@
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_D provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000100000011000100000100;
unsigned MARCHID_VAL = 0x80000004;
}
}

73
gen_input/TGC_D_XRB_MAC.core_desc Normal file
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@ -0,0 +1,73 @@
import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
InstructionSet X_RB_MAC extends RISCVBase {
architectural_state {
register unsigned<64> ACC;
}
instructions {
RESET_ACC { // v-- funct7 v-- funct3
encoding: 7'd0 :: 10'b0 :: 3'd0 :: 5'b0 :: 7'b0001011;
behavior: ACC = 0;
}
GET_ACC_LO {
encoding: 7'd1 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
behavior: if (rd != 0) X[rd] = ACC[31:0];
}
GET_ACC_HI {
encoding: 7'd2 :: 10'b0 :: 3'd0 :: rd[4:0] :: 7'b0001011;
behavior: if (rd != 0) X[rd] = ACC[63:32];
}
MACU_32 {
encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
behavior: {
unsigned<64> mul = X[rs1] * X[rs2];
unsigned<33> add = mul[31:0] + ACC[31:0];
ACC = add[31:0];
}
}
MACS_32 {
encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd1 :: 5'b0 :: 7'b0001011;
behavior: {
signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
signed<33> add = ((signed) mul[31:0]) + ((signed) ACC[31:0]);
ACC = add[31:0]; // bit range always yields unsigned type
}
}
MACU_64 {
encoding: 7'd0 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
behavior: {
unsigned<64> mul = X[rs1] * X[rs2];
unsigned<65> add = mul + ACC;
ACC = add[63:0];
}
}
MACS_64 {
encoding: 7'd1 :: rs2[4:0] :: rs1[4:0] :: 3'd2 :: 5'b0 :: 7'b0001011;
behavior: {
signed<64> mul = ((signed) X[rs1]) * ((signed) X[rs2]);
signed<65> add = mul + ((signed) ACC);
ACC = add[63:0];
}
}
}
}
Core TGC_D_XRB_MAC provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_MAC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned MARCHID_VAL = 0x80000004;
}
}

133
gen_input/TGC_D_XRB_NN.core_desc Normal file
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@ -0,0 +1,133 @@
import "CoreDSL-Instruction-Set-Description/RISCVBase.core_desc"
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
InstructionSet X_RB_NN extends RISCVBase {
instructions {
// signed saturate with pre-shift
SSAT {
// instruction format: R-type
// opcode space: custom-1 (inst[6:2] = 01010)
// opcode = 0b0101011, func3 = 0b000, func7 = <bit position to saturate to>
encoding: sat_bit_pos[6:0] :: rs2[4:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b0101011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}, {name(sat_bit_pos)}";
behavior: {
signed<XLEN> val_s = (signed<XLEN>)X[rs1];
unsigned<XLEN> pre_shift = (unsigned<XLEN>)X[rs2];
unsigned<XLEN> sat_limit;
signed<XLEN> upper_limit;
signed<XLEN> lower_limit;
if((rd != 0) && (sat_bit_pos > 0) && (sat_bit_pos <= 32) && (pre_shift < 32)) {
sat_limit = (unsigned<XLEN>)(1 << (sat_bit_pos - 1));
upper_limit = (signed)sat_limit - 1;
lower_limit = (signed)sat_limit * (-1);
// important: arithmetical shift right
val_s = val_s >> pre_shift;
X[rd] = (val_s > upper_limit) ? (upper_limit) : ( (val_s < lower_limit) ? (lower_limit) : (val_s) );
}
}
}
// custom packed dot product with accumulation (4x8bit)
PDOT8 {
// instruction format: R-type
// opcode space: custom-1 (inst[6:2] = 01010)
// opcode = 0b0101011, func3 = 0b001, func7 = 0b0000000
encoding: 0b0000000 :: rs2[4:0] :: rs1[4:0] :: 0b001 :: rd[4:0] :: 0b0101011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: {
signed<8> op1_0 = (signed<8>)X[rs1][ 7: 0];
signed<8> op1_1 = (signed<8>)X[rs1][15: 8];
signed<8> op1_2 = (signed<8>)X[rs1][23:16];
signed<8> op1_3 = (signed<8>)X[rs1][31:24];
signed<8> op2_0 = (signed<8>)X[rs2][ 7: 0];
signed<8> op2_1 = (signed<8>)X[rs2][15: 8];
signed<8> op2_2 = (signed<8>)X[rs2][23:16];
signed<8> op2_3 = (signed<8>)X[rs2][31:24];
signed<XLEN> op3 = (signed<XLEN>)X[rd];
signed<16> mul0 = op1_0 * op2_0;
signed<16> mul1 = op1_1 * op2_1;
signed<16> mul2 = op1_2 * op2_2;
signed<16> mul3 = op1_3 * op2_3;
signed<19> sum_tmp = mul0 + mul1 + mul2 + mul3;
signed<33> result = op3 + sum_tmp;
if(rd != 0) X[rd] = result[31:0];
}
}
// standard signed multiply accumulate with 32 bit operands and 32 bit result
MAC {
// instruction format: R-type
// opcode space: custom-1 (inst[6:2] = 01010)
// opcode = 0b0101011, func3 = 0b010, func7 = 0b0000000
encoding: 0b0000000 :: rs2[4:0] :: rs1[4:0] :: 0b010 :: rd[4:0] :: 0b0101011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
behavior: {
signed<65> result = (signed)X[rs1] * (signed)X[rs2] + (signed)X[rd];
if(rd != 0) X[rd] = result[31:0];
}
}
// WARNING: The following two HW loop instructions are not fully specified or implemented. The idea is to design the HW loops identical to the RI5CY core (current naming: CV32E40P)
// See "Short Hardware Loop Setup Instructions" from RI5CY specification document from April 2019, revision 4.0: https://www.pulp-platform.org/docs/ri5cy_user_manual.pdf -> page 38, chapter 14.2
// Specific CSRs are introduced to support the HW loops (see page 17, chapter 7).
// lp.setup HW loop (Short Hardware Loop Setup Instruction)
LOOP {
// instruction format: I-type
// opcode space: custom-3 (inst[6:2] = 11110)
// opcode = 0b1111011, func3 = 0b100
// uimmL[11:0] src1 100 0000 L 111 1011 -> lp.setup L,rs1, uimmL
encoding: imm[11:0] :: rs1[4:0] :: 0b100 :: 0b0000 :: L[0:0] :: 0b1111011;
args_disass:"{name(L)}, {name(rs1)}, {imm}";
behavior: {
// L: loop level (two loop levels would be sufficient); L=0 has higher priority and is considered as the inner loop.
/*
lpstart[L] = PC + 4;
lpend[L] = PC + ((unsigned<12>)imm << 1);
lpcount[L] = rs1;
*/
}
}
// lp.setupi HW loop (Short Hardware Loop Setup Instruction with immediate value for loop count)
LOOPI {
// instruction format: I-type
// opcode space: custom-3 (inst[6:2] = 11110)
// opcode = 0b1111011, func3 = 0b101
// uimmL[11:0] uimmS[4:0] 101 0000 L 111 1011 -> lp.setupi L, uimmS, uimmL
encoding: imm2[11:0] :: imm1[4:0] :: 0b101 :: 0b0000 :: L[0:0] :: 0b1111011;
args_disass:"{name(L)}, {imm1}, {imm2}";
behavior: {
// L: loop level (two loop levels would be sufficient); L=0 has higher priority and is considered as the inner loop.
/*
lpstart[L] = PC + 4;
lpend[L] = PC + ((unsigned<5>)imm1 << 1);
lpcount[L] = (unsigned<12>)imm2;
*/
}
}
}
}
Core TGC_D_XRB_NN provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_NN {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000100100000011000100000100;
unsigned MARCHID_VAL = 0x80000004;
}
}

37
gen_input/TGFS.core_desc
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@ -1,37 +0,0 @@
import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_B provides RV32I {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000000000100000000;
unsigned PGSIZE = 0x1000; //1 << 12;
unsigned PGMASK = 0xfff; //PGSIZE-1
}
}
Core TGC_C provides RV32I, RV32M, RV32IC {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned PGSIZE = 0x1000; //1 << 12;
unsigned PGMASK = 0xfff; //PGSIZE-1
}
}
Core TGC_D provides RV32I, RV32M, RV32IC {
architectural_state {
unsigned XLEN=32;
unsigned PCLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
}
}

4
gen_input/templates/CORENAME.cpp.gtl
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@ -58,7 +58,9 @@ ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default; ${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
void ${coreDef.name.toLowerCase()}::reset(uint64_t address) { void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0)); auto base_ptr = reinterpret_cast<traits<${coreDef.name.toLowerCase()}>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i)
*(base_ptr+i)=0;
reg.PC=address; reg.PC=address;
reg.NEXT_PC=reg.PC; reg.NEXT_PC=reg.PC;
reg.PRIV=0x3; reg.PRIV=0x3;

8
gen_input/templates/CORENAME.h.gtl
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@ -140,14 +140,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
void reset(uint64_t address=0) override; void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override; uint8_t* get_regs_base_ptr() override;
/// deprecated
void get_reg(short idx, std::vector<uint8_t>& value) override {}
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
bool get_flag(int flag) override {return false;}
void set_flag(int, bool value) override {};
/// deprecated
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
inline uint64_t get_icount() { return reg.icount; } inline uint64_t get_icount() { return reg.icount; }

16
gen_input/templates/CORENAME_instr.yaml.gtl Normal file
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@ -0,0 +1,16 @@
<% def getInstructionGroups() {
def instrGroups = [:]
instructions.each {
def groupName = it['instruction'].eContainer().name
if(!instrGroups.containsKey(groupName)) {
instrGroups[groupName]=[]
}
instrGroups[groupName]+=it;
}
instrGroups
}%><%getInstructionGroups().each{name, instrList -> %>
${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %>
- ${it.instruction.name}:
encoding: ${it.encoding}
mask: ${it.mask}<%}}%>

18
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -29,7 +29,13 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
*******************************************************************************/ *******************************************************************************/
<%
import com.minres.coredsl.util.BigIntegerWithRadix
def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
}
%>
#include "../fp_functions.h" #include "../fp_functions.h"
#include <iss/arch/${coreDef.name.toLowerCase()}.h> #include <iss/arch/${coreDef.name.toLowerCase()}.h>
#include <iss/arch/riscv_hart_m_p.h> #include <iss/arch/riscv_hart_m_p.h>
@ -92,7 +98,10 @@ protected:
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 }; // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 }; enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 }; enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) }; enum {
LUT_SIZE = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK32)),
LUT_SIZE_C = 1 << util::bit_count(static_cast<uint32_t>(EXTR_MASK16))
};
std::array<compile_func, LUT_SIZE> lut; std::array<compile_func, LUT_SIZE> lut;
@ -201,8 +210,8 @@ private:
} }
// used registers<%instr.usedVariables.each{ k,v-> // used registers<%instr.usedVariables.each{ k,v->
if(v.isArray) {%> if(v.isArray) {%>
auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
auto* ${k} = reinterpret_cast<uint${v.type.size}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]); auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
<%}}%>// calculate next pc value <%}}%>// calculate next pc value
*NEXT_PC = *PC + ${instr.length/8}; *NEXT_PC = *PC + ${instr.length/8};
// execute instruction // execute instruction
@ -243,7 +252,7 @@ private:
return pc; return pc;
} }
static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK; //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
auto phys_pc = this->core.v2p(pc); auto phys_pc = this->core.v2p(pc);
//if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary //if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
@ -324,6 +333,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
if (is_jump_to_self_enabled(cond) && if (is_jump_to_self_enabled(cond) &&
(insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
auto f = decode_inst(insn); auto f = decode_inst(insn);
auto old_pc = pc.val;
pc = (this->*f)(pc, insn); pc = (this->*f)(pc, insn);
} }
} }

5
incl/iss/arch/riscv_hart_common.h
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@ -43,6 +43,8 @@ namespace arch {
enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 }; enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8};
enum riscv_csr { enum riscv_csr {
/* user-level CSR */ /* user-level CSR */
// User Trap Setup // User Trap Setup
@ -164,7 +166,8 @@ enum riscv_csr {
// Debug Mode Registers // Debug Mode Registers
dcsr = 0x7B0, dcsr = 0x7B0,
dpc = 0x7B1, dpc = 0x7B1,
dscratch = 0x7B2 dscratch0 = 0x7B2,
dscratch1 = 0x7B3
}; };

229
incl/iss/arch/riscv_hart_m_p.h
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@ -66,7 +66,7 @@
namespace iss { namespace iss {
namespace arch { namespace arch {
template <typename BASE> class riscv_hart_m_p : public BASE { template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_m_p : public BASE {
protected: protected:
const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}}; const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
const std::array<const char *, 16> trap_str = {{"" const std::array<const char *, 16> trap_str = {{""
@ -92,7 +92,7 @@ protected:
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
public: public:
using core = BASE; using core = BASE;
using this_class = riscv_hart_m_p<BASE>; using this_class = riscv_hart_m_p<BASE, FEAT>;
using phys_addr_t = typename core::phys_addr_t; using phys_addr_t = typename core::phys_addr_t;
using reg_t = typename core::reg_t; using reg_t = typename core::reg_t;
using addr_t = typename core::addr_t; using addr_t = typename core::addr_t;
@ -221,7 +221,7 @@ public:
protected: protected:
struct riscv_instrumentation_if : public iss::instrumentation_if { struct riscv_instrumentation_if : public iss::instrumentation_if {
riscv_instrumentation_if(riscv_hart_m_p<BASE> &arch) riscv_instrumentation_if(riscv_hart_m_p<BASE, FEAT> &arch)
: arch(arch) {} : arch(arch) {}
/** /**
* get the name of this architecture * get the name of this architecture
@ -236,7 +236,7 @@ protected:
virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; }; virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
riscv_hart_m_p<BASE> &arch; riscv_hart_m_p<BASE, FEAT> &arch;
}; };
friend struct riscv_instrumentation_if; friend struct riscv_instrumentation_if;
@ -246,6 +246,9 @@ protected:
virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data); virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data); virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
iss::status read_clic(uint64_t addr, unsigned length, uint8_t *const data);
iss::status write_clic(uint64_t addr, unsigned length, const uint8_t *const data);
virtual iss::status read_csr(unsigned addr, reg_t &val); virtual iss::status read_csr(unsigned addr, reg_t &val);
virtual iss::status write_csr(unsigned addr, reg_t val); virtual iss::status write_csr(unsigned addr, reg_t val);
@ -270,10 +273,22 @@ protected:
std::unordered_map<uint64_t, uint8_t> atomic_reservation; std::unordered_map<uint64_t, uint8_t> atomic_reservation;
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb; std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb; std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
uint8_t clic_cfg_reg{0};
uint32_t clic_info_reg{0};
std::array<uint32_t, 32> clic_inttrig_reg;
union clic_int_reg_t {
struct{
uint8_t ip;
uint8_t ie;
uint8_t attr;
uint8_t ctl;
};
uint32_t raw;
};
std::vector<clic_int_reg_t> clic_int_reg;
private: iss::status read_csr_reg(unsigned addr, reg_t &val);
iss::status read_reg(unsigned addr, reg_t &val); iss::status write_csr_reg(unsigned addr, reg_t val);
iss::status write_reg(unsigned addr, reg_t val);
iss::status read_null(unsigned addr, reg_t &val); iss::status read_null(unsigned addr, reg_t &val);
iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;} iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;}
iss::status read_cycle(unsigned addr, reg_t &val); iss::status read_cycle(unsigned addr, reg_t &val);
@ -291,50 +306,63 @@ private:
iss::status write_ip(unsigned addr, reg_t val); iss::status write_ip(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val); iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_epc(unsigned addr, reg_t val); iss::status write_epc(unsigned addr, reg_t val);
iss::status write_intstatus(unsigned addr, reg_t val);
iss::status write_intthresh(unsigned addr, reg_t val);
iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
iss::status read_dcsr_reg(unsigned addr, reg_t &val);
iss::status write_dcsr_reg(unsigned addr, reg_t val);
iss::status read_dpc_reg(unsigned addr, reg_t &val);
iss::status write_dpc_reg(unsigned addr, reg_t val);
reg_t mhartid_reg{0x0}; reg_t mhartid_reg{0x0};
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb; std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb; std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
protected:
void check_interrupt(); void check_interrupt();
bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
uint64_t clic_base_addr{0};
unsigned clic_num_irq{0};
unsigned clic_num_trigger{0};
unsigned mcause_max_irq{16};
inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
}; };
template <typename BASE> template <typename BASE, features_e FEAT>
riscv_hart_m_p<BASE>::riscv_hart_m_p() riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p()
: state() : state()
, instr_if(*this) { , instr_if(*this) {
// reset values // reset values
csr[misa] = traits<BASE>::MISA_VAL; csr[misa] = traits<BASE>::MISA_VAL;
csr[mvendorid] = 0x669; csr[mvendorid] = 0x669;
csr[marchid] = 0x80000003; csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1; csr[mimpid] = 1;
csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file
uart_buf.str(""); uart_buf.str("");
for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){ for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){
csr_rd_cb[addr] = &this_class::read_null; csr_rd_cb[addr] = &this_class::read_null;
csr_wr_cb[addr] = &this_class::write_reg; csr_wr_cb[addr] = &this_class::write_csr_reg;
} }
for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){ for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){
csr_rd_cb[addr] = &this_class::read_null; csr_rd_cb[addr] = &this_class::read_null;
csr_wr_cb[addr] = &this_class::write_reg; csr_wr_cb[addr] = &this_class::write_csr_reg;
} }
for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){ for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){
csr_rd_cb[addr] = &this_class::read_null; csr_rd_cb[addr] = &this_class::read_null;
csr_wr_cb[addr] = &this_class::write_reg; csr_wr_cb[addr] = &this_class::write_csr_reg;
} }
for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){ for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){
csr_rd_cb[addr] = &this_class::read_null; csr_rd_cb[addr] = &this_class::read_null;
} }
for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){ for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){
csr_rd_cb[addr] = &this_class::read_null; csr_rd_cb[addr] = &this_class::read_null;
//csr_wr_cb[addr] = &this_class::write_reg; //csr_wr_cb[addr] = &this_class::write_csr_reg;
} }
// common regs // common regs
const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}}; const std::array<unsigned, 10> addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, mtval, mscratch}};
for(auto addr: addrs) { for(auto addr: addrs) {
csr_rd_cb[addr] = &this_class::read_reg; csr_rd_cb[addr] = &this_class::read_csr_reg;
csr_wr_cb[addr] = &this_class::write_reg; csr_wr_cb[addr] = &this_class::write_csr_reg;
} }
// special handling & overrides // special handling & overrides
csr_rd_cb[time] = &this_class::read_time; csr_rd_cb[time] = &this_class::read_time;
@ -362,15 +390,23 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
csr_rd_cb[mie] = &this_class::read_ie; csr_rd_cb[mie] = &this_class::read_ie;
csr_wr_cb[mie] = &this_class::write_ie; csr_wr_cb[mie] = &this_class::write_ie;
csr_rd_cb[mhartid] = &this_class::read_hartid; csr_rd_cb[mhartid] = &this_class::read_hartid;
csr_rd_cb[mcounteren] = &this_class::read_null;
csr_wr_cb[mcounteren] = &this_class::write_null;
csr_wr_cb[misa] = &this_class::write_null; csr_wr_cb[misa] = &this_class::write_null;
csr_wr_cb[mvendorid] = &this_class::write_null; csr_wr_cb[mvendorid] = &this_class::write_null;
csr_wr_cb[marchid] = &this_class::write_null; csr_wr_cb[marchid] = &this_class::write_null;
csr_wr_cb[mimpid] = &this_class::write_null; csr_wr_cb[mimpid] = &this_class::write_null;
if(FEAT & FEAT_DEBUG){
csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg;
csr_wr_cb[dpc] = &this_class::write_dpc_reg;
csr_rd_cb[dpc] = &this_class::read_dpc_reg;
csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
}
} }
template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) { template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT>::load_file(std::string name, int type) {
FILE *fp = fopen(name.c_str(), "r"); FILE *fp = fopen(name.c_str(), "r");
if (fp) { if (fp) {
std::array<char, 5> buf; std::array<char, 5> buf;
@ -397,7 +433,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_fi
traits<BASE>::MEM, pseg->get_physical_address(), traits<BASE>::MEM, pseg->get_physical_address(),
fsize, reinterpret_cast<const uint8_t *const>(seg_data)); fsize, reinterpret_cast<const uint8_t *const>(seg_data));
if (res != iss::Ok) if (res != iss::Ok)
LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
<< pseg->get_physical_address(); << pseg->get_physical_address();
} }
} }
@ -436,8 +472,8 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_fi
throw std::runtime_error("memory load file not found"); throw std::runtime_error("memory load file not found");
} }
template <typename BASE> template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_type access, const uint32_t space, iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const access_type access, const uint32_t space,
const uint64_t addr, const unsigned length, uint8_t *const data) { const uint64_t addr, const unsigned length, uint8_t *const data) {
#ifndef NDEBUG #ifndef NDEBUG
if (access && iss::access_type::DEBUG) { if (access && iss::access_type::DEBUG) {
@ -505,8 +541,8 @@ iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_typ
} }
} }
template <typename BASE> template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_type access, const uint32_t space, iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const access_type access, const uint32_t space,
const uint64_t addr, const unsigned length, const uint8_t *const data) { const uint64_t addr, const unsigned length, const uint8_t *const data) {
#ifndef NDEBUG #ifndef NDEBUG
const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
@ -621,7 +657,7 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
} }
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_csr(unsigned addr, reg_t &val) {
if (addr >= csr.size()) return iss::Err; if (addr >= csr.size()) return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3; auto req_priv_lvl = (addr >> 8) & 0x3;
if (this->reg.PRIV < req_priv_lvl) // not having required privileges if (this->reg.PRIV < req_priv_lvl) // not having required privileges
@ -632,7 +668,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_csr(unsigned add
return (this->*(it->second))(addr, val); return (this->*(it->second))(addr, val);
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_csr(unsigned addr, reg_t val) {
if (addr >= csr.size()) return iss::Err; if (addr >= csr.size()) return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3; auto req_priv_lvl = (addr >> 8) & 0x3;
if (this->reg.PRIV < req_priv_lvl) // not having required privileges if (this->reg.PRIV < req_priv_lvl) // not having required privileges
@ -645,22 +681,22 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_csr(unsigned ad
return (this->*(it->second))(addr, val); return (this->*(it->second))(addr, val);
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_reg(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_csr_reg(unsigned addr, reg_t &val) {
val = csr[addr]; val = csr[addr];
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_null(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_null(unsigned addr, reg_t &val) {
val = 0; val = 0;
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_reg(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_csr_reg(unsigned addr, reg_t val) {
csr[addr] = val; csr[addr] = val;
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) {
auto cycle_val = this->reg.icount + cycle_offset; auto cycle_val = this->reg.icount + cycle_offset;
if (addr == mcycle) { if (addr == mcycle) {
val = static_cast<reg_t>(cycle_val); val = static_cast<reg_t>(cycle_val);
@ -671,7 +707,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned a
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cycle(unsigned addr, reg_t val) {
if (sizeof(typename traits<BASE>::reg_t) != 4) { if (sizeof(typename traits<BASE>::reg_t) != 4) {
if (addr == mcycleh) if (addr == mcycleh)
return iss::Err; return iss::Err;
@ -687,7 +723,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_instret(unsigned addr, reg_t &val) {
if ((addr&0xff) == (minstret&0xff)) { if ((addr&0xff) == (minstret&0xff)) {
val = static_cast<reg_t>(this->reg.instret); val = static_cast<reg_t>(this->reg.instret);
} else if ((addr&0xff) == (minstreth&0xff)) { } else if ((addr&0xff) == (minstreth&0xff)) {
@ -697,7 +733,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_instret(unsigned
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_instret(unsigned addr, reg_t val) {
if (sizeof(typename traits<BASE>::reg_t) != 4) { if (sizeof(typename traits<BASE>::reg_t) != 4) {
if ((addr&0xff) == (minstreth&0xff)) if ((addr&0xff) == (minstreth&0xff))
return iss::Err; return iss::Err;
@ -713,7 +749,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigne
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) {
uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052; uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052;
if (addr == time) { if (addr == time) {
val = static_cast<reg_t>(time_val); val = static_cast<reg_t>(time_val);
@ -724,64 +760,105 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned ad
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_tvec(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_tvec(unsigned addr, reg_t &val) {
val = csr[mtvec] & ~2; val = csr[mtvec] & ~2;
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_status(unsigned addr, reg_t &val) {
val = state.mstatus & hart_state_type::get_mask(); val = state.mstatus & hart_state_type::get_mask();
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_status(unsigned addr, reg_t val) {
state.write_mstatus(val); state.write_mstatus(val);
check_interrupt(); check_interrupt();
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cause(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable csr[mcause] = val & ((1UL<<(traits<BASE>::XLEN-1))|0xf); //TODO: make exception code size configurable
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_hartid(unsigned addr, reg_t &val) {
val = csr[mie];
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned addr, reg_t &val) {
val = mhartid_reg; val = mhartid_reg;
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
auto mask = get_irq_mask();
val = csr[mie] & mask;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
auto mask = get_irq_mask(); auto mask = get_irq_mask();
csr[mie] = (csr[mie] & ~mask) | (val & mask); csr[mie] = (csr[mie] & ~mask) | (val & mask);
check_interrupt(); check_interrupt();
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_ip(unsigned addr, reg_t &val) {
val = csr[mip]; auto mask = get_irq_mask();
val = csr[mip] & mask;
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
auto mask = get_irq_mask(); auto mask = get_irq_mask();
mask &= ~(1 << 7); // MTIP is read only mask &= 0xf; // only xSIP is writable
csr[mip] = (csr[mip] & ~mask) | (val & mask); csr[mip] = (csr[mip] & ~mask) | (val & mask);
check_interrupt(); check_interrupt();
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_epc(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_epc(unsigned addr, reg_t val) {
csr[addr] = val & get_pc_mask(); csr[addr] = val & get_pc_mask();
return iss::Ok; return iss::Ok;
} }
template <typename BASE> template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) {
iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) { if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
// +-------------- ebreakm
// | +---------- stepi
// | | +++----- cause
// | | ||| +- step
csr[addr] = val & 0b1000100111000100U;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
val = csr[addr];
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
csr[addr] = val;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_dpc_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
val = this->reg.DPC;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_dpc_reg(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
this->reg.DPC = val;
return iss::Ok;
}
template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
if(mem_read_cb) return mem_read_cb(paddr, length, data); if(mem_read_cb) return mem_read_cb(paddr, length, data);
switch (paddr.val) { switch (paddr.val) {
case 0x0200BFF8: { // CLINT base, mtime reg case 0x0200BFF8: { // CLINT base, mtime reg
@ -805,8 +882,8 @@ iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, u
return iss::Ok; return iss::Ok;
} }
template <typename BASE> template <typename BASE, features_e FEAT>
iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) { iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) {
if(mem_write_cb) return mem_write_cb(paddr, length, data); if(mem_write_cb) return mem_write_cb(paddr, length, data);
switch (paddr.val) { switch (paddr.val) {
case 0x10013000: // UART0 base, TXFIFO reg case 0x10013000: // UART0 base, TXFIFO reg
@ -883,12 +960,12 @@ iss::status riscv_hart_m_p<BASE>::write_mem(phys_addr_t paddr, unsigned length,
return iss::Ok; return iss::Ok;
} }
template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t address) { template <typename BASE, features_e FEAT> inline void riscv_hart_m_p<BASE, FEAT>::reset(uint64_t address) {
BASE::reset(address); BASE::reset(address);
state.mstatus = hart_state_type::mstatus_reset_val; state.mstatus = hart_state_type::mstatus_reset_val;
} }
template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() { template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check_interrupt() {
//auto ideleg = csr[mideleg]; //auto ideleg = csr[mideleg];
// Multiple simultaneous interrupts and traps at the same privilege level are // Multiple simultaneous interrupts and traps at the same privilege level are
// handled in the following decreasing priority order: // handled in the following decreasing priority order:
@ -910,17 +987,43 @@ template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
} }
} }
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) { template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0] // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
// calculate and write mcause val // calculate and write mcause val
auto trap_id = bit_sub<0, 16>(flags); auto trap_id = bit_sub<0, 16>(flags);
auto cause = bit_sub<16, 15>(flags); auto cause = bit_sub<16, 15>(flags);
if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
// calculate effective privilege level // calculate effective privilege level
if (trap_id == 0) { // exception if (trap_id == 0) { // exception
if (cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
// store ret addr in xepc register // store ret addr in xepc register
csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception csr[mepc] = static_cast<reg_t>(addr) & get_pc_mask(); // store actual address instruction of exception
csr[mtval] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data; /*
* write mtval if new_priv=M_MODE, spec says:
* When a hardware breakpoint is triggered, or an instruction-fetch, load,
* or store address-misaligned,
* access, or page-fault exception occurs, mtval is written with the
* faulting effective address.
*/
switch(cause){
case 0:
csr[mtval] = static_cast<reg_t>(addr);
break;
case 2:
csr[mtval] = (instr & 0x3)==3?instr:instr&0xffff;
break;
case 3:
//TODO: implement debug mode behavior
// csr[dpc] = addr;
// csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
csr[mtval] = 0;
break;
case 4:
case 6:
csr[mtval] = fault_data;
break;
default:
csr[mtval] = 0;
}
fault_data = 0; fault_data = 0;
} else { } else {
csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
@ -948,7 +1051,11 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
this->reg.PRIV = PRIV_M; this->reg.PRIV = PRIV_M;
this->reg.trap_state = 0; this->reg.trap_state = 0;
std::array<char, 32> buffer; std::array<char, 32> buffer;
#if defined(_MSC_VER)
sprintf(buffer.data(), "0x%016llx", addr);
#else
sprintf(buffer.data(), "0x%016lx", addr); sprintf(buffer.data(), "0x%016lx", addr);
#endif
if((flags&0xffffffff) != 0xffffffff) if((flags&0xffffffff) != 0xffffffff)
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
@ -956,7 +1063,7 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
return this->reg.NEXT_PC; return this->reg.NEXT_PC;
} }
template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) { template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::leave_trap(uint64_t flags) {
state.mstatus.MIE = state.mstatus.MPIE; state.mstatus.MIE = state.mstatus.MPIE;
state.mstatus.MPIE = 1; state.mstatus.MPIE = 1;
// sets the pc to the value stored in the x epc register. // sets the pc to the value stored in the x epc register.

10
incl/iss/arch/riscv_hart_msu_vp.h
View File

@ -145,7 +145,7 @@ public:
mstatus_t mstatus; mstatus_t mstatus;
static const reg_t mstatus_reset_val = 0; static const reg_t mstatus_reset_val = 0x1800;
void write_mstatus(T val, unsigned priv_lvl) { void write_mstatus(T val, unsigned priv_lvl) {
auto mask = get_mask(priv_lvl); auto mask = get_mask(priv_lvl);
@ -398,7 +398,7 @@ private:
iss::status read_ip(unsigned addr, reg_t &val); iss::status read_ip(unsigned addr, reg_t &val);
iss::status write_ip(unsigned addr, reg_t val); iss::status write_ip(unsigned addr, reg_t val);
iss::status read_hartid(unsigned addr, reg_t &val); iss::status read_hartid(unsigned addr, reg_t &val);
iss::status write_mepc(unsigned addr, reg_t val); iss::status write_epc(unsigned addr, reg_t val);
iss::status read_satp(unsigned addr, reg_t &val); iss::status read_satp(unsigned addr, reg_t &val);
iss::status write_satp(unsigned addr, reg_t val); iss::status write_satp(unsigned addr, reg_t val);
iss::status read_fcsr(unsigned addr, reg_t &val); iss::status read_fcsr(unsigned addr, reg_t &val);
@ -419,7 +419,7 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
// reset values // reset values
csr[misa] = traits<BASE>::MISA_VAL; csr[misa] = traits<BASE>::MISA_VAL;
csr[mvendorid] = 0x669; csr[mvendorid] = 0x669;
csr[marchid] = 0x80000003; csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1; csr[mimpid] = 1;
uart_buf.str(""); uart_buf.str("");
@ -954,8 +954,8 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ip(unsigned
return iss::Ok; return iss::Ok;
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_epc(unsigned addr, reg_t val) { template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_epc(unsigned addr, reg_t val) {
csr[addr] = val & get_pc_mask(); csr[addr] = val & get_pc_mask();
return iss::Ok; return iss::Ok;
} }

198
incl/iss/arch/riscv_hart_mu_p.h
View File

@ -66,8 +66,6 @@
namespace iss { namespace iss {
namespace arch { namespace arch {
enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N, FEAT_CLIC};
template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_mu_p : public BASE { template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_mu_p : public BASE {
protected: protected:
const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}}; const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
@ -146,7 +144,7 @@ public:
mstatus_t mstatus; mstatus_t mstatus;
static const reg_t mstatus_reset_val = 0; static const reg_t mstatus_reset_val = 0x1800; // MPP set to 1
void write_mstatus(T val, unsigned priv_lvl) { void write_mstatus(T val, unsigned priv_lvl) {
auto mask = get_mask(priv_lvl); auto mask = get_mask(priv_lvl);
@ -183,7 +181,7 @@ public:
}; };
using hart_state_type = hart_state<reg_t>; using hart_state_type = hart_state<reg_t>;
constexpr reg_t get_irq_wrmask(size_t mode) { constexpr reg_t get_irq_mask(size_t mode) {
std::array<const reg_t, 4> m = {{ std::array<const reg_t, 4> m = {{
0b000100010001, // U mode 0b000100010001, // U mode
0b001100110011, // S mode 0b001100110011, // S mode
@ -304,7 +302,6 @@ protected:
}; };
std::vector<clic_int_reg_t> clic_int_reg; std::vector<clic_int_reg_t> clic_int_reg;
private:
iss::status read_csr_reg(unsigned addr, reg_t &val); iss::status read_csr_reg(unsigned addr, reg_t &val);
iss::status write_csr_reg(unsigned addr, reg_t val); iss::status write_csr_reg(unsigned addr, reg_t val);
iss::status read_null(unsigned addr, reg_t &val); iss::status read_null(unsigned addr, reg_t &val);
@ -328,18 +325,23 @@ private:
iss::status write_epc(unsigned addr, reg_t val); iss::status write_epc(unsigned addr, reg_t val);
iss::status write_intstatus(unsigned addr, reg_t val); iss::status write_intstatus(unsigned addr, reg_t val);
iss::status write_intthresh(unsigned addr, reg_t val); iss::status write_intthresh(unsigned addr, reg_t val);
iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
iss::status read_dcsr_reg(unsigned addr, reg_t &val);
iss::status write_dcsr_reg(unsigned addr, reg_t val);
iss::status read_dpc_reg(unsigned addr, reg_t &val);
iss::status write_dpc_reg(unsigned addr, reg_t val);
reg_t mhartid_reg{0x0}; reg_t mhartid_reg{0x0};
std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb; std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb; std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
protected:
void check_interrupt(); void check_interrupt();
bool pmp_check(const access_type type, const uint64_t addr, const unsigned len); bool pmp_check(const access_type type, const uint64_t addr, const unsigned len);
uint64_t clic_base_addr{0}; uint64_t clic_base_addr{0};
unsigned clic_num_irq{0}; unsigned clic_num_irq{0};
unsigned clic_num_trigger{0}; unsigned clic_num_trigger{0};
unsigned mcause_max_irq{16}; unsigned mcause_max_irq{16};
inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
}; };
template <typename BASE, features_e FEAT> template <typename BASE, features_e FEAT>
@ -349,7 +351,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
// reset values // reset values
csr[misa] = traits<BASE>::MISA_VAL; csr[misa] = traits<BASE>::MISA_VAL;
csr[mvendorid] = 0x669; csr[mvendorid] = 0x669;
csr[marchid] = 0x80000004; csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1; csr[mimpid] = 1;
csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file
@ -464,6 +466,16 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq; clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq;
mcause_max_irq=clic_num_irq+16; mcause_max_irq=clic_num_irq+16;
} }
if(FEAT & FEAT_DEBUG){
csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg;
csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg;
csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg;
csr_wr_cb[dpc] = &this_class::write_dpc_reg;
csr_rd_cb[dpc] = &this_class::read_dpc_reg;
csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
}
} }
template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) { template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) {
@ -493,7 +505,7 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
traits<BASE>::MEM, pseg->get_physical_address(), traits<BASE>::MEM, pseg->get_physical_address(),
fsize, reinterpret_cast<const uint8_t *const>(seg_data)); fsize, reinterpret_cast<const uint8_t *const>(seg_data));
if (res != iss::Ok) if (res != iss::Ok)
LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex
<< pseg->get_physical_address(); << pseg->get_physical_address();
} }
} }
@ -543,25 +555,27 @@ template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_
constexpr auto PMP_NA4 =0x2U; constexpr auto PMP_NA4 =0x2U;
constexpr auto PMP_NAPOT =0x3U; constexpr auto PMP_NAPOT =0x3U;
reg_t base = 0; reg_t base = 0;
auto any_active = false;
for (size_t i = 0; i < 16; i++) { for (size_t i = 0; i < 16; i++) {
reg_t tor = csr[pmpaddr0+i] << PMP_SHIFT; reg_t tor = csr[pmpaddr0+i] << PMP_SHIFT;
uint8_t cfg = csr[pmpcfg0+(i/4)]>>(i%4); uint8_t cfg = csr[pmpcfg0+(i/4)]>>(i%4);
if (cfg & PMP_A) { if (cfg & PMP_A) {
any_active=true;
auto pmp_a = (cfg & PMP_A) >> 3; auto pmp_a = (cfg & PMP_A) >> 3;
bool is_tor = pmp_a == PMP_TOR; auto is_tor = pmp_a == PMP_TOR;
bool is_na4 = pmp_a == PMP_NA4; auto is_na4 = pmp_a == PMP_NA4;
reg_t mask = (csr[pmpaddr0+i] << 1) | (!is_na4); reg_t mask = (csr[pmpaddr0+i] << 1) | (!is_na4);
mask = ~(mask & ~(mask + 1)) << PMP_SHIFT; mask = ~(mask & ~(mask + 1)) << PMP_SHIFT;
// Check each 4-byte sector of the access // Check each 4-byte sector of the access
bool any_match = false; auto any_match = false;
bool all_match = true; auto all_match = true;
for (reg_t offset = 0; offset < len; offset += 1 << PMP_SHIFT) { for (reg_t offset = 0; offset < len; offset += 1 << PMP_SHIFT) {
reg_t cur_addr = addr + offset; reg_t cur_addr = addr + offset;
bool napot_match = ((cur_addr ^ tor) & mask) == 0; auto napot_match = ((cur_addr ^ tor) & mask) == 0;
bool tor_match = base <= cur_addr && cur_addr < tor; auto tor_match = base <= cur_addr && cur_addr < tor;
bool match = is_tor ? tor_match : napot_match; auto match = is_tor ? tor_match : napot_match;
any_match |= match; any_match |= match;
all_match &= match; all_match &= match;
} }
@ -577,7 +591,38 @@ template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_
} }
base = tor; base = tor;
} }
return this->reg.PRIV == PRIV_M; // constexpr auto pmp_num_regs = 16;
// reg_t tor_base = 0;
// auto any_active = false;
// auto lower_addr = addr >>2;
// auto upper_addr = (addr+len-1)>>2;
// for (size_t i = 0; i < pmp_num_regs; i++) {
// uint8_t cfg = csr[pmpcfg0+(i/4)]>>(i%4);
// uint8_t cfg_next = i==(pmp_num_regs-1)? 0 : csr[pmpcfg0+((i+1)/4)]>>((i+1)%4);
// auto pmpaddr = csr[pmpaddr0+i];
// if (cfg & PMP_A) {
// any_active=true;
// auto is_tor = bit_sub<3, 2>(cfg) == PMP_TOR;
// auto is_napot = bit_sub<4, 1>(cfg) && bit_sub<3, 2>(cfg_next)!= PMP_TOR;
// if(is_napot) {
// reg_t mask = bit_sub<3, 1>(cfg)?~( pmpaddr & ~(pmpaddr + 1)): 0x3fffffff;
// auto mpmpaddr = pmpaddr & mask;
// if((lower_addr&mask) == mpmpaddr && (upper_addr&mask)==mpmpaddr)
// return (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) ||
// (type == access_type::READ && (cfg & PMP_R)) ||
// (type == access_type::WRITE && (cfg & PMP_W)) ||
// (type == access_type::FETCH && (cfg & PMP_X));
// } else if(is_tor) {
// if(lower_addr>=tor_base && upper_addr<=pmpaddr)
// return (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) ||
// (type == access_type::READ && (cfg & PMP_R)) ||
// (type == access_type::WRITE && (cfg & PMP_W)) ||
// (type == access_type::FETCH && (cfg & PMP_X));
// }
// }
// tor_base = pmpaddr;
// }
return !any_active || this->reg.PRIV == PRIV_M;
} }
@ -917,7 +962,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ie(unsigned addr, reg_t &val) {
auto mask = get_irq_wrmask((addr >> 8) & 0x3); auto mask = get_irq_mask((addr >> 8) & 0x3);
val = csr[mie] & mask; val = csr[mie] & mask;
if(this->reg.PRIV!=3) if(this->reg.PRIV!=3)
val &= csr[mideleg]; val &= csr[mideleg];
@ -925,16 +970,14 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
auto mask = get_irq_wrmask((addr >> 8) & 0x3); auto mask = get_irq_mask((addr >> 8) & 0x3);
if(this->reg.PRIV==0)
mask&= ~(0xff<<4); // STIE and UTIE are read only in user and supervisor mode
csr[mie] = (csr[mie] & ~mask) | (val & mask); csr[mie] = (csr[mie] & ~mask) | (val & mask);
check_interrupt(); check_interrupt();
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ip(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_ip(unsigned addr, reg_t &val) {
auto mask = get_irq_wrmask((addr >> 8) & 0x3); auto mask = get_irq_mask((addr >> 8) & 0x3);
val = csr[mip] & mask; val = csr[mip] & mask;
if(this->reg.PRIV!=3) if(this->reg.PRIV!=3)
val &= csr[mideleg]; val &= csr[mideleg];
@ -942,10 +985,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ip(unsigned addr, reg_t val) {
auto mask = get_irq_wrmask((addr >> 8) & 0x3); auto mask = get_irq_mask((addr >> 8) & 0x3);
mask &= ~(8 << 4); // MTIP is read only mask &= 0xf; // only xSIP is writable
if(this->reg.PRIV!=3)
mask &= ~(3 << 4); // STIP and UTIP are read only in user and supervisor mode
csr[mip] = (csr[mip] & ~mask) | (val & mask); csr[mip] = (csr[mip] & ~mask) | (val & mask);
check_interrupt(); check_interrupt();
return iss::Ok; return iss::Ok;
@ -968,6 +1009,45 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr_dcsr(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
// +-------------- ebreakm
// | +---------- stepi
// | | +++----- cause
// | | ||| +- step
csr[addr] = val & 0b1000100111000100U;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_dcsr_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
val = csr[addr];
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dcsr_reg(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
csr[addr] = val;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_dpc_reg(unsigned addr, reg_t &val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
val = this->reg.DPC;
return iss::Ok;
}
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_dpc_reg(unsigned addr, reg_t val) {
if(!debug_mode_active())
throw illegal_instruction_fault(this->fault_data);
this->reg.DPC = val;
return iss::Ok;
}
template<typename BASE, features_e FEAT> template<typename BASE, features_e FEAT>
iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) { iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val) {
csr[addr]= val &0xff; csr[addr]= val &0xff;
@ -1203,7 +1283,27 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
* access, or page-fault exception occurs, mtval is written with the * access, or page-fault exception occurs, mtval is written with the
* faulting effective address. * faulting effective address.
*/ */
csr[utval | (new_priv << 8)] = cause==2?((instr & 0x3)==3?instr:instr&0xffff):fault_data; switch(cause){
case 0:
csr[utval | (new_priv << 8)] = static_cast<reg_t>(addr);
break;
case 2:
csr[utval | (new_priv << 8)] = (instr & 0x3)==3?instr:instr&0xffff;
break;
case 3:
//TODO: implement debug mode behavior
// csr[dpc] = addr;
// csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
csr[utval | (new_priv << 8)] = 0;
break;
case 4:
case 6:
case 7:
csr[utval | (new_priv << 8)] = fault_data;
break;
default:
csr[utval | (new_priv << 8)] = 0;
}
fault_data = 0; fault_data = 0;
} else { } else {
if (this->reg.PRIV != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0) if (this->reg.PRIV != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0)
@ -1256,27 +1356,33 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::leave_trap(uint64_t flags) { template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::leave_trap(uint64_t flags) {
auto cur_priv = this->reg.PRIV; auto cur_priv = this->reg.PRIV;
auto inst_priv = (flags & 0x3)? 3:0; auto inst_priv = (flags & 0x3)? 3:0;
auto status = state.mstatus; if(inst_priv>cur_priv){
// pop the relevant lower-privilege interrupt enable and privilege mode stack auto trap_val = 0x80ULL << 24 | (2 << 16); // illegal instruction
// clear respective yIE this->reg.trap_state = trap_val;
switch (inst_priv) { this->reg.NEXT_PC = std::numeric_limits<uint32_t>::max();
case PRIV_M: } else {
this->reg.PRIV = state.mstatus.MPP; auto status = state.mstatus;
state.mstatus.MPP = 0; // clear mpp to U mode // pop the relevant lower-privilege interrupt enable and privilege mode stack
state.mstatus.MIE = state.mstatus.MPIE; // clear respective yIE
state.mstatus.MPIE = 1; switch (inst_priv) {
break; case PRIV_M:
case PRIV_U: this->reg.PRIV = state.mstatus.MPP;
this->reg.PRIV = 0; state.mstatus.MPP = 0; // clear mpp to U mode
state.mstatus.UIE = state.mstatus.UPIE; state.mstatus.MIE = state.mstatus.MPIE;
state.mstatus.UPIE = 1; state.mstatus.MPIE = 1;
break; break;
case PRIV_U:
this->reg.PRIV = 0;
state.mstatus.UIE = state.mstatus.UPIE;
state.mstatus.UPIE = 1;
break;
}
// sets the pc to the value stored in the x epc register.
this->reg.NEXT_PC = csr[uepc | inst_priv << 8];
CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to "
<< lvl[this->reg.PRIV];
check_interrupt();
} }
// sets the pc to the value stored in the x epc register.
this->reg.NEXT_PC = csr[uepc | inst_priv << 8];
CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to "
<< lvl[this->reg.PRIV];
check_interrupt();
return this->reg.NEXT_PC; return this->reg.NEXT_PC;
} }

119
incl/iss/arch/tgc_c.h
View File

@ -47,18 +47,18 @@ template <> struct traits<tgc_c> {
constexpr static char const* const core_type = "TGC_C"; constexpr static char const* const core_type = "TGC_C";
static constexpr std::array<const char*, 35> reg_names{ static constexpr std::array<const char*, 36> reg_names{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}}; {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
static constexpr std::array<const char*, 35> reg_aliases{ static constexpr std::array<const char*, 36> reg_aliases{
{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}}; {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64}; enum constants {MISA_VAL=0b01000000000000000001000100000100, MARCHID_VAL=0x80000003, XLEN=32, CSR_SIZE=4096, INSTR_ALIGNMENT=2, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64};
constexpr static unsigned FP_REGS_SIZE = 0; constexpr static unsigned FP_REGS_SIZE = 0;
enum reg_e { enum reg_e {
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, NUM_REGS, X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS,
TRAP_STATE=NUM_REGS, TRAP_STATE=NUM_REGS,
PENDING_TRAP, PENDING_TRAP,
ICOUNT, ICOUNT,
@ -76,11 +76,11 @@ template <> struct traits<tgc_c> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>; using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 40> reg_bit_widths{ static constexpr std::array<const uint32_t, 41> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,64,64,64}}; {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64}};
static constexpr std::array<const uint32_t, 40> reg_byte_offsets{ static constexpr std::array<const uint32_t, 41> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,153,161}}; {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
@ -133,50 +133,52 @@ template <> struct traits<tgc_c> {
SRET = 41, SRET = 41,
MRET = 42, MRET = 42,
WFI = 43, WFI = 43,
CSRRW = 44, DRET = 44,
CSRRS = 45, CSRRW = 45,
CSRRC = 46, CSRRS = 46,
CSRRWI = 47, CSRRC = 47,
CSRRSI = 48, CSRRWI = 48,
CSRRCI = 49, CSRRSI = 49,
MUL = 50, CSRRCI = 50,
MULH = 51, FENCE_I = 51,
MULHSU = 52, MUL = 52,
MULHU = 53, MULH = 53,
DIV = 54, MULHSU = 54,
DIVU = 55, MULHU = 55,
REM = 56, DIV = 56,
REMU = 57, DIVU = 57,
CADDI4SPN = 58, REM = 58,
CLW = 59, REMU = 59,
CSW = 60, CADDI4SPN = 60,
CADDI = 61, CLW = 61,
CNOP = 62, CSW = 62,
CJAL = 63, CADDI = 63,
CLI = 64, CNOP = 64,
CLUI = 65, CJAL = 65,
CADDI16SP = 66, CLI = 66,
__reserved_clui = 67, CLUI = 67,
CSRLI = 68, CADDI16SP = 68,
CSRAI = 69, __reserved_clui = 69,
CANDI = 70, CSRLI = 70,
CSUB = 71, CSRAI = 71,
CXOR = 72, CANDI = 72,
COR = 73, CSUB = 73,
CAND = 74, CXOR = 74,
CJ = 75, COR = 75,
CBEQZ = 76, CAND = 76,
CBNEZ = 77, CJ = 77,
CSLLI = 78, CBEQZ = 78,
CLWSP = 79, CBNEZ = 79,
CMV = 80, CSLLI = 80,
CJR = 81, CLWSP = 81,
__reserved_cmv = 82, CMV = 82,
CADD = 83, CJR = 83,
CJALR = 84, __reserved_cmv = 84,
CEBREAK = 85, CADD = 85,
CSWSP = 86, CJALR = 86,
DII = 87, CEBREAK = 87,
CSWSP = 88,
DII = 89,
MAX_OPCODE MAX_OPCODE
}; };
}; };
@ -194,14 +196,6 @@ struct tgc_c: public arch_if {
void reset(uint64_t address=0) override; void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override; uint8_t* get_regs_base_ptr() override;
/// deprecated
void get_reg(short idx, std::vector<uint8_t>& value) override {}
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
bool get_flag(int flag) override {return false;}
void set_flag(int, bool value) override {};
/// deprecated
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
inline uint64_t get_icount() { return reg.icount; } inline uint64_t get_icount() { return reg.icount; }
@ -261,6 +255,7 @@ protected:
uint32_t PC = 0; uint32_t PC = 0;
uint32_t NEXT_PC = 0; uint32_t NEXT_PC = 0;
uint8_t PRIV = 0; uint8_t PRIV = 0;
uint32_t DPC = 0;
uint32_t trap_state = 0, pending_trap = 0; uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0; uint64_t icount = 0;
uint64_t cycle = 0; uint64_t cycle = 0;

9
incl/sysc/core_complex.h
View File

@ -48,6 +48,9 @@
#include <util/range_lut.h> #include <util/range_lut.h>
#include <memory> #include <memory>
namespace iss {
class vm_plugin;
}
namespace sysc { namespace sysc {
class tlm_dmi_ext : public tlm::tlm_dmi { class tlm_dmi_ext : public tlm::tlm_dmi {
@ -99,6 +102,8 @@ public:
cci::cci_param<uint32_t> mhartid{"mhartid", 0}; cci::cci_param<uint32_t> mhartid{"mhartid", 0};
cci::cci_param<std::string> plugins{"plugins", ""};
core_complex(sc_core::sc_module_name const& name); core_complex(sc_core::sc_module_name const& name);
#else #else
@ -122,6 +127,8 @@ public:
scml_property<uint32_t> mhartid{"mhartid", 0}; scml_property<uint32_t> mhartid{"mhartid", 0};
scml_property<std::string> plugins{"plugins", ""};
core_complex(sc_core::sc_module_name const& name) core_complex(sc_core::sc_module_name const& name)
: sc_module(name) : sc_module(name)
, local_irq_i{"local_irq_i", 16} , local_irq_i{"local_irq_i", 16}
@ -185,6 +192,8 @@ protected:
std::unique_ptr<scc::tick2time> t2t; std::unique_ptr<scc::tick2time> t2t;
private: private:
void init(); void init();
std::vector<iss::vm_plugin *> plugin_list;
}; };
} /* namespace SiFive */ } /* namespace SiFive */
} /* namespace sysc */ } /* namespace sysc */

2
softfloat/build/Linux-x86_64-GCC/platform.h
View File

@ -49,7 +49,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
#ifdef __GNUC__
#define SOFTFLOAT_BUILTIN_CLZ 1 #define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_INTRINSIC_INT128 1 #define SOFTFLOAT_INTRINSIC_INT128 1
#endif
#include "opts-GCC.h" #include "opts-GCC.h"

12
src/iss/tgc_c.cpp
View File

@ -39,10 +39,10 @@
using namespace iss::arch; using namespace iss::arch;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgc_c>::reg_names; constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_names;
constexpr std::array<const char*, 35> iss::arch::traits<iss::arch::tgc_c>::reg_aliases; constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths; constexpr std::array<const uint32_t, 41> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets; constexpr std::array<const uint32_t, 41> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
tgc_c::tgc_c() { tgc_c::tgc_c() {
reg.icount = 0; reg.icount = 0;
@ -51,7 +51,9 @@ tgc_c::tgc_c() {
tgc_c::~tgc_c() = default; tgc_c::~tgc_c() = default;
void tgc_c::reset(uint64_t address) { void tgc_c::reset(uint64_t address) {
for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<tgc_c>::reg_t),0)); auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
*(base_ptr+i)=0;
reg.PC=address; reg.PC=address;
reg.NEXT_PC=reg.PC; reg.NEXT_PC=reg.PC;
reg.PRIV=0x3; reg.PRIV=0x3;

31
src/main.cpp
View File

@ -49,12 +49,21 @@ using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
#include "iss/arch/tgc_d.h" #include "iss/arch/tgc_d.h"
using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>; using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif #endif
#ifdef CORE_TGC_D_XRB_MAC
#include "iss/arch/riscv_hart_mu_p.h"
#include "iss/arch/tgc_d_xrb_mac.h"
using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
#endif
#ifdef WITH_LLVM #ifdef WITH_LLVM
#include <iss/llvm/jit_helper.h> #include <iss/llvm/jit_helper.h>
#endif #endif
#include <iss/log_categories.h> #include <iss/log_categories.h>
#include <iss/plugin/cycle_estimate.h> #include <iss/plugin/cycle_estimate.h>
#include <iss/plugin/instruction_count.h> #include <iss/plugin/instruction_count.h>
#include <iss/plugin/loader.h>
#if defined(HAS_LUA)
#include <iss/plugin/lua.h>
#endif
namespace po = boost::program_options; namespace po = boost::program_options;
@ -138,9 +147,15 @@ int main(int argc, char *argv[]) {
std::tie(cpu, vm) = std::tie(cpu, vm) =
iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>()); iss::create_cpu<tgc_d_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else } else
#endif
#ifdef CORE_TGC_D_XRB_MAC
if (isa_opt == "tgc_d_xrb_mac") {
std::tie(cpu, vm) =
iss::create_cpu<tgc_d_xrb_mac_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
} else
#endif #endif
{ {
LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl; LOG(ERR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
return 127; return 127;
} }
if (clim.count("plugin")) { if (clim.count("plugin")) {
@ -161,8 +176,16 @@ int main(int argc, char *argv[]) {
vm->register_plugin(*ce_plugin); vm->register_plugin(*ce_plugin);
plugin_list.push_back(ce_plugin); plugin_list.push_back(ce_plugin);
} else { } else {
LOG(ERROR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl; std::array<char const*, 1> a{{filename.c_str()}};
return 127; iss::plugin::loader l(plugin_name, {{"initPlugin"}});
auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
if(plugin){
vm->register_plugin(*plugin);
plugin_list.push_back(plugin);
} else {
LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
return 127;
}
} }
} }
} }
@ -196,7 +219,7 @@ int main(int argc, char *argv[]) {
auto cycles = clim["instructions"].as<uint64_t>(); auto cycles = clim["instructions"].as<uint64_t>();
res = vm->start(cycles, dump); res = vm->start(cycles, dump);
} catch (std::exception &e) { } catch (std::exception &e) {
LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
<< std::endl; << std::endl;
res = 2; res = 2;
} }

821
src/plugin/GCOV.cpp
View File

@ -1,821 +0,0 @@
//===- GCOV.cpp - LLVM coverage tool --------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// GCOV implements the interface to read and write coverage files that use
// 'gcov' format.
//
//===----------------------------------------------------------------------===//
#include "GCOV.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/Path.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <system_error>
using namespace llvm;
//===----------------------------------------------------------------------===//
// GCOVFile implementation.
/// readGCNO - Read GCNO buffer.
bool GCOVFile::readGCNO(GCOVBuffer &Buffer) {
if (!Buffer.readGCNOFormat())
return false;
if (!Buffer.readGCOVVersion(Version))
return false;
if (!Buffer.readInt(Checksum))
return false;
while (true) {
if (!Buffer.readFunctionTag())
break;
auto GFun = make_unique<GCOVFunction>(*this);
if (!GFun->readGCNO(Buffer, Version))
return false;
Functions.push_back(std::move(GFun));
}
GCNOInitialized = true;
return true;
}
/// readGCDA - Read GCDA buffer. It is required that readGCDA() can only be
/// called after readGCNO().
bool GCOVFile::readGCDA(GCOVBuffer &Buffer) {
assert(GCNOInitialized && "readGCDA() can only be called after readGCNO()");
if (!Buffer.readGCDAFormat())
return false;
GCOV::GCOVVersion GCDAVersion;
if (!Buffer.readGCOVVersion(GCDAVersion))
return false;
if (Version != GCDAVersion) {
errs() << "GCOV versions do not match.\n";
return false;
}
uint32_t GCDAChecksum;
if (!Buffer.readInt(GCDAChecksum))
return false;
if (Checksum != GCDAChecksum) {
errs() << "File checksums do not match: " << Checksum
<< " != " << GCDAChecksum << ".\n";
return false;
}
for (size_t i = 0, e = Functions.size(); i < e; ++i) {
if (!Buffer.readFunctionTag()) {
errs() << "Unexpected number of functions.\n";
return false;
}
if (!Functions[i]->readGCDA(Buffer, Version))
return false;
}
if (Buffer.readObjectTag()) {
uint32_t Length;
uint32_t Dummy;
if (!Buffer.readInt(Length))
return false;
if (!Buffer.readInt(Dummy))
return false; // checksum
if (!Buffer.readInt(Dummy))
return false; // num
if (!Buffer.readInt(RunCount))
return false;
Buffer.advanceCursor(Length - 3);
}
while (Buffer.readProgramTag()) {
uint32_t Length;
if (!Buffer.readInt(Length))
return false;
Buffer.advanceCursor(Length);
++ProgramCount;
}
return true;
}
void GCOVFile::print(raw_ostream &OS) const {
for (const auto &FPtr : Functions)
FPtr->print(OS);
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// dump - Dump GCOVFile content to dbgs() for debugging purposes.
LLVM_DUMP_METHOD void GCOVFile::dump() const {
print(dbgs());
}
#endif
/// collectLineCounts - Collect line counts. This must be used after
/// reading .gcno and .gcda files.
void GCOVFile::collectLineCounts(FileInfo &FI) {
for (const auto &FPtr : Functions)
FPtr->collectLineCounts(FI);
FI.setRunCount(RunCount);
FI.setProgramCount(ProgramCount);
}
//===----------------------------------------------------------------------===//
// GCOVFunction implementation.
/// readGCNO - Read a function from the GCNO buffer. Return false if an error
/// occurs.
bool GCOVFunction::readGCNO(GCOVBuffer &Buff, GCOV::GCOVVersion Version) {
uint32_t Dummy;
if (!Buff.readInt(Dummy))
return false; // Function header length
if (!Buff.readInt(Ident))
return false;
if (!Buff.readInt(Checksum))
return false;
if (Version != GCOV::V402) {
uint32_t CfgChecksum;
if (!Buff.readInt(CfgChecksum))
return false;
if (Parent.getChecksum() != CfgChecksum) {
errs() << "File checksums do not match: " << Parent.getChecksum()
<< " != " << CfgChecksum << " in (" << Name << ").\n";
return false;
}
}
if (!Buff.readString(Name))
return false;
if (!Buff.readString(Filename))
return false;
if (!Buff.readInt(LineNumber))
return false;
// read blocks.
if (!Buff.readBlockTag()) {
errs() << "Block tag not found.\n";
return false;
}
uint32_t BlockCount;
if (!Buff.readInt(BlockCount))
return false;
for (uint32_t i = 0, e = BlockCount; i != e; ++i) {
if (!Buff.readInt(Dummy))
return false; // Block flags;
Blocks.push_back(make_unique<GCOVBlock>(*this, i));
}
// read edges.
while (Buff.readEdgeTag()) {
uint32_t EdgeCount;
if (!Buff.readInt(EdgeCount))
return false;
EdgeCount = (EdgeCount - 1) / 2;
uint32_t BlockNo;
if (!Buff.readInt(BlockNo))
return false;
if (BlockNo >= BlockCount) {
errs() << "Unexpected block number: " << BlockNo << " (in " << Name
<< ").\n";
return false;
}
for (uint32_t i = 0, e = EdgeCount; i != e; ++i) {
uint32_t Dst;
if (!Buff.readInt(Dst))
return false;
Edges.push_back(make_unique<GCOVEdge>(*Blocks[BlockNo], *Blocks[Dst]));
GCOVEdge *Edge = Edges.back().get();
Blocks[BlockNo]->addDstEdge(Edge);
Blocks[Dst]->addSrcEdge(Edge);
if (!Buff.readInt(Dummy))
return false; // Edge flag
}
}
// read line table.
while (Buff.readLineTag()) {
uint32_t LineTableLength;
// Read the length of this line table.
if (!Buff.readInt(LineTableLength))
return false;
uint32_t EndPos = Buff.getCursor() + LineTableLength * 4;
uint32_t BlockNo;
// Read the block number this table is associated with.
if (!Buff.readInt(BlockNo))
return false;
if (BlockNo >= BlockCount) {
errs() << "Unexpected block number: " << BlockNo << " (in " << Name
<< ").\n";
return false;
}
GCOVBlock &Block = *Blocks[BlockNo];
// Read the word that pads the beginning of the line table. This may be a
// flag of some sort, but seems to always be zero.
if (!Buff.readInt(Dummy))
return false;
// Line information starts here and continues up until the last word.
if (Buff.getCursor() != (EndPos - sizeof(uint32_t))) {
StringRef F;
// Read the source file name.
if (!Buff.readString(F))
return false;
if (Filename != F) {
errs() << "Multiple sources for a single basic block: " << Filename
<< " != " << F << " (in " << Name << ").\n";
return false;
}
// Read lines up to, but not including, the null terminator.
while (Buff.getCursor() < (EndPos - 2 * sizeof(uint32_t))) {
uint32_t Line;
if (!Buff.readInt(Line))
return false;
// Line 0 means this instruction was injected by the compiler. Skip it.
if (!Line)
continue;
Block.addLine(Line);
}
// Read the null terminator.
if (!Buff.readInt(Dummy))
return false;
}
// The last word is either a flag or padding, it isn't clear which. Skip
// over it.
if (!Buff.readInt(Dummy))
return false;
}
return true;
}
/// readGCDA - Read a function from the GCDA buffer. Return false if an error
/// occurs.
bool GCOVFunction::readGCDA(GCOVBuffer &Buff, GCOV::GCOVVersion Version) {
uint32_t HeaderLength;
if (!Buff.readInt(HeaderLength))
return false; // Function header length
uint64_t EndPos = Buff.getCursor() + HeaderLength * sizeof(uint32_t);
uint32_t GCDAIdent;
if (!Buff.readInt(GCDAIdent))
return false;
if (Ident != GCDAIdent) {
errs() << "Function identifiers do not match: " << Ident
<< " != " << GCDAIdent << " (in " << Name << ").\n";
return false;
}
uint32_t GCDAChecksum;
if (!Buff.readInt(GCDAChecksum))
return false;
if (Checksum != GCDAChecksum) {
errs() << "Function checksums do not match: " << Checksum
<< " != " << GCDAChecksum << " (in " << Name << ").\n";
return false;
}
uint32_t CfgChecksum;
if (Version != GCOV::V402) {
if (!Buff.readInt(CfgChecksum))
return false;
if (Parent.getChecksum() != CfgChecksum) {
errs() << "File checksums do not match: " << Parent.getChecksum()
<< " != " << CfgChecksum << " (in " << Name << ").\n";
return false;
}
}
if (Buff.getCursor() < EndPos) {
StringRef GCDAName;
if (!Buff.readString(GCDAName))
return false;
if (Name != GCDAName) {
errs() << "Function names do not match: " << Name << " != " << GCDAName
<< ".\n";
return false;
}
}
if (!Buff.readArcTag()) {
errs() << "Arc tag not found (in " << Name << ").\n";
return false;
}
uint32_t Count;
if (!Buff.readInt(Count))
return false;
Count /= 2;
// This for loop adds the counts for each block. A second nested loop is
// required to combine the edge counts that are contained in the GCDA file.
for (uint32_t BlockNo = 0; Count > 0; ++BlockNo) {
// The last block is always reserved for exit block
if (BlockNo >= Blocks.size()) {
errs() << "Unexpected number of edges (in " << Name << ").\n";
return false;
}
if (BlockNo == Blocks.size() - 1)
errs() << "(" << Name << ") has arcs from exit block.\n";
GCOVBlock &Block = *Blocks[BlockNo];
for (size_t EdgeNo = 0, End = Block.getNumDstEdges(); EdgeNo < End;
++EdgeNo) {
if (Count == 0) {
errs() << "Unexpected number of edges (in " << Name << ").\n";
return false;
}
uint64_t ArcCount;
if (!Buff.readInt64(ArcCount))
return false;
Block.addCount(EdgeNo, ArcCount);
--Count;
}
Block.sortDstEdges();
}
return true;
}
/// getEntryCount - Get the number of times the function was called by
/// retrieving the entry block's count.
uint64_t GCOVFunction::getEntryCount() const {
return Blocks.front()->getCount();
}
/// getExitCount - Get the number of times the function returned by retrieving
/// the exit block's count.
uint64_t GCOVFunction::getExitCount() const {
return Blocks.back()->getCount();
}
void GCOVFunction::print(raw_ostream &OS) const {
OS << "===== " << Name << " (" << Ident << ") @ " << Filename << ":"
<< LineNumber << "\n";
for (const auto &Block : Blocks)
Block->print(OS);
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// dump - Dump GCOVFunction content to dbgs() for debugging purposes.
LLVM_DUMP_METHOD void GCOVFunction::dump() const {
print(dbgs());
}
#endif
/// collectLineCounts - Collect line counts. This must be used after
/// reading .gcno and .gcda files.
void GCOVFunction::collectLineCounts(FileInfo &FI) {
// If the line number is zero, this is a function that doesn't actually appear
// in the source file, so there isn't anything we can do with it.
if (LineNumber == 0)
return;
for (const auto &Block : Blocks)
Block->collectLineCounts(FI);
FI.addFunctionLine(Filename, LineNumber, this);
}
//===----------------------------------------------------------------------===//
// GCOVBlock implementation.
/// ~GCOVBlock - Delete GCOVBlock and its content.
GCOVBlock::~GCOVBlock() {
SrcEdges.clear();
DstEdges.clear();
Lines.clear();
}
/// addCount - Add to block counter while storing the edge count. If the
/// destination has no outgoing edges, also update that block's count too.
void GCOVBlock::addCount(size_t DstEdgeNo, uint64_t N) {
assert(DstEdgeNo < DstEdges.size()); // up to caller to ensure EdgeNo is valid
DstEdges[DstEdgeNo]->Count = N;
Counter += N;
if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges())
DstEdges[DstEdgeNo]->Dst.Counter += N;
}
/// sortDstEdges - Sort destination edges by block number, nop if already
/// sorted. This is required for printing branch info in the correct order.
void GCOVBlock::sortDstEdges() {
if (!DstEdgesAreSorted) {
SortDstEdgesFunctor SortEdges;
std::stable_sort(DstEdges.begin(), DstEdges.end(), SortEdges);
}
}
/// collectLineCounts - Collect line counts. This must be used after
/// reading .gcno and .gcda files.
void GCOVBlock::collectLineCounts(FileInfo &FI) {
for (uint32_t N : Lines)
FI.addBlockLine(Parent.getFilename(), N, this);
}
void GCOVBlock::print(raw_ostream &OS) const {
OS << "Block : " << Number << " Counter : " << Counter << "\n";
if (!SrcEdges.empty()) {
OS << "\tSource Edges : ";
for (const GCOVEdge *Edge : SrcEdges)
OS << Edge->Src.Number << " (" << Edge->Count << "), ";
OS << "\n";
}
if (!DstEdges.empty()) {
OS << "\tDestination Edges : ";
for (const GCOVEdge *Edge : DstEdges)
OS << Edge->Dst.Number << " (" << Edge->Count << "), ";
OS << "\n";
}
if (!Lines.empty()) {
OS << "\tLines : ";
for (uint32_t N : Lines)
OS << (N) << ",";
OS << "\n";
}
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// dump - Dump GCOVBlock content to dbgs() for debugging purposes.
LLVM_DUMP_METHOD void GCOVBlock::dump() const {
print(dbgs());
}
#endif
//===----------------------------------------------------------------------===//
// FileInfo implementation.
// Safe integer division, returns 0 if numerator is 0.
static uint32_t safeDiv(uint64_t Numerator, uint64_t Divisor) {
if (!Numerator)
return 0;
return Numerator / Divisor;
}
// This custom division function mimics gcov's branch ouputs:
// - Round to closest whole number
// - Only output 0% or 100% if it's exactly that value
static uint32_t branchDiv(uint64_t Numerator, uint64_t Divisor) {
if (!Numerator)
return 0;
if (Numerator == Divisor)
return 100;
uint8_t Res = (Numerator * 100 + Divisor / 2) / Divisor;
if (Res == 0)
return 1;
if (Res == 100)
return 99;
return Res;
}
namespace {
struct formatBranchInfo {
formatBranchInfo(const GCOV::Options &Options, uint64_t Count, uint64_t Total)
: Options(Options), Count(Count), Total(Total) {}
void print(raw_ostream &OS) const {
if (!Total)
OS << "never executed";
else if (Options.BranchCount)
OS << "taken " << Count;
else
OS << "taken " << branchDiv(Count, Total) << "%";
}
const GCOV::Options &Options;
uint64_t Count;
uint64_t Total;
};
static raw_ostream &operator<<(raw_ostream &OS, const formatBranchInfo &FBI) {
FBI.print(OS);
return OS;
}
class LineConsumer {
std::unique_ptr<MemoryBuffer> Buffer;
StringRef Remaining;
public:
LineConsumer(StringRef Filename) {
ErrorOr<std::unique_ptr<MemoryBuffer>> BufferOrErr =
MemoryBuffer::getFileOrSTDIN(Filename);
if (std::error_code EC = BufferOrErr.getError()) {
errs() << Filename << ": " << EC.message() << "\n";
Remaining = "";
} else {
Buffer = std::move(BufferOrErr.get());
Remaining = Buffer->getBuffer();
}
}
bool empty() { return Remaining.empty(); }
void printNext(raw_ostream &OS, uint32_t LineNum) {
StringRef Line;
if (empty())
Line = "/*EOF*/";
else
std::tie(Line, Remaining) = Remaining.split("\n");
OS << format("%5u:", LineNum) << Line << "\n";
}
};
} // end anonymous namespace
/// Convert a path to a gcov filename. If PreservePaths is true, this
/// translates "/" to "#", ".." to "^", and drops ".", to match gcov.
static std::string mangleCoveragePath(StringRef Filename, bool PreservePaths) {
if (!PreservePaths)
return sys::path::filename(Filename).str();
// This behaviour is defined by gcov in terms of text replacements, so it's
// not likely to do anything useful on filesystems with different textual
// conventions.
llvm::SmallString<256> Result("");
StringRef::iterator I, S, E;
for (I = S = Filename.begin(), E = Filename.end(); I != E; ++I) {
if (*I != '/')
continue;
if (I - S == 1 && *S == '.') {
// ".", the current directory, is skipped.
} else if (I - S == 2 && *S == '.' && *(S + 1) == '.') {
// "..", the parent directory, is replaced with "^".
Result.append("^#");
} else {
if (S < I)
// Leave other components intact,
Result.append(S, I);
// And separate with "#".
Result.push_back('#');
}
S = I + 1;
}
if (S < I)
Result.append(S, I);
return Result.str();
}
std::string FileInfo::getCoveragePath(StringRef Filename,
StringRef MainFilename) {
if (Options.NoOutput)
// This is probably a bug in gcov, but when -n is specified, paths aren't
// mangled at all, and the -l and -p options are ignored. Here, we do the
// same.
return Filename;
std::string CoveragePath;
if (Options.LongFileNames && !Filename.equals(MainFilename))
CoveragePath =
mangleCoveragePath(MainFilename, Options.PreservePaths) + "##";
CoveragePath += mangleCoveragePath(Filename, Options.PreservePaths) + ".gcov";
return CoveragePath;
}
std::unique_ptr<raw_ostream>
FileInfo::openCoveragePath(StringRef CoveragePath) {
if (Options.NoOutput)
return llvm::make_unique<raw_null_ostream>();
std::error_code EC;
auto OS = llvm::make_unique<raw_fd_ostream>(CoveragePath, EC,
sys::fs::F_Text);
if (EC) {
errs() << EC.message() << "\n";
return llvm::make_unique<raw_null_ostream>();
}
return std::move(OS);
}
/// print - Print source files with collected line count information.
void FileInfo::print(raw_ostream &InfoOS, StringRef MainFilename,
StringRef GCNOFile, StringRef GCDAFile) {
SmallVector<StringRef, 4> Filenames;
for (const auto &LI : LineInfo)
Filenames.push_back(LI.first());
std::sort(Filenames.begin(), Filenames.end());
for (StringRef Filename : Filenames) {
auto AllLines = LineConsumer(Filename);
std::string CoveragePath = getCoveragePath(Filename, MainFilename);
std::unique_ptr<raw_ostream> CovStream = openCoveragePath(CoveragePath);
raw_ostream &CovOS = *CovStream;
CovOS << " -: 0:Source:" << Filename << "\n";
CovOS << " -: 0:Graph:" << GCNOFile << "\n";
CovOS << " -: 0:Data:" << GCDAFile << "\n";
CovOS << " -: 0:Runs:" << RunCount << "\n";
CovOS << " -: 0:Programs:" << ProgramCount << "\n";
const LineData &Line = LineInfo[Filename];
GCOVCoverage FileCoverage(Filename);
for (uint32_t LineIndex = 0; LineIndex < Line.LastLine || !AllLines.empty();
++LineIndex) {
if (Options.BranchInfo) {
FunctionLines::const_iterator FuncsIt = Line.Functions.find(LineIndex);
if (FuncsIt != Line.Functions.end())
printFunctionSummary(CovOS, FuncsIt->second);
}
BlockLines::const_iterator BlocksIt = Line.Blocks.find(LineIndex);
if (BlocksIt == Line.Blocks.end()) {
// No basic blocks are on this line. Not an executable line of code.
CovOS << " -:";
AllLines.printNext(CovOS, LineIndex + 1);
} else {
const BlockVector &Blocks = BlocksIt->second;
// Add up the block counts to form line counts.
DenseMap<const GCOVFunction *, bool> LineExecs;
uint64_t LineCount = 0;
for (const GCOVBlock *Block : Blocks) {
if (Options.AllBlocks) {
// Only take the highest block count for that line.
uint64_t BlockCount = Block->getCount();
LineCount = LineCount > BlockCount ? LineCount : BlockCount;
} else {
// Sum up all of the block counts.
LineCount += Block->getCount();
}
if (Options.FuncCoverage) {
// This is a slightly convoluted way to most accurately gather line
// statistics for functions. Basically what is happening is that we
// don't want to count a single line with multiple blocks more than
// once. However, we also don't simply want to give the total line
// count to every function that starts on the line. Thus, what is
// happening here are two things:
// 1) Ensure that the number of logical lines is only incremented
// once per function.
// 2) If there are multiple blocks on the same line, ensure that the
// number of lines executed is incremented as long as at least
// one of the blocks are executed.
const GCOVFunction *Function = &Block->getParent();
if (FuncCoverages.find(Function) == FuncCoverages.end()) {
std::pair<const GCOVFunction *, GCOVCoverage> KeyValue(
Function, GCOVCoverage(Function->getName()));
FuncCoverages.insert(KeyValue);
}
GCOVCoverage &FuncCoverage = FuncCoverages.find(Function)->second;
if (LineExecs.find(Function) == LineExecs.end()) {
if (Block->getCount()) {
++FuncCoverage.LinesExec;
LineExecs[Function] = true;
} else {
LineExecs[Function] = false;
}
++FuncCoverage.LogicalLines;
} else if (!LineExecs[Function] && Block->getCount()) {
++FuncCoverage.LinesExec;
LineExecs[Function] = true;
}
}
}
if (LineCount == 0)
CovOS << " #####:";
else {
CovOS << format("%9" PRIu64 ":", LineCount);
++FileCoverage.LinesExec;
}
++FileCoverage.LogicalLines;
AllLines.printNext(CovOS, LineIndex + 1);
uint32_t BlockNo = 0;
uint32_t EdgeNo = 0;
for (const GCOVBlock *Block : Blocks) {
// Only print block and branch information at the end of the block.
if (Block->getLastLine() != LineIndex + 1)
continue;
if (Options.AllBlocks)
printBlockInfo(CovOS, *Block, LineIndex, BlockNo);
if (Options.BranchInfo) {
size_t NumEdges = Block->getNumDstEdges();
if (NumEdges > 1)
printBranchInfo(CovOS, *Block, FileCoverage, EdgeNo);
else if (Options.UncondBranch && NumEdges == 1)
printUncondBranchInfo(CovOS, EdgeNo,
(*Block->dst_begin())->Count);
}
}
}
}
FileCoverages.push_back(std::make_pair(CoveragePath, FileCoverage));
}
// FIXME: There is no way to detect calls given current instrumentation.
if (Options.FuncCoverage)
printFuncCoverage(InfoOS);
printFileCoverage(InfoOS);
}
/// printFunctionSummary - Print function and block summary.
void FileInfo::printFunctionSummary(raw_ostream &OS,
const FunctionVector &Funcs) const {
for (const GCOVFunction *Func : Funcs) {
uint64_t EntryCount = Func->getEntryCount();
uint32_t BlocksExec = 0;
for (const GCOVBlock &Block : Func->blocks())
if (Block.getNumDstEdges() && Block.getCount())
++BlocksExec;
OS << "function " << Func->getName() << " called " << EntryCount
<< " returned " << safeDiv(Func->getExitCount() * 100, EntryCount)
<< "% blocks executed "
<< safeDiv(BlocksExec * 100, Func->getNumBlocks() - 1) << "%\n";
}
}
/// printBlockInfo - Output counts for each block.
void FileInfo::printBlockInfo(raw_ostream &OS, const GCOVBlock &Block,
uint32_t LineIndex, uint32_t &BlockNo) const {
if (Block.getCount() == 0)
OS << " $$$$$:";
else
OS << format("%9" PRIu64 ":", Block.getCount());
OS << format("%5u-block %2u\n", LineIndex + 1, BlockNo++);
}
/// printBranchInfo - Print conditional branch probabilities.
void FileInfo::printBranchInfo(raw_ostream &OS, const GCOVBlock &Block,
GCOVCoverage &Coverage, uint32_t &EdgeNo) {
SmallVector<uint64_t, 16> BranchCounts;
uint64_t TotalCounts = 0;
for (const GCOVEdge *Edge : Block.dsts()) {
BranchCounts.push_back(Edge->Count);
TotalCounts += Edge->Count;
if (Block.getCount())
++Coverage.BranchesExec;
if (Edge->Count)
++Coverage.BranchesTaken;
++Coverage.Branches;
if (Options.FuncCoverage) {
const GCOVFunction *Function = &Block.getParent();
GCOVCoverage &FuncCoverage = FuncCoverages.find(Function)->second;
if (Block.getCount())
++FuncCoverage.BranchesExec;
if (Edge->Count)
++FuncCoverage.BranchesTaken;
++FuncCoverage.Branches;
}
}
for (uint64_t N : BranchCounts)
OS << format("branch %2u ", EdgeNo++)
<< formatBranchInfo(Options, N, TotalCounts) << "\n";
}
/// printUncondBranchInfo - Print unconditional branch probabilities.
void FileInfo::printUncondBranchInfo(raw_ostream &OS, uint32_t &EdgeNo,
uint64_t Count) const {
OS << format("unconditional %2u ", EdgeNo++)
<< formatBranchInfo(Options, Count, Count) << "\n";
}
// printCoverage - Print generic coverage info used by both printFuncCoverage
// and printFileCoverage.
void FileInfo::printCoverage(raw_ostream &OS,
const GCOVCoverage &Coverage) const {
OS << format("Lines executed:%.2f%% of %u\n",
double(Coverage.LinesExec) * 100 / Coverage.LogicalLines,
Coverage.LogicalLines);
if (Options.BranchInfo) {
if (Coverage.Branches) {
OS << format("Branches executed:%.2f%% of %u\n",
double(Coverage.BranchesExec) * 100 / Coverage.Branches,
Coverage.Branches);
OS << format("Taken at least once:%.2f%% of %u\n",
double(Coverage.BranchesTaken) * 100 / Coverage.Branches,
Coverage.Branches);
} else {
OS << "No branches\n";
}
OS << "No calls\n"; // to be consistent with gcov
}
}
// printFuncCoverage - Print per-function coverage info.
void FileInfo::printFuncCoverage(raw_ostream &OS) const {
for (const auto &FC : FuncCoverages) {
const GCOVCoverage &Coverage = FC.second;
OS << "Function '" << Coverage.Name << "'\n";
printCoverage(OS, Coverage);
OS << "\n";
}
}
// printFileCoverage - Print per-file coverage info.
void FileInfo::printFileCoverage(raw_ostream &OS) const {
for (const auto &FC : FileCoverages) {
const std::string &Filename = FC.first;
const GCOVCoverage &Coverage = FC.second;
OS << "File '" << Coverage.Name << "'\n";
printCoverage(OS, Coverage);
if (!Options.NoOutput)
OS << Coverage.Name << ":creating '" << Filename << "'\n";
OS << "\n";
}
}

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src/plugin/GCOV.h
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@ -1,460 +0,0 @@
//===- GCOV.h - LLVM coverage tool ------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This header provides the interface to read and write coverage files that
// use 'gcov' format.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_PROFILEDATA_GCOV_H
#define LLVM_PROFILEDATA_GCOV_H
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/iterator.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <cstddef>
#include <cstdint>
#include <memory>
#include <string>
#include <utility>
namespace llvm {
class GCOVFunction;
class GCOVBlock;
class FileInfo;
namespace GCOV {
enum GCOVVersion { V402, V404, V704 };
/// \brief A struct for passing gcov options between functions.
struct Options {
Options(bool A, bool B, bool C, bool F, bool P, bool U, bool L, bool N)
: AllBlocks(A), BranchInfo(B), BranchCount(C), FuncCoverage(F),
PreservePaths(P), UncondBranch(U), LongFileNames(L), NoOutput(N) {}
bool AllBlocks;
bool BranchInfo;
bool BranchCount;
bool FuncCoverage;
bool PreservePaths;
bool UncondBranch;
bool LongFileNames;
bool NoOutput;
};
} // end namespace GCOV
/// GCOVBuffer - A wrapper around MemoryBuffer to provide GCOV specific
/// read operations.
class GCOVBuffer {
public:
GCOVBuffer(MemoryBuffer *B) : Buffer(B) {}
/// readGCNOFormat - Check GCNO signature is valid at the beginning of buffer.
bool readGCNOFormat() {
StringRef File = Buffer->getBuffer().slice(0, 4);
if (File != "oncg") {
errs() << "Unexpected file type: " << File << ".\n";
return false;
}
Cursor = 4;
return true;
}
/// readGCDAFormat - Check GCDA signature is valid at the beginning of buffer.
bool readGCDAFormat() {
StringRef File = Buffer->getBuffer().slice(0, 4);
if (File != "adcg") {
errs() << "Unexpected file type: " << File << ".\n";
return false;
}
Cursor = 4;
return true;
}
/// readGCOVVersion - Read GCOV version.
bool readGCOVVersion(GCOV::GCOVVersion &Version) {
StringRef VersionStr = Buffer->getBuffer().slice(Cursor, Cursor + 4);
if (VersionStr == "*204") {
Cursor += 4;
Version = GCOV::V402;
return true;
}
if (VersionStr == "*404") {
Cursor += 4;
Version = GCOV::V404;
return true;
}
if (VersionStr == "*704") {
Cursor += 4;
Version = GCOV::V704;
return true;
}
errs() << "Unexpected version: " << VersionStr << ".\n";
return false;
}
/// readFunctionTag - If cursor points to a function tag then increment the
/// cursor and return true otherwise return false.
bool readFunctionTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
Tag[3] != '\1') {
return false;
}
Cursor += 4;
return true;
}
/// readBlockTag - If cursor points to a block tag then increment the
/// cursor and return true otherwise return false.
bool readBlockTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x41' ||
Tag[3] != '\x01') {
return false;
}
Cursor += 4;
return true;
}
/// readEdgeTag - If cursor points to an edge tag then increment the
/// cursor and return true otherwise return false.
bool readEdgeTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x43' ||
Tag[3] != '\x01') {
return false;
}
Cursor += 4;
return true;
}
/// readLineTag - If cursor points to a line tag then increment the
/// cursor and return true otherwise return false.
bool readLineTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x45' ||
Tag[3] != '\x01') {
return false;
}
Cursor += 4;
return true;
}
/// readArcTag - If cursor points to an gcda arc tag then increment the
/// cursor and return true otherwise return false.
bool readArcTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\xa1' ||
Tag[3] != '\1') {
return false;
}
Cursor += 4;
return true;
}
/// readObjectTag - If cursor points to an object summary tag then increment
/// the cursor and return true otherwise return false.
bool readObjectTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
Tag[3] != '\xa1') {
return false;
}
Cursor += 4;
return true;
}
/// readProgramTag - If cursor points to a program summary tag then increment
/// the cursor and return true otherwise return false.
bool readProgramTag() {
StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4);
if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' ||
Tag[3] != '\xa3') {
return false;
}
Cursor += 4;
return true;
}
bool readInt(uint32_t &Val) {
if (Buffer->getBuffer().size() < Cursor + 4) {
errs() << "Unexpected end of memory buffer: " << Cursor + 4 << ".\n";
return false;
}
StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor + 4);
Cursor += 4;
Val = *(const uint32_t *)(Str.data());
return true;
}
bool readInt64(uint64_t &Val) {
uint32_t Lo, Hi;
if (!readInt(Lo) || !readInt(Hi))
return false;
Val = ((uint64_t)Hi << 32) | Lo;
return true;
}
bool readString(StringRef &Str) {
uint32_t Len = 0;
// Keep reading until we find a non-zero length. This emulates gcov's
// behaviour, which appears to do the same.
while (Len == 0)
if (!readInt(Len))
return false;
Len *= 4;
if (Buffer->getBuffer().size() < Cursor + Len) {
errs() << "Unexpected end of memory buffer: " << Cursor + Len << ".\n";
return false;
}
Str = Buffer->getBuffer().slice(Cursor, Cursor + Len).split('\0').first;
Cursor += Len;
return true;
}
uint64_t getCursor() const { return Cursor; }
void advanceCursor(uint32_t n) { Cursor += n * 4; }
private:
MemoryBuffer *Buffer;
uint64_t Cursor = 0;
};
/// GCOVFile - Collects coverage information for one pair of coverage file
/// (.gcno and .gcda).
class GCOVFile {
public:
GCOVFile() = default;
bool readGCNO(GCOVBuffer &Buffer);
bool readGCDA(GCOVBuffer &Buffer);
uint32_t getChecksum() const { return Checksum; }
void print(raw_ostream &OS) const;
void dump() const;
void collectLineCounts(FileInfo &FI);
private:
bool GCNOInitialized = false;
GCOV::GCOVVersion Version;
uint32_t Checksum = 0;
SmallVector<std::unique_ptr<GCOVFunction>, 16> Functions;
uint32_t RunCount = 0;
uint32_t ProgramCount = 0;
};
/// GCOVEdge - Collects edge information.
struct GCOVEdge {
GCOVEdge(GCOVBlock &S, GCOVBlock &D) : Src(S), Dst(D) {}
GCOVBlock &Src;
GCOVBlock &Dst;
uint64_t Count = 0;
};
/// GCOVFunction - Collects function information.
class GCOVFunction {
public:
using BlockIterator = pointee_iterator<SmallVectorImpl<
std::unique_ptr<GCOVBlock>>::const_iterator>;
GCOVFunction(GCOVFile &P) : Parent(P) {}
bool readGCNO(GCOVBuffer &Buffer, GCOV::GCOVVersion Version);
bool readGCDA(GCOVBuffer &Buffer, GCOV::GCOVVersion Version);
StringRef getName() const { return Name; }
StringRef getFilename() const { return Filename; }
size_t getNumBlocks() const { return Blocks.size(); }
uint64_t getEntryCount() const;
uint64_t getExitCount() const;
BlockIterator block_begin() const { return Blocks.begin(); }
BlockIterator block_end() const { return Blocks.end(); }
iterator_range<BlockIterator> blocks() const {
return make_range(block_begin(), block_end());
}
void print(raw_ostream &OS) const;
void dump() const;
void collectLineCounts(FileInfo &FI);
private:
GCOVFile &Parent;
uint32_t Ident = 0;
uint32_t Checksum;
uint32_t LineNumber = 0;
StringRef Name;
StringRef Filename;
SmallVector<std::unique_ptr<GCOVBlock>, 16> Blocks;
SmallVector<std::unique_ptr<GCOVEdge>, 16> Edges;
};
/// GCOVBlock - Collects block information.
class GCOVBlock {
struct EdgeWeight {
EdgeWeight(GCOVBlock *D) : Dst(D) {}
GCOVBlock *Dst;
uint64_t Count = 0;
};
struct SortDstEdgesFunctor {
bool operator()(const GCOVEdge *E1, const GCOVEdge *E2) {
return E1->Dst.Number < E2->Dst.Number;
}
};
public:
using EdgeIterator = SmallVectorImpl<GCOVEdge *>::const_iterator;
GCOVBlock(GCOVFunction &P, uint32_t N) : Parent(P), Number(N) {}
~GCOVBlock();
const GCOVFunction &getParent() const { return Parent; }
void addLine(uint32_t N) { Lines.push_back(N); }
uint32_t getLastLine() const { return Lines.back(); }
void addCount(size_t DstEdgeNo, uint64_t N);
uint64_t getCount() const { return Counter; }
void addSrcEdge(GCOVEdge *Edge) {
assert(&Edge->Dst == this); // up to caller to ensure edge is valid
SrcEdges.push_back(Edge);
}
void addDstEdge(GCOVEdge *Edge) {
assert(&Edge->Src == this); // up to caller to ensure edge is valid
// Check if adding this edge causes list to become unsorted.
if (DstEdges.size() && DstEdges.back()->Dst.Number > Edge->Dst.Number)
DstEdgesAreSorted = false;
DstEdges.push_back(Edge);
}
size_t getNumSrcEdges() const { return SrcEdges.size(); }
size_t getNumDstEdges() const { return DstEdges.size(); }
void sortDstEdges();
EdgeIterator src_begin() const { return SrcEdges.begin(); }
EdgeIterator src_end() const { return SrcEdges.end(); }
iterator_range<EdgeIterator> srcs() const {
return make_range(src_begin(), src_end());
}
EdgeIterator dst_begin() const { return DstEdges.begin(); }
EdgeIterator dst_end() const { return DstEdges.end(); }
iterator_range<EdgeIterator> dsts() const {
return make_range(dst_begin(), dst_end());
}
void print(raw_ostream &OS) const;
void dump() const;
void collectLineCounts(FileInfo &FI);
private:
GCOVFunction &Parent;
uint32_t Number;
uint64_t Counter = 0;
bool DstEdgesAreSorted = true;
SmallVector<GCOVEdge *, 16> SrcEdges;
SmallVector<GCOVEdge *, 16> DstEdges;
SmallVector<uint32_t, 16> Lines;
};
class FileInfo {
// It is unlikely--but possible--for multiple functions to be on the same
// line.
// Therefore this typedef allows LineData.Functions to store multiple
// functions
// per instance. This is rare, however, so optimize for the common case.
using FunctionVector = SmallVector<const GCOVFunction *, 1>;
using FunctionLines = DenseMap<uint32_t, FunctionVector>;
using BlockVector = SmallVector<const GCOVBlock *, 4>;
using BlockLines = DenseMap<uint32_t, BlockVector>;
struct LineData {
LineData() = default;
BlockLines Blocks;
FunctionLines Functions;
uint32_t LastLine = 0;
};
struct GCOVCoverage {
GCOVCoverage(StringRef Name) : Name(Name) {}
StringRef Name;
uint32_t LogicalLines = 0;
uint32_t LinesExec = 0;
uint32_t Branches = 0;
uint32_t BranchesExec = 0;
uint32_t BranchesTaken = 0;
};
public:
FileInfo(const GCOV::Options &Options) : Options(Options) {}
void addBlockLine(StringRef Filename, uint32_t Line, const GCOVBlock *Block) {
if (Line > LineInfo[Filename].LastLine)
LineInfo[Filename].LastLine = Line;
LineInfo[Filename].Blocks[Line - 1].push_back(Block);
}
void addFunctionLine(StringRef Filename, uint32_t Line,
const GCOVFunction *Function) {
if (Line > LineInfo[Filename].LastLine)
LineInfo[Filename].LastLine = Line;
LineInfo[Filename].Functions[Line - 1].push_back(Function);
}
void setRunCount(uint32_t Runs) { RunCount = Runs; }
void setProgramCount(uint32_t Programs) { ProgramCount = Programs; }
void print(raw_ostream &OS, StringRef MainFilename, StringRef GCNOFile,
StringRef GCDAFile);
private:
std::string getCoveragePath(StringRef Filename, StringRef MainFilename);
std::unique_ptr<raw_ostream> openCoveragePath(StringRef CoveragePath);
void printFunctionSummary(raw_ostream &OS, const FunctionVector &Funcs) const;
void printBlockInfo(raw_ostream &OS, const GCOVBlock &Block,
uint32_t LineIndex, uint32_t &BlockNo) const;
void printBranchInfo(raw_ostream &OS, const GCOVBlock &Block,
GCOVCoverage &Coverage, uint32_t &EdgeNo);
void printUncondBranchInfo(raw_ostream &OS, uint32_t &EdgeNo,
uint64_t Count) const;
void printCoverage(raw_ostream &OS, const GCOVCoverage &Coverage) const;
void printFuncCoverage(raw_ostream &OS) const;
void printFileCoverage(raw_ostream &OS) const;
const GCOV::Options &Options;
StringMap<LineData> LineInfo;
uint32_t RunCount = 0;
uint32_t ProgramCount = 0;
using FileCoverageList = SmallVector<std::pair<std::string, GCOVCoverage>, 4>;
using FuncCoverageMap = MapVector<const GCOVFunction *, GCOVCoverage>;
FileCoverageList FileCoverages;
FuncCoverageMap FuncCoverages;
};
} // end namespace llvm
#endif // LLVM_SUPPORT_GCOV_H

12
src/plugin/cycle_estimate.cpp
View File

@ -47,10 +47,10 @@ iss::plugin::cycle_estimate::cycle_estimate(std::string config_file_name)
try { try {
is >> root; is >> root;
} catch (Json::RuntimeError &e) { } catch (Json::RuntimeError &e) {
LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
} }
} else { } else {
LOG(ERROR) << "Could not open input file " << config_file_name; LOG(ERR) << "Could not open input file " << config_file_name;
} }
} }
} }
@ -77,7 +77,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
} }
} }
} else { } else {
LOG(ERROR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl; LOG(ERR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
} }
return true; return true;
@ -87,6 +87,8 @@ void iss::plugin::cycle_estimate::callback(instr_info_t instr_info, exec_info co
assert(arch_instr && "No instrumentation interface available but callback executed"); assert(arch_instr && "No instrumentation interface available but callback executed");
auto entry = delays[instr_info.instr_id]; auto entry = delays[instr_info.instr_id];
bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8); bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
uint32_t delay = taken ? entry.taken : entry.not_taken; if (taken && entry.taken > 1)
if(delay>1) arch_instr->set_curr_instr_cycles(delay); arch_instr->set_curr_instr_cycles(entry.taken);
else if (entry.not_taken > 1)
arch_instr->set_curr_instr_cycles(entry.not_taken);
} }

6
src/plugin/instruction_count.cpp
View File

@ -46,10 +46,10 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
try { try {
is >> root; is >> root;
} catch (Json::RuntimeError &e) { } catch (Json::RuntimeError &e) {
LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
} }
} else { } else {
LOG(ERROR) << "Could not open input file " << config_file_name; LOG(ERR) << "Could not open input file " << config_file_name;
} }
} }
} }
@ -85,7 +85,7 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
} }
rep_counts.resize(delays.size()); rep_counts.resize(delays.size());
} else { } else {
LOG(ERROR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl; LOG(ERR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
} }
return true; return true;
} }

71
src/sysc/core_complex.cpp
View File

@ -30,6 +30,14 @@
* *
*******************************************************************************/ *******************************************************************************/
// clang-format off
#include "iss/debugger/gdb_session.h"
#include "iss/debugger/encoderdecoder.h"
#include "iss/debugger/server.h"
#include "iss/debugger/target_adapter_if.h"
#include "iss/iss.h"
#include "iss/vm_types.h"
#include <iss/plugin/loader.h>
#include "sysc/core_complex.h" #include "sysc/core_complex.h"
#ifdef CORE_TGC_B #ifdef CORE_TGC_B
#include "iss/arch/riscv_hart_m_p.h" #include "iss/arch/riscv_hart_m_p.h"
@ -44,22 +52,25 @@ using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
#include "iss/arch/tgc_d.h" #include "iss/arch/tgc_d.h"
using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>; using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::FEAT_PMP>;
#endif #endif
#include "iss/debugger/encoderdecoder.h" #ifdef CORE_TGC_D_XRB_MAC
#include "iss/debugger/gdb_session.h" #include "iss/arch/riscv_hart_mu_p.h"
#include "iss/debugger/server.h" #include "iss/arch/tgc_d_xrb_mac.h"
#include "iss/debugger/target_adapter_if.h" using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, iss::arch::FEAT_PMP>;
#include "iss/iss.h" #endif
#include "iss/vm_types.h" #include <scc/report.h>
#include "scc/report.h" #include <util/ities.h>
#include <iostream> #include <iostream>
#include <sstream> #include <sstream>
#include <array> #include <array>
#include <iss/plugin/cycle_estimate.h>
#include <iss/plugin/instruction_count.h>
// clang-format on
#define STR(X) #X #define STR(X) #X
#define CREATE_CORE(CN) \ #define CREATE_CORE(CN) \
if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else if (type == STR(CN)) { std::tie(cpu, vm) = create_core<CN ## _plat_type>(backend, gdb_port, hart_id); } else
#ifdef WITH_SCV #ifdef HAS_SCV
#include <scv.h> #include <scv.h>
#else #else
#include <scv-tr.h> #include <scv-tr.h>
@ -72,6 +83,12 @@ using namespace scv_tr;
#define GET_PROP_VALUE(P) P.getValue() #define GET_PROP_VALUE(P) P.getValue()
#endif #endif
#ifdef _MSC_VER
// not #if defined(_WIN32) || defined(_WIN64) because we have strncasecmp in mingw
#define strncasecmp _strnicmp
#define strcasecmp _stricmp
#endif
namespace sysc { namespace sysc {
namespace tgfs { namespace tgfs {
using namespace std; using namespace std;
@ -285,9 +302,12 @@ public:
#endif #endif
#ifdef CORE_TGC_D #ifdef CORE_TGC_D
CREATE_CORE(tgc_d) CREATE_CORE(tgc_d)
#endif
#ifdef CORE_TGC_D_XRB_MACD
CREATE_CORE(tgc_d_xrb_mac)
#endif #endif
{ {
LOG(ERROR) << "Illegal argument value for core type: " << type << std::endl; LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;
} }
auto *srv = debugger::server<debugger::gdb_session>::get(); auto *srv = debugger::server<debugger::gdb_session>::get();
if (srv) tgt_adapter = srv->get_target(); if (srv) tgt_adapter = srv->get_target();
@ -364,6 +384,8 @@ void core_complex::init(){
core_complex::~core_complex(){ core_complex::~core_complex(){
delete cpu; delete cpu;
delete trc; delete trc;
for (auto *p : plugin_list)
delete p;
} }
void core_complex::trace(sc_trace_file *trf) const {} void core_complex::trace(sc_trace_file *trf) const {}
@ -375,6 +397,37 @@ void core_complex::before_end_of_elaboration() {
cpu->create_cpu(GET_PROP_VALUE(core_type), GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid)); cpu->create_cpu(GET_PROP_VALUE(core_type), GET_PROP_VALUE(backend), GET_PROP_VALUE(gdb_server_port), GET_PROP_VALUE(mhartid));
sc_assert(cpu->vm!=nullptr); sc_assert(cpu->vm!=nullptr);
cpu->vm->setDisassEnabled(GET_PROP_VALUE(enable_disass) || trc->m_db != nullptr); cpu->vm->setDisassEnabled(GET_PROP_VALUE(enable_disass) || trc->m_db != nullptr);
if (GET_PROP_VALUE(plugins).length()) {
auto p = util::split(GET_PROP_VALUE(plugins), ';');
for (std::string const& opt_val : p) {
std::string plugin_name=opt_val;
std::string filename{"cycles.txt"};
std::size_t found = opt_val.find('=');
if (found != std::string::npos) {
plugin_name = opt_val.substr(0, found);
filename = opt_val.substr(found + 1, opt_val.size());
}
if (plugin_name == "ic") {
auto *plugin = new iss::plugin::instruction_count(filename);
cpu->vm->register_plugin(*plugin);
plugin_list.push_back(plugin);
} else if (plugin_name == "ce") {
auto *plugin = new iss::plugin::cycle_estimate(filename);
cpu->vm->register_plugin(*plugin);
plugin_list.push_back(plugin);
} else {
std::array<char const*, 1> a{{filename.c_str()}};
iss::plugin::loader l(plugin_name, {{"initPlugin"}});
auto* plugin = l.call_function<iss::vm_plugin*>("initPlugin", a.size(), a.data());
if(plugin){
cpu->vm->register_plugin(*plugin);
plugin_list.push_back(plugin);
} else
SCCERR(SCMOD) << "Unknown plugin '" << plugin_name << "' or plugin not found";
}
}
}
} }
void core_complex::start_of_simulation() { void core_complex::start_of_simulation() {

428
src/vm/interp/vm_tgc_c.cpp
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