renames core(s)
This commit is contained in:
parent
0b719a4b57
commit
c8a4a4c736
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@ -31,13 +31,13 @@ add_subdirectory(softfloat)
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set(LIB_SOURCES
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src/iss/plugin/instruction_count.cpp
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src/iss/arch/tgc_c.cpp
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src/vm/tcc/vm_tgc_c.cpp
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src/vm/interp/vm_tgc_c.cpp
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src/iss/arch/tgc5c.cpp
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src/vm/tcc/vm_tgc5c.cpp
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src/vm/interp/vm_tgc5c.cpp
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src/vm/fp_functions.cpp
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)
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if(WITH_TCC)
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list(APPEND LIB_SOURCES src/vm/tcc/vm_tgc_c.cpp)
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list(APPEND LIB_SOURCES src/vm/tcc/vm_tgc5c.cpp)
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endif()
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# library files
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@ -1,8 +1,8 @@
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import "ISA/RV32I.core_desc"
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import "ISA/RVI.core_desc"
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import "ISA/RVM.core_desc"
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import "ISA/RVC.core_desc"
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Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
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Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
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architectural_state {
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XLEN=32;
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// definitions for the architecture wrapper
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@ -30,7 +30,7 @@
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*
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*******************************************************************************/
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#include "tgc_c.h"
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#include "tgc5c.h"
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#include "util/ities.h"
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#include <util/logging.h>
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#include <cstdio>
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@ -39,18 +39,18 @@
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using namespace iss::arch;
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constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_names;
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constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
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constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
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constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
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constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc5c>::reg_names;
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constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc5c>::reg_aliases;
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constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_bit_widths;
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constexpr std::array<const uint32_t, 43> iss::arch::traits<iss::arch::tgc5c>::reg_byte_offsets;
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tgc_c::tgc_c() = default;
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tgc5c::tgc5c() = default;
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tgc_c::~tgc_c() = default;
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tgc5c::~tgc5c() = default;
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void tgc_c::reset(uint64_t address) {
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auto base_ptr = reinterpret_cast<traits<tgc_c>::reg_t*>(get_regs_base_ptr());
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for(size_t i=0; i<traits<tgc_c>::NUM_REGS; ++i)
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void tgc5c::reset(uint64_t address) {
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auto base_ptr = reinterpret_cast<traits<tgc5c>::reg_t*>(get_regs_base_ptr());
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for(size_t i=0; i<traits<tgc5c>::NUM_REGS; ++i)
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*(base_ptr+i)=0;
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reg.PC=address;
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reg.NEXT_PC=reg.PC;
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@ -59,11 +59,11 @@ void tgc_c::reset(uint64_t address) {
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reg.icount=0;
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}
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uint8_t *tgc_c::get_regs_base_ptr() {
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uint8_t *tgc5c::get_regs_base_ptr() {
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return reinterpret_cast<uint8_t*>(®);
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}
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tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) {
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tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &pc) {
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return phys_addr_t(pc); // change logical address to physical address
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}
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@ -30,8 +30,8 @@
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*
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*******************************************************************************/
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#ifndef _TGC_C_H_
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#define _TGC_C_H_
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#ifndef _TGC5C_H_
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#define _TGC5C_H_
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#include <array>
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#include <iss/arch/traits.h>
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@ -41,11 +41,11 @@
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namespace iss {
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namespace arch {
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struct tgc_c;
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struct tgc5c;
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template <> struct traits<tgc_c> {
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template <> struct traits<tgc5c> {
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constexpr static char const* const core_type = "TGC_C";
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constexpr static char const* const core_type = "TGC5C";
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static constexpr std::array<const char*, 36> reg_names{
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{"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}};
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@ -175,15 +175,15 @@ template <> struct traits<tgc_c> {
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};
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};
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struct tgc_c: public arch_if {
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struct tgc5c: public arch_if {
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using virt_addr_t = typename traits<tgc_c>::virt_addr_t;
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using phys_addr_t = typename traits<tgc_c>::phys_addr_t;
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using reg_t = typename traits<tgc_c>::reg_t;
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using addr_t = typename traits<tgc_c>::addr_t;
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using virt_addr_t = typename traits<tgc5c>::virt_addr_t;
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using phys_addr_t = typename traits<tgc5c>::phys_addr_t;
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using reg_t = typename traits<tgc5c>::reg_t;
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using addr_t = typename traits<tgc5c>::addr_t;
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tgc_c();
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~tgc_c();
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tgc5c();
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~tgc5c();
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void reset(uint64_t address=0) override;
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@ -196,9 +196,9 @@ struct tgc_c: public arch_if {
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inline uint64_t stop_code() { return interrupt_sim; }
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inline phys_addr_t v2p(const iss::addr_t& addr){
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if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
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if (addr.space != traits<tgc5c>::MEM || addr.type == iss::address_type::PHYSICAL ||
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addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
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return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
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return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc5c>::addr_mask);
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} else
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return virt2phys(addr);
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}
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@ -211,7 +211,7 @@ struct tgc_c: public arch_if {
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#pragma pack(push, 1)
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struct TGC_C_regs {
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struct TGC5C_regs {
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uint32_t X0 = 0;
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uint32_t X1 = 0;
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uint32_t X2 = 0;
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@ -267,4 +267,4 @@ struct tgc_c: public arch_if {
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}
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}
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#endif /* _TGC_C_H_ */
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#endif /* _TGC5C_H_ */
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@ -2,49 +2,49 @@
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#define _ISS_ARCH_TGC_MAPPER_H
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#include "riscv_hart_m_p.h"
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#include "tgc_c.h"
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using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
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#ifdef CORE_TGC_A
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#include "tgc5c.h"
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using tgc5c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5c>;
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#ifdef CORE_TGC5A
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#include "riscv_hart_m_p.h"
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#include <iss/arch/tgc_a.h>
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using tgc_a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_a>;
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#include <iss/arch/tgc5a.h>
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using tgc5a_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5a>;
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#endif
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#ifdef CORE_TGC_B
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#ifdef CORE_TGC5B
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#include "riscv_hart_m_p.h"
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#include <iss/arch/tgc_b.h>
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using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
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#include <iss/arch/tgc5b.h>
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using tgc5b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc5b>;
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#endif
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#ifdef CORE_TGC_C_XRB_NN
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#ifdef CORE_TGC5C_XRB_NN
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#include "riscv_hart_m_p.h"
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#include "hwl.h"
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#include <iss/arch/tgc_c_xrb_nn.h>
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using tgc_c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc_c_xrb_nn>>;
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#include <iss/arch/tgc5c_xrb_nn.h>
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using tgc5c_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_m_p<iss::arch::tgc5c_xrb_nn>>;
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#endif
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#ifdef CORE_TGC_D
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#ifdef CORE_TGC5D
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#include "riscv_hart_mu_p.h"
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#include <iss/arch/tgc_d.h>
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using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
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#include <iss/arch/tgc5d.h>
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using tgc5d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
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#endif
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#ifdef CORE_TGC_D_XRB_MAC
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#ifdef CORE_TGC5D_XRB_MAC
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#include "riscv_hart_mu_p.h"
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#include <iss/arch/tgc_d_xrb_mac.h>
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using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
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#include <iss/arch/tgc5d_xrb_mac.h>
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using tgc5d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
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#endif
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#ifdef CORE_TGC_D_XRB_NN
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#ifdef CORE_TGC5D_XRB_NN
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#include "riscv_hart_mu_p.h"
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#include "hwl.h"
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#include <iss/arch/tgc_d_xrb_nn.h>
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using tgc_d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
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#include <iss/arch/tgc5d_xrb_nn.h>
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using tgc5d_xrb_nn_plat_type = iss::arch::hwl<iss::arch::riscv_hart_mu_p<iss::arch::tgc5d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>>;
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#endif
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#ifdef CORE_TGC_E
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#ifdef CORE_TGC5E
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#include "riscv_hart_mu_p.h"
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#include <iss/arch/tgc_e.h>
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using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
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#include <iss/arch/tgc5e.h>
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using tgc5e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
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#endif
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#ifdef CORE_TGC_X
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#ifdef CORE_TGC5X
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#include "riscv_hart_mu_p.h"
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#include <iss/arch/tgc_x.h>
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using tgc_x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
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#include <iss/arch/tgc5x.h>
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using tgc5x_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc5x, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N | iss::arch::FEAT_TCM)>;
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#endif
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#endif
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@ -145,7 +145,7 @@ public:
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std::tie(cpu, vm) = f.create(type+"|"+backend);
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} else {
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auto base_isa = type.substr(0, 5);
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if(base_isa=="tgc_d" || base_isa=="tgc_e") {
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if(base_isa=="tgc5d" || base_isa=="tgc5e") {
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std::tie(cpu, vm) = f.create(type + "|mu_p_clic_pmp|" + backend, gdb_port);
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} else {
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std::tie(cpu, vm) = f.create(type + "|m_p|" + backend, gdb_port);
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@ -96,7 +96,7 @@ public:
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cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
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cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
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cci::cci_param<std::string> core_type{"core_type", "tgc5c"};
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cci::cci_param<std::string> backend{"backend", "interp"};
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scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
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scml_property<std::string> core_type{"core_type", "tgc_c"};
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scml_property<std::string> core_type{"core_type", "tgc5c"};
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scml_property<std::string> backend{"backend", "interp"};
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, elf_file{"elf_file", ""}
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, enable_disass{"enable_disass", false}
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, reset_address{"reset_address", 0ULL}
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, core_type{"core_type", "tgc_c"}
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, core_type{"core_type", "tgc5c"}
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, backend{"backend", "interp"}
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, gdb_server_port{"gdb_server_port", 0}
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, dump_ir{"dump_ir", false}
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@ -31,7 +31,7 @@
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*******************************************************************************/
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#include <iss/factory.h>
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#include <iss/arch/tgc_c.h>
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#include <iss/arch/tgc5c.h>
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/arch/riscv_hart_mu_p.h>
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#include "sc_core_adapter.h"
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namespace iss {
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namespace interp {
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volatile std::array<bool, 2> tgc_init = {
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core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
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arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
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return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
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}),
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core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
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arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
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return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
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})
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};
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#if defined(WITH_TCC)
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namespace tcc {
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volatile std::array<bool, 2> tgc_init = {
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core_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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core_factory::instance().register_creator("tgc5c|m_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc_c>>(cc);
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arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
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return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
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}),
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core_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned gdb_port, void* data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
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arch::tgc_c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc_c>>(cc);
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arch::tgc5c* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
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return {cpu_ptr{cpu}, vm_ptr{create(cpu, gdb_port)}};
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})
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};
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*
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*******************************************************************************/
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#include <iss/arch/tgc_c.h>
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#include <iss/arch/tgc5c.h>
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||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
|
@ -50,7 +50,7 @@
|
|||
|
||||
namespace iss {
|
||||
namespace interp {
|
||||
namespace tgc_c {
|
||||
namespace tgc5c {
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
using namespace std::placeholders;
|
||||
|
@ -2635,11 +2635,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
|
|||
return pc;
|
||||
}
|
||||
|
||||
} // namespace tgc_c
|
||||
} // namespace tgc5c
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
|
||||
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
|
||||
std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
|
||||
auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
||||
|
@ -2652,15 +2652,15 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
|
|||
namespace iss {
|
||||
namespace {
|
||||
volatile std::array<bool, 2> dummy = {
|
||||
core_factory::instance().register_creator("tgc_c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
|
||||
auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
|
||||
core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
|
||||
auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
|
||||
return {cpu_ptr{cpu}, vm_ptr{vm}};
|
||||
}),
|
||||
core_factory::instance().register_creator("tgc_c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
|
||||
auto vm = new interp::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
|
||||
core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
|
||||
auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
|
||||
return {cpu_ptr{cpu}, vm_ptr{vm}};
|
||||
})
|
|
@ -30,8 +30,8 @@
|
|||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iss/arch/tgc_c.h>
|
||||
#include <iss/arch/riscv_hart_m_p.h>
|
||||
#include <iss/arch/tgc5c.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
|
@ -52,7 +52,7 @@ namespace fp_impl {
|
|||
void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
|
||||
}
|
||||
|
||||
namespace tgc_c {
|
||||
namespace tgc5c {
|
||||
using namespace ::llvm;
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
|
@ -4151,11 +4151,11 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *b
|
|||
bb, this->trap_blk, 1);
|
||||
}
|
||||
|
||||
} // namespace tgc_c
|
||||
} // namespace tgc5c
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
|
||||
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
|
||||
std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
|
||||
auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
|
@ -30,7 +30,7 @@
|
|||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include <iss/arch/tgc_c.h>
|
||||
#include <iss/arch/tgc5c.h>
|
||||
#include <iss/debugger/gdb_session.h>
|
||||
#include <iss/debugger/server.h>
|
||||
#include <iss/iss.h>
|
||||
|
@ -48,7 +48,7 @@
|
|||
|
||||
namespace iss {
|
||||
namespace tcc {
|
||||
namespace tgc_c {
|
||||
namespace tgc5c {
|
||||
using namespace iss::arch;
|
||||
using namespace iss::debugger;
|
||||
|
||||
|
@ -3210,11 +3210,11 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
|
|||
tu("return *next_pc;");
|
||||
}
|
||||
|
||||
} // namespace tgc_c
|
||||
} // namespace tgc5c
|
||||
|
||||
template <>
|
||||
std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {
|
||||
auto ret = new tgc_c::vm_impl<arch::tgc_c>(*core, dump);
|
||||
std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
|
||||
auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
|
||||
return std::unique_ptr<vm_if>(ret);
|
||||
}
|
||||
|
@ -3227,15 +3227,15 @@ std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short por
|
|||
namespace iss {
|
||||
namespace {
|
||||
volatile std::array<bool, 2> dummy = {
|
||||
core_factory::instance().register_creator("tgc_c|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc_c>();
|
||||
auto vm = new tcc::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
|
||||
core_factory::instance().register_creator("tgc5c|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
|
||||
auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
|
||||
return {cpu_ptr{cpu}, vm_ptr{vm}};
|
||||
}),
|
||||
core_factory::instance().register_creator("tgc_c|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc_c>();
|
||||
auto vm = new tcc::tgc_c::vm_impl<arch::tgc_c>(*cpu, false);
|
||||
core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
|
||||
auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
|
||||
auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
|
||||
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
|
||||
return {cpu_ptr{cpu}, vm_ptr{vm}};
|
||||
})
|
Loading…
Reference in New Issue