DBT-RISE/DBT-RISE-TGC
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renames core(s)

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eyck committed 2023-08-28 07:09:55 +02:00
1 parent 0b719a4b57
commit c8a4a4c736
11 files changed
+100 -100
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gen_input/TGC_C.core_desc
+2 -2
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@@ -1,8 +1,8 @@
import "ISA/RV32I.core_desc"
import "ISA/RVI.core_desc"
import "ISA/RVM.core_desc"
import "ISA/RVC.core_desc"
Core TGC_C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
architectural_state {
XLEN=32;
// definitions for the architecture wrapper