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  • 0de438dc52 avoid interrupts while printing master stas 2022-05-02 09:51:05 +02:00
  • 5f44f8df98 Improve wait for interrupt routines stas 2022-04-28 19:20:32 +02:00
  • 02ce96eed8 improve interrupt handling stas 2022-04-26 15:29:49 +02:00
  • 46f197c287 Add additional registers for input to FW (number of XSPNs, batch size, iterations) feature/rework_xspn Johannes Wirth 2022-03-11 14:21:25 +01:00
  • 43e2a299db fpga_spn: add check if input-/ref-data fits into memory Johannes Wirth 2022-03-10 14:17:52 +01:00
  • 8450f85c93 raven_spn: add check if input-/ref-data fits into memory Johannes Wirth 2022-03-10 13:11:10 +01:00
  • a14ff554b0 Move XSPN input and ref data to Validation-VP Johannes Wirth 2022-03-10 13:09:11 +01:00
  • 588ca3c7ba Merge pull request 'Add allocate+free functionality for fpga' (#1) from feature/fpga-alloc-free into master stas 2022-02-11 16:12:21 +01:00
  • 91f28e9f2b Add allocate+free functionality for fpga feature/fpga-alloc-free Johannes Wirth 2022-01-20 18:22:21 +01:00
  • 446af340c8 fpga_spn: use separate reset for DMA Johannes Wirth 2021-11-10 09:51:19 +01:00
  • 89ea594399 Update FPGA Firmware for bigger batch sizes Johannes Wirth 2021-07-13 10:51:28 +02:00
  • a70f5bb09c add wait for both spn interrupts stas 2021-05-17 11:54:37 +02:00
  • 1b09899d2a XSPN hybrid simulation passed in MINRES environment stas 2021-04-22 14:50:21 +02:00
  • 5ba7d5dd24 extend spn_checker to comapre the results from 2nd XSPN accelerator stas 2021-04-20 20:36:00 +02:00
  • 26d7560891 add second XSPN partition stas 2021-04-20 08:30:39 +02:00
  • 96de37dbc2 increase XSPN load stas 2021-04-14 08:45:21 +02:00
  • d0eff8c08d longer simulation stas 2021-04-12 13:12:04 +02:00
  • 2a9ce332c7 fix hello-world init stas 2021-04-09 11:19:05 +02:00
  • 9578bcfa45 Use spn_checker in fpga_spn firmware Johannes Wirth 2021-03-31 16:22:08 +02:00
  • f5e0d13891 move data handling into snp_checker vp stas 2021-03-26 10:36:15 +01:00
  • b03f1bff4f create snp result checker to enable parallel spn calculation and result comparison stas 2021-03-25 09:36:16 +01:00
  • 8c0211f945 Cleanup SPN firmwares Johannes Wirth 2021-03-19 11:56:13 +01:00
  • 3743cbfecd enable result check in raven_spn fw stas 2021-03-10 12:05:23 +01:00
  • 6bfe684e73 Create separate xspn-fpga FW Add xspn data for different accelerators Johannes Wirth 2021-03-04 11:19:35 +01:00
  • 7f8ddf3201 re-implement wait_for_interrupt and get rid of multiplication in check_results for better performance stas 2021-01-08 09:30:47 +01:00
  • 685f25e2ce Passed multi-thread-xspn-vp simulation stas 2021-01-06 17:27:58 +01:00
  • 3d93e4b9a5 Give XSPN the address of the input_data array stas 2021-01-05 12:56:31 +01:00
  • 62cdc0c7b9 error exit stas 2020-12-30 11:37:06 +01:00
  • 4dbbb73f01 restructure for parallel execution stas 2020-12-14 12:52:05 +01:00
  • 0d0d12edff wait for interrupt instead of time delay stas 2020-12-14 08:43:11 +01:00
  • db22ccbce5 run 10000 XSPN samples stas 2020-12-11 17:01:35 +01:00
  • 06cc727883 200 XSPN samples passed stas 2020-12-10 15:38:25 +01:00
  • 50428965e9 Compile XSPN input and ref data in flash memory. stas 2020-12-08 17:07:21 +01:00
  • afb8a677f1 check first XSPN result value in FW, add gcc_except_table, replace self-made printf with one from the lib. stas 2020-12-07 12:55:10 +01:00
  • 1d46ef5fea fix raven_spn cdt project stas 2020-12-07 08:42:38 +01:00
  • 01cfbd34fe 1st successful XSPN run. Insert few samples and get one result stas 2020-12-04 12:34:49 +01:00
  • 8249a0417e First configuration of the XSPNController stas 2020-11-04 17:41:56 +01:00
  • 4720c923cd add SPN configuration stas 2020-10-02 12:10:43 +02:00
  • 7d5de86015 start implementing FW to control SPN HW stas 2020-10-01 17:18:29 +02:00
  • 62da6407d8 delay instead of sync stas 2020-09-17 15:39:30 +02:00
  • 0773f51fd3 fix synchronization stas 2020-09-17 15:19:14 +02:00
  • 9e9b644e29 remove unused timer interrupt handler stas 2020-09-16 15:12:21 +02:00
  • 9157a42042 raven FW with data and interrupt transfer (based on bldc project) stas 2020-09-16 10:28:54 +02:00
  • 4c790f8810 add eclipse project stas 2020-09-09 08:43:20 +02:00
  • ba27721c4d run different code depending on the MHARTID reg value stas 2020-09-04 12:56:12 +02:00
  • e15e299968 initial FW setup for Raven validation stas 2020-09-03 11:13:37 +02:00
  • ce24b0f2f2 build hello fw with GCC Toolchain v2020.04.1 (set GPIO_IOF_EN). Remove obsolete function write_hex stas 2020-09-02 09:13:01 +02:00
  • 830c1382b9 add CDT project files, update binaries eyck 2020-06-18 12:32:41 +02:00
  • 27cad2f819 add a few more fw examples eyck 2020-06-18 12:15:52 +02:00
  • a96cb14dcf Added doxygen comments and refactored a few functions eyck 2018-10-21 22:48:57 +02:00
  • 188bd2b5dd Changed delay calculation for open loop commutation eyck 2018-10-21 22:29:45 +02:00
  • 458c75c5e4 some renaming eyck 2018-10-21 00:14:14 +02:00
  • 9f9088a110 Changed naming of constants and formatting eyck 2018-10-16 18:51:48 +02:00
  • d6db5f7e04 Fixed rxwm setting as it defines the maximum number of received bytes *before* the interrupt eyck 2018-10-05 12:23:39 +02:00
  • 2a45030414 Added binary for easy jump start eyck 2018-09-26 09:09:23 +02:00
  • 2ebe9541d5 Working version eyck 2018-09-26 08:07:48 +02:00
  • a4bfa4e679 cleanup of makefiles eyck 2018-09-25 20:32:56 +02:00
  • 038c199c0a cleanup and rename of files eyck 2018-09-25 19:17:28 +02:00
  • 3512206d77 Added hello world project eyck 2018-09-25 18:31:29 +02:00
  • 215767a724 Sync commit eyck 2018-09-14 14:03:20 +02:00
  • 250fa831d0 Initial version of riscv-bldc-forced-communication eyck 2018-08-08 20:59:10 +02:00
  • 42b87091a4 Initial commit DVCon2018 2018-06-23 10:17:35 +00:00