forked from Firmware/Firmwares
wait for interrupt instead of time delay
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85
raven_spn/src/init.h
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85
raven_spn/src/init.h
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@ -0,0 +1,85 @@
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#ifndef SRC_INIT_H_
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#define SRC_INIT_H_
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#include <cstdio>
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#include <array>
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#include "delay.h"
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#include "bsp.h"
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#include "plic/plic_driver.h"
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typedef void (*function_ptr_t) (void);
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//! Instance data for the PLIC.
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plic_instance_t g_plic;
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std::array<function_ptr_t,PLIC_NUM_INTERRUPTS> g_ext_interrupt_handlers;
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bool hw_interrupt{false};
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/*! \brief external interrupt handler
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*
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* routes the peripheral interrupts to the the respective handler
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*
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*/
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extern "C" void handle_m_ext_interrupt() {
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plic_source int_num = PLIC_claim_interrupt(&g_plic);
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if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS))
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g_ext_interrupt_handlers[int_num]();
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else
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exit(1 + (uintptr_t) int_num);
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PLIC_complete_interrupt(&g_plic, int_num);
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}
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/*! \brief dummy interrupt handler
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*
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*/
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void no_interrupt_handler (void) {};
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/*! \brief configure the per-interrupt handler
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*
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*/
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void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1) {
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g_ext_interrupt_handlers[irq_num] = handler;
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// Priority must be set > 0 to trigger the interrupt.
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PLIC_set_priority(&g_plic, irq_num, prio);
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// Have to enable the interrupt both at the GPIO level, and at the PLIC level.
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PLIC_enable_interrupt(&g_plic, irq_num);
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}
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static void msi_interrupt_handler(){
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hw_interrupt = true;
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}
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void wait_for_interrupt() {
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while (!hw_interrupt) {
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delayUS(1);
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};
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hw_interrupt = false;
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}
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/*!\brief initializes platform
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*
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*/
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void platform_init(){
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// UART init section TODO: clarify how to get the functions from init.c?
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GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
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GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
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UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
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F_CPU=PRCI_measure_mcycle_freq(20, RTC_FREQ);
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printf("core freq at %d Hz\n", F_CPU);
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// initialie interupt & trap handling
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write_csr(mtvec, &trap_entry);
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PLIC_init(&g_plic, PLIC_CTRL_ADDR, PLIC_NUM_INTERRUPTS, PLIC_NUM_PRIORITIES, 0);
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// Disable the machine & timer interrupts until setup is done.
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clear_csr(mie, MIP_MEIP);
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clear_csr(mie, MIP_MTIP);
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for (auto& h:g_ext_interrupt_handlers) h=no_interrupt_handler;
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configure_irq(2, msi_interrupt_handler);
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// Enable interrupts in general.
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set_csr(mstatus, MSTATUS_MIE);
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// Enable the Machine-External bit in MIE
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set_csr(mie, MIP_MEIP);
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hw_interrupt = false;
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}
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#endif /* SRC_INIT_H_ */
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@ -1,88 +1,16 @@
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#include "raven_spn.h"
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#include "spn_regs.h"
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#include "delay.h"
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#include "bsp.h"
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#include "plic/plic_driver.h"
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#include "init.h"
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#include <cstdio>
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#include <cstdint>
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#include <array>
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#include <cmath>
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#include <cmath> // log
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using spn =spn_regs<0x90000000>;
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#define IOF_ENABLE_TERMINAL (0x30000)
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// huge arrays of XSPN input and referance data
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extern std::array<uint8_t, 50000> input_data;
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extern std::array<double, 10000> ref_data;
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constexpr auto ln2 = std::log(2);
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typedef void (*function_ptr_t) (void);
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//! Instance data for the PLIC.
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plic_instance_t g_plic;
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std::array<function_ptr_t,PLIC_NUM_INTERRUPTS> g_ext_interrupt_handlers;
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/*! \brief external interrupt handler
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*
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* routes the peripheral interrupts to the the respective handler
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*
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*/
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extern "C" void handle_m_ext_interrupt() {
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plic_source int_num = PLIC_claim_interrupt(&g_plic);
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if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS))
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g_ext_interrupt_handlers[int_num]();
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else
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exit(1 + (uintptr_t) int_num);
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PLIC_complete_interrupt(&g_plic, int_num);
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}
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/*! \brief dummy interrupt handler
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*
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*/
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void no_interrupt_handler (void) {};
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/*! \brief configure the per-interrupt handler
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*
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*/
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void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1) {
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g_ext_interrupt_handlers[irq_num] = handler;
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// Priority must be set > 0 to trigger the interrupt.
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PLIC_set_priority(&g_plic, irq_num, prio);
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// Have to enable the interrupt both at the GPIO level, and at the PLIC level.
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PLIC_enable_interrupt(&g_plic, irq_num);
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}
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static void msi_interrupt_handler(){
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printf("INterrupt handler call\n");
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}
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/*!\brief initializes platform
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*
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*/
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void platform_init(){
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// UART init section TODO: clarify how to get the functions from init.c?
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GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
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GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
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UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
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F_CPU=PRCI_measure_mcycle_freq(20, RTC_FREQ);
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printf("core freq at %d Hz\n", F_CPU);
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// initialie interupt & trap handling
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write_csr(mtvec, &trap_entry);
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PLIC_init(&g_plic, PLIC_CTRL_ADDR, PLIC_NUM_INTERRUPTS, PLIC_NUM_PRIORITIES, 0);
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// Disable the machine & timer interrupts until setup is done.
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clear_csr(mie, MIP_MEIP);
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clear_csr(mie, MIP_MTIP);
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for (auto& h:g_ext_interrupt_handlers) h=no_interrupt_handler;
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configure_irq(2, msi_interrupt_handler);
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// Enable interrupts in general.
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set_csr(mstatus, MSTATUS_MIE);
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// Enable the Machine-External bit in MIE
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set_csr(mie, MIP_MEIP);
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}
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bool double_equals(double a, double b, double epsilon = 0.001)
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{
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return std::abs(a - b) < epsilon;
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@ -92,11 +20,12 @@ void run_xspn() {
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spn::mode_reg() = 0;
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spn::input_length_reg() = 100; // each sample consists of 5 uint8 values
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spn::input_addr_reg() = 0x800C0000;
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spn::output_addr_reg() = 0x8001C000;
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spn::output_addr_reg() = 0x800A0000;
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spn::num_of_in_beats_reg() = 8; // Number of AXI4 burst beats needed to load all input data
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spn::num_of_out_beats_reg() = 13; // Number of AXI4 burst beats needed to store all result data
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spn::start_reg() = 1;
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delayUS(50);
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wait_for_interrupt();
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spn::interrupt_reg() = 1;
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}
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@ -107,8 +36,9 @@ int main() {
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platform_init();
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spn::mode_reg() = 1;
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spn::start_reg() = 1;
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printf("READOUT HW:0x%x\n", spn::readout_reg());
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wait_for_interrupt();
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spn::interrupt_reg() = 1;
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printf("READOUT HW:0x%x\n", spn::readout_reg());
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for (int k = 0; k < 10000; k+=100) {
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// write input samples into the memory
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@ -126,7 +56,7 @@ int main() {
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run_xspn();
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// read calculation results from the memory
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double * res_base = (double*) 0x8001C000;
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double * res_base = (double*) 0x800A0000;
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for (int i = 0; i < 100; i++) {
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if (!double_equals(res_base[i] * ln2, ref_data.at(k+i))) {
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