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Firmware:main

9 Commits
cmake_flow ... main

Author SHA1 Message Date
stas
87dc0ec230 Merge remote-tracking branch 'origin/develop' into main 2024-04-17 08:27:23 +02:00
Eyck-Alexander Jentzsch
8ac5244670 changes fill naming to be stricly increasing 2024-03-28 11:48:37 +01:00
Eyck-Alexander Jentzsch
6365331de8 fixes bug that duplicated variable names 2024-03-28 11:33:57 +01:00
Eyck-Alexander Jentzsch
baddcf17af adds improved firmware headers for peripherals 2024-03-28 09:34:01 +01:00
Eyck Jentzsch
7218dcfa69 changes target extension to become .elf 2024-03-24 21:19:08 +01:00
Eyck Jentzsch
3389875643 fixes rve settings 2024-03-21 07:23:21 +01:00
Eyck Jentzsch
4d25972e4d fixes TGCP environment 2024-03-20 12:53:12 +01:00
Eyck Jentzsch
e051cf180e Merge branch 'develop' 2024-03-20 07:38:03 +01:00
Eyck Jentzsch
ab2b7214fe fixes TGCP env 2024-03-14 08:12:52 +01:00
57 changed files with 1187 additions and 3046 deletions
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1
.gitignore vendored
View File

@ -151,4 +151,3 @@ compile_commands.json
CTestTestfile.cmake
*.dump
/doc/

11
CMakeLists.txt
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@ -1,11 +0,0 @@
cmake_minimum_required(VERSION 3.12)
project(bsp C)
add_subdirectory(libwrap)
add_subdirectory(env)
message(STATUS " in bsp with ${CMAKE_CXX_FLAGS}")
message(STATUS " SUPPORTED_BOARDS= ${SUPPORTED_BOARDS}")
add_library(${PROJECT_NAME} INTERFACE)
target_include_directories(${PROJECT_NAME} INTERFACE
include/
env/${BOARD}
env/)

64
env/CMakeLists.txt vendored
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@ -1,64 +0,0 @@
project(env)
message(STATUS " here in bsp/env")
message(STATUS " BOARD: ${BOARD}")
# Enable ASM language
enable_language(ASM)
set(ASM_SOURCES
entry.S
start.S
)
add_library(asm_obj OBJECT ${ASM_SOURCES})
set_target_properties(asm_obj PROPERTIES ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bare-metal-bsp/${PROJECT_NAME})
target_include_directories(asm_obj PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}
${BSP_BASE}/include
#include/
${BSP_BASE}/env
${BSP_BASE}/env/${BOARD}
${BSP_BASE}/drivers
)
# Export variables for hello-world to use
set(ENV_OBJECTS
$<TARGET_OBJECTS:asm_obj>
PARENT_SCOPE
)
set(BOARD_LIB_NAME ${BOARD})
message(STATUS " BOARD_LIB_NAME: ${BOARD_LIB_NAME}")
set(BOARD_LIB_SRC
${BOARD}/init.c
${BOARD}/write.c
)
add_library(${BOARD_LIB_NAME} STATIC ${BOARD_LIB_SRC})
set_target_properties(${BOARD_LIB_NAME} PROPERTIES ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bare-metal-bsp/${PROJECT_NAME})
# Set ASM compile options
#set(CMAKE_ASM_COMPILER riscv64-unknown-elf-as)
#set(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -march=${RISCV_ARCH}_zicsr_zifencei -mabi=${RISCV_ABI}")
#add_subdirectory(${BOARD})
target_include_directories(${BOARD_LIB_NAME} PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}
${BSP_BASE}/include
${BSP_BASE}/libwrap/sys
${BSP_BASE}/env
${BSP_BASE}/env/${BOARD}
${BSP_BASE}/drivers
)
# Include the ISS board configuration
#set(ISS_SOURCE_DIR "${CMAKE_SOURCE_DIR}/bare-metal-bsp/env/iss")
#set(ISS_BINARY_DIR "${CMAKE_BINARY_DIR}/iss_build")
#add_subdirectory(${ISS_SOURCE_DIR} ${ISS_BINARY_DIR})
# Export board library
#set(BOARD_LIB board_iss PARENT_SCOPE)

7
env/TGCP/init.c vendored
View File

@ -110,12 +110,13 @@ void _fini()
}
int is_uart_ready(int uart_id){
return 1;
return !UART0_REG(UART_REG_TXFIFO) & 0x80000000;
}
int try_write_uart_char(int uart_id, char c){
*((char*)0x10000000) = c;
if(UART0_REG(UART_REG_TXFIFO) & 0x80000000) return 0;
UART0_REG(UART_REG_TXFIFO) = c;
return 1;
}
void write_uart_char(int uart_id, char c){
*((char*)0x10000000) = c;
UART0_REG(UART_REG_TXFIFO) = c;
}

71
env/TGCP/link.lds vendored
View File

@ -22,13 +22,18 @@ SECTIONS
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
*crt0.o(.text .text.*)
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.init)
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .text.*)
*(.stub)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
@ -50,6 +55,13 @@ SECTIONS
. = ALIGN(4);
/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >flash AT>flash :flash
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >flash AT>flash :flash
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
@ -116,13 +128,6 @@ SECTIONS
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
@ -133,9 +138,11 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
.data :
{
__SDATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
@ -158,7 +165,6 @@ SECTIONS
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
@ -171,4 +177,47 @@ SECTIONS
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
.debug_addr 0 : { *(.debug_addr) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}

13
env/TGCP/platform.h vendored
View File

@ -7,7 +7,18 @@
#define MCAUSE_INT 0x80000000
#define MCAUSE_CAUSE 0x7FFFFFFF
#include "bits.h"
#define UART0_BASE_ADDR 0xffff0000ULL
#define UART_REG_TXFIFO 0x00
#define UART_REG_RXFIFO 0x04
#define UART_REG_TXCTRL 0x08
#define UART_REG_RXCTRL 0x0c
#define UART_REG_IE 0x10
#define UART_REG_IP 0x14
#define UART_REG_DIV 0x18
#define UART_TXEN 0x1
#define UART0_REG(ADDR) *((volatile uint32_t*) (UART0_BASE_ADDR + ADDR))
/****************************************************************************
* Platform definitions
*****************************************************************************/

9
env/common-gcc.mk vendored
View File

@ -2,6 +2,7 @@ ifndef _MK_COMMON
_MK_COMMON := # defined
TL_TARGET?=all
BOARD?=iss
.PHONY: $(TL_TARGET)
$(TL_TARGET): $(TARGET).elf
@ -12,11 +13,9 @@ PLATFORM_DIR = $(ENV_DIR)/$(BOARD)
include $(BSP_BASE)/libwrap/libwrap.mk
BOARD?=iss
ASM_SRCS += $(ENV_DIR)/start.S $(ENV_DIR)/entry.S
C_SRCS += $(PLATFORM_DIR)/init.c
C_SRCS += $(PLATFORM_DIR)/write.c
LINKER_SCRIPT ?= $(PLATFORM_DIR)/$(LINK_TARGET).lds
@ -24,7 +23,6 @@ INCLUDES += -I$(BSP_BASE)/include
INCLUDES += -I$(BSP_BASE)/drivers/
INCLUDES += -I$(ENV_DIR)
INCLUDES += -I$(PLATFORM_DIR)
INCLUDES += -I$(BSP_BASE)/libwrap/sys/
LDFLAGS += -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI)
LDFLAGS += -L$(ENV_DIR)
@ -44,7 +42,7 @@ CXX_OBJS := $(CXX_SRCS:.cpp=.o)
LINK_OBJS += $(ASM_OBJS) $(C_OBJS) $(CXX_OBJS)
LINK_DEPS += $(LINKER_SCRIPT)
CLEAN_OBJS += $(TARGET) $(LINK_OBJS)
CLEAN_OBJS += $(TARGET).elf $(LINK_OBJS)
GCCVERSION = $(shell $(CC) --version | grep gcc | awk '{print($NF);}')
ifeq ($(GCCVERSION),9.2)
@ -66,6 +64,7 @@ OBJCOPY := $(TOOL_DIR)$(TRIPLET)-objcopy
ifndef NO_DEFAULT_LINK
$(TARGET).elf: $(LINK_OBJS) $(LINK_DEPS)
echo LINK_OBJS: $(LINK_OBJS)
$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP_LDFLAGS) $(LIBWRAP) $(LD_SCRIPT) -o $@
$(OBJDUMP) -d -S $@ > $(TARGET).dis
endif
@ -81,6 +80,6 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)
.PHONY: clean
clean:
rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf
rm -f $(CLEAN_OBJS) $(LIBWRAP)
endif

19
env/ehrenberg/init.c vendored
View File

@ -85,26 +85,19 @@ void __attribute__((weak)) handle_m_ext_interrupt(){
void __attribute__((weak)) handle_m_time_interrupt(){
uint64_t time = get_aclint_mtime(aclint);
time+=MTIMER_NEXT_TICK_INC;
set_aclint_mtimecmp(aclint, time);
set_aclint_mtime(aclint, time);
}
void __attribute__((weak)) default_handler(void) {
puts("default handler\n");
}
void __attribute__((weak)) interrupt_handler(unsigned) {
puts("interrupt handler\n");
}
uint32_t handle_trap(uint32_t mcause, uint32_t mepc, uint32_t sp){
if ((mcause & MCAUSE_INT)) {
if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
handle_m_ext_interrupt();
} else if (((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
handle_m_time_interrupt();
} else {
interrupt_handler(mcause& ~MCAUSE_INT);
}
if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
handle_m_ext_interrupt();
// External Machine-Level interrupt from PLIC
} else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
handle_m_time_interrupt();
} else {
write(1, "trap\n", 5);
_exit(1 + mcause);

72
env/ehrenberg/link.lds vendored
View File

@ -25,13 +25,18 @@ SECTIONS
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
*crt0.o(.text .text.*)
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.init)
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .text.*)
*(.stub)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
@ -53,6 +58,13 @@ SECTIONS
. = ALIGN(4);
/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >flash AT>flash :flash
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >flash AT>flash :flash
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
@ -119,15 +131,9 @@ SECTIONS
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
@ -135,9 +141,11 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
.data :
{
__SDATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
@ -160,7 +168,6 @@ SECTIONS
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
@ -173,4 +180,47 @@ SECTIONS
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
.debug_addr 0 : { *(.debug_addr) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}

23
env/ehrenberg/platform.h vendored
View File

@ -17,30 +17,21 @@
#include "ehrenberg/devices/uart.h"
#include "ehrenberg/devices/timer.h"
#include "ehrenberg/devices/aclint.h"
#include "ehrenberg/devices/interrupt.h"
#include "ehrenberg/devices/qspi.h"
#include "ehrenberg/devices/i2s.h"
#include "ehrenberg/devices/camera.h"
#include "ehrenberg/devices/dma.h"
#include "ehrenberg/devices/msg_if.h"
#define PERIPH(TYPE, ADDR) ((volatile TYPE*) (ADDR))
#define APB_BASE 0xF0000000
#define gpio PERIPH(gpio_t, APB_BASE+0x0000)
#define uart PERIPH(uart_t, APB_BASE+0x1000)
#define timer PERIPH(timercounter_t, APB_BASE+0x20000)
#define aclint PERIPH(aclint_t, APB_BASE+0x30000)
#define irq PERIPH(irq_t, APB_BASE+0x40000)
#define qspi PERIPH(qspi_t, APB_BASE+0x50000)
#define i2s PERIPH(i2s_t, APB_BASE+0x90000)
#define camera PERIPH(camera_t, APB_BASE+0xA0000)
#define dma PERIPH(dma_t, APB_BASE+0xB0000)
#define msgif PERIPH(msgif_t, APB_BASE+0xC0000)
#define gpio PERIPH(gpio_t, APB_BASE+0x0000)
#define uart PERIPH(uart_t, APB_BASE+0x1000)
#define timer PERIPH(timer_t, APB_BASE+0x20000)
#define aclint PERIPH(aclint_t, APB_BASE+0x30000)
#define irq PERIPH(irq_t, APB_BASE+0x40000)
#define qspi PERIPH(qspi_t, APB_BASE+0x50000)
#define XIP_START_LOC 0xE0040000
#define RAM_START_LOC 0x80000000
// Misc

167
env/ehrenberg/ram.lds vendored
View File

@ -1,167 +0,0 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
rom (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128k
ram (wxa!ri) : ORIGIN = 0x80004000, LENGTH = 128k
}
PHDRS
{
rom PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init ORIGIN(rom) :
{
KEEP (*(SORT_NONE(.init)))
} >rom AT>rom :rom
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >rom AT>rom :rom
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >rom AT>rom :rom
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >rom AT>rom :rom
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >rom AT>rom :rom
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >rom AT>rom :rom
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >rom AT>rom :rom
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >rom AT>rom :rom
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >rom AT>rom :rom
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >rom AT>rom :rom
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>rom :ram_init
.data :
{
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>rom :ram_init
.srodata :
{
PROVIDE( __global_pointer$ = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>rom :ram_init
.sdata :
{
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
}

170
env/ehrenberg/rom.lds vendored
View File

@ -1,170 +0,0 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 4k
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32k
}
PHDRS
{
rom PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init ORIGIN(rom) :
{
KEEP (*(SORT_NONE(.init)))
} >rom AT>rom :rom
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >rom AT>rom :rom
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >rom AT>rom :rom
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >rom AT>rom :rom
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >rom AT>rom :rom
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >rom AT>rom :rom
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >rom AT>rom :rom
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >rom AT>rom :rom
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >rom AT>rom :rom
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >rom AT>rom :rom
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>rom :ram_init
.data :
{
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>rom :ram_init
.srodata :
{
PROVIDE( __global_pointer$ = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>rom :ram_init
.sdata :
{
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
}

122
env/entry.S vendored
View File

@ -10,80 +10,66 @@
.align 2
.global trap_entry
trap_entry:
addi sp, sp, -32*REGBYTES
sw x1, 1*REGBYTES(sp)
sw x2, 2*REGBYTES(sp)
sw x3, 3*REGBYTES(sp)
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
#ifndef __riscv_abi_rve
sw x16, 16*REGBYTES(sp)
sw x17, 17*REGBYTES(sp)
sw x18, 18*REGBYTES(sp)
sw x19, 19*REGBYTES(sp)
sw x20, 20*REGBYTES(sp)
sw x21, 21*REGBYTES(sp)
sw x22, 22*REGBYTES(sp)
sw x23, 23*REGBYTES(sp)
sw x24, 24*REGBYTES(sp)
sw x25, 25*REGBYTES(sp)
sw x26, 26*REGBYTES(sp)
sw x27, 27*REGBYTES(sp)
sw x28, 28*REGBYTES(sp)
sw x29, 29*REGBYTES(sp)
sw x30, 30*REGBYTES(sp)
sw x31, 31*REGBYTES(sp)
#ifdef __riscv_abi_rve
addi sp, sp, -8*REGBYTES
STORE x1, 1*REGBYTES(sp) // ra
STORE x5, 2*REGBYTES(sp) // t0
STORE x10, 3*REGBYTES(sp) // a0
STORE x11, 4*REGBYTES(sp) // a1
STORE x12, 5*REGBYTES(sp) // a2
STORE x13, 6*REGBYTES(sp) // a3
STORE x15, 7*REGBYTES(sp) // t1
#else
addi sp, sp, -16*REGBYTES
STORE x1, 1*REGBYTES(sp) // ra
STORE x5, 2*REGBYTES(sp) // t0
STORE x6, 3*REGBYTES(sp) // t1
STORE x7, 4*REGBYTES(sp) // t2
STORE x10, 5*REGBYTES(sp) // a0
STORE x11, 6*REGBYTES(sp) // a1
STORE x12, 7*REGBYTES(sp) // a2
STORE x13, 8*REGBYTES(sp) // a3
STORE x14, 9*REGBYTES(sp) // a4
STORE x15, 10*REGBYTES(sp) // a5
STORE x16, 11*REGBYTES(sp) // a6
STORE x17, 12*REGBYTES(sp) // a7
STORE x28, 13*REGBYTES(sp) // t3
STORE x29, 14*REGBYTES(sp) // t4
STORE x30, 15*REGBYTES(sp) // t5
STORE x31, 16*REGBYTES(sp) // t6
#endif
csrr a0, mcause
csrr a1, mepc
mv a2, sp
call handle_trap
csrw mepc, a0
lw x1, 1*REGBYTES(sp)
lw x2, 2*REGBYTES(sp)
lw x3, 3*REGBYTES(sp)
lw x4, 4*REGBYTES(sp)
lw x5, 5*REGBYTES(sp)
lw x6, 6*REGBYTES(sp)
lw x7, 7*REGBYTES(sp)
lw x8, 8*REGBYTES(sp)
lw x9, 9*REGBYTES(sp)
lw x10, 10*REGBYTES(sp)
lw x11, 11*REGBYTES(sp)
lw x12, 12*REGBYTES(sp)
lw x13, 13*REGBYTES(sp)
lw x14, 14*REGBYTES(sp)
lw x15, 15*REGBYTES(sp)
#ifndef __riscv_abi_rve
lw x16, 16*REGBYTES(sp)
lw x17, 17*REGBYTES(sp)
lw x18, 18*REGBYTES(sp)
lw x19, 19*REGBYTES(sp)
lw x20, 20*REGBYTES(sp)
lw x21, 21*REGBYTES(sp)
lw x22, 22*REGBYTES(sp)
lw x23, 23*REGBYTES(sp)
lw x24, 24*REGBYTES(sp)
lw x25, 25*REGBYTES(sp)
lw x26, 26*REGBYTES(sp)
lw x27, 27*REGBYTES(sp)
lw x28, 28*REGBYTES(sp)
lw x29, 29*REGBYTES(sp)
lw x30, 30*REGBYTES(sp)
lw x31, 31*REGBYTES(sp)
#ifdef __riscv_abi_rve
addi sp, sp, -8*REGBYTES
LOAD x1, 1*REGBYTES(sp) // ra
LOAD x5, 2*REGBYTES(sp) // t0
LOAD x10, 3*REGBYTES(sp) // a0
LOAD x11, 4*REGBYTES(sp) // a1
LOAD x12, 5*REGBYTES(sp) // a2
LOAD x13, 6*REGBYTES(sp) // a3
LOAD x15, 7*REGBYTES(sp) // t1
#else
addi sp, sp, -16*REGBYTES
LOAD x1, 1*REGBYTES(sp) // ra
LOAD x5, 2*REGBYTES(sp) // t0
LOAD x6, 3*REGBYTES(sp) // t1
LOAD x7, 4*REGBYTES(sp) // t2
LOAD x10, 5*REGBYTES(sp) // a0
LOAD x11, 6*REGBYTES(sp) // a1
LOAD x12, 7*REGBYTES(sp) // a2
LOAD x13, 8*REGBYTES(sp) // a3
LOAD x14, 9*REGBYTES(sp) // a4
LOAD x15, 10*REGBYTES(sp) // a5
LOAD x16, 11*REGBYTES(sp) // a6
LOAD x17, 12*REGBYTES(sp) // a7
LOAD x28, 13*REGBYTES(sp) // t3
LOAD x29, 14*REGBYTES(sp) // t4
LOAD x30, 15*REGBYTES(sp) // t5
LOAD x31, 16*REGBYTES(sp) // t6
#endif
mret

30
env/iss/CMakeLists.txt vendored
View File

@ -1,30 +0,0 @@
#cmake_minimum_required(VERSION 3.12)
project(iss)
message(STATUS " here in iss")
# Create library for ISS board support
add_library(board_iss STATIC
init.c
write.c
)
# Include directories
target_include_directories(board_iss PUBLIC
${BSP_BASE}/include
${BSP_BASE}/env
${CMAKE_CURRENT_SOURCE_DIR}
)
# Set compile options
target_compile_options(board_iss PRIVATE
-march=${RISCV_ARCH}_zicsr_zifencei
-mabi=${RISCV_ABI}
-mcmodel=medany
-ffunction-sections
-fdata-sections
)
# Add compile definitions
target_compile_definitions(board_iss PRIVATE
BOARD_${BOARD}
)

71
env/iss/link.lds vendored
View File

@ -22,13 +22,18 @@ SECTIONS
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
*crt0.o(.text .text.*)
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.init)
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .text.*)
*(.stub)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
@ -50,6 +55,13 @@ SECTIONS
. = ALIGN(4);
/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >flash AT>flash :flash
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >flash AT>flash :flash
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
@ -116,13 +128,6 @@ SECTIONS
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
@ -133,9 +138,11 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
.data :
{
__SDATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
@ -158,7 +165,6 @@ SECTIONS
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
@ -171,4 +177,47 @@ SECTIONS
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
.debug_addr 0 : { *(.debug_addr) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}

38
env/iss/write.c vendored
View File

@ -1,38 +0,0 @@
/* See LICENSE of license details. */
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
const uint8_t *current = (const uint8_t *)ptr;
#if defined(SEMIHOSTING)
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
sh_writec(current[jj]);
}
return len;
} else {
sh_write(current, fd);
return len;
}
// return len;
#endif
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
*((uint32_t *)0xFFFF0000) = current[jj];
}
return len;
}
return _stub(EBADF);
}
weak_under_alias(write);

71
env/rtl/link.lds vendored
View File

@ -22,13 +22,18 @@ SECTIONS
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
*crt0.o(.text .text.*)
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.init)
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.text .text.*)
*(.stub)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
@ -50,6 +55,13 @@ SECTIONS
. = ALIGN(4);
/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >flash AT>flash :flash
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >flash AT>flash :flash
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
@ -116,13 +128,6 @@ SECTIONS
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.srodata :
{
PROVIDE( _gp = . + 0x800 );
@ -133,9 +138,11 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
.data :
{
__SDATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
@ -158,7 +165,6 @@ SECTIONS
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
@ -171,4 +177,47 @@ SECTIONS
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
/* DWARF Extension. */
.debug_macro 0 : { *(.debug_macro) }
.debug_addr 0 : { *(.debug_addr) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}

16
env/start.S vendored
View File

@ -1,4 +1,3 @@
#include "encoding.h"
// See LICENSE for license details.
.section .init
@ -8,17 +7,12 @@
_start:
.option push
.option norelax
.option norvc
j 1f
.2byte 0x4e4d
.2byte 0x5352
.4byte 0x669
1:
la gp, trap_entry
csrw mtvec, gp
la gp, __global_pointer$
.option pop
la sp, _sp
la t0, trap_entry
csrw mtvec, t0
/* Load data section */
la a0, _data_lma
la a1, _data
@ -43,11 +37,11 @@ _start:
2:
/* Call global constructors */
#ifndef HAVE_NO_INIT_FINI
//#ifdef HAVE_INIT_FINI
la a0, __libc_fini_array
call atexit
call __libc_init_array
#endif
//#endif
#ifndef __riscv_float_abi_soft
/* Enable FPU */
li t0, MSTATUS_FS

2
env/tgc_vp vendored
View File

@ -1 +1 @@
ehrenberg
ehrenberg/

9
include/ehrenberg/devices/aclint.h
View File

@ -1,9 +1,10 @@
#ifndef _DEVICES_ACLINT_H
#define _DEVICES_ACLINT_H
#ifndef _BSP_ACLINT_H
#define _BSP_ACLINT_H
#include <stdint.h>
#include "gen/aclint.h"
#include "gen/Apb3AClint.h"
#define aclint_t apb3aclint_t
static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value){
set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
@ -25,4 +26,4 @@ static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg){
return value;
}
#endif /* _DEVICES_ACLINT_H */
#endif /* _BSP_ACLINT_H */

6
include/ehrenberg/devices/camera.h
View File

@ -1,6 +0,0 @@
#ifndef _DEVICES_CAM_H
#define _DEVICES_CAM_H
#include "gen/camera.h"
#endif /* _DEVICES_CAM_H */

11
include/ehrenberg/devices/dma.h
View File

@ -1,11 +0,0 @@
#ifndef _DEVICES_DMA_H
#define _DEVICES_DMA_H
#include "gen/dma.h"
#define EVENT_UART 1
#define I2S_LEFT_SAMPLE_AVAIL 2
#define I2S_RIGHT_SAMPLE_AVAIL 4
#define CAMERA_PIXEL_AVAIL 8
#endif /* _BSP_DMA_H */

40
include/ehrenberg/devices/gen/aclint.h → include/ehrenberg/devices/gen/Apb3AClint.h
View File

@ -3,16 +3,16 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_ACLINT_H
#define _BSP_ACLINT_H
#ifndef _BSP_APB3ACLINT_H
#define _BSP_APB3ACLINT_H
#include <stdint.h>
typedef struct {
typedef struct __attribute((__packed__)) {
volatile uint32_t MSIP0;
uint8_t fill0[16380];
volatile uint32_t MTIMECMP0LO;
@ -20,7 +20,7 @@ typedef struct {
uint8_t fill1[32752];
volatile uint32_t MTIME_LO;
volatile uint32_t MTIME_HI;
}aclint_t;
}apb3aclint_t;
#define ACLINT_MSIP0_OFFS 0
#define ACLINT_MSIP0_MASK 0x1
@ -43,49 +43,43 @@ typedef struct {
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
//ACLINT_MSIP0
inline uint32_t get_aclint_msip0(volatile aclint_t* reg){
return reg->MSIP0;
}
inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value){
reg->MSIP0 = value;
}
inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg){
inline uint32_t get_aclint_msip0(volatile apb3aclint_t* reg){
return (reg->MSIP0 >> 0) & 0x1;
}
inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value){
inline void set_aclint_msip0(volatile apb3aclint_t* reg, uint8_t value){
reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
}
//ACLINT_MTIMECMP0LO
inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg){
inline uint32_t get_aclint_mtimecmp0lo(volatile apb3aclint_t* reg){
return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
}
inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value){
inline void set_aclint_mtimecmp0lo(volatile apb3aclint_t* reg, uint32_t value){
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
}
//ACLINT_MTIMECMP0HI
inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg){
inline uint32_t get_aclint_mtimecmp0hi(volatile apb3aclint_t* reg){
return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
}
inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value){
inline void set_aclint_mtimecmp0hi(volatile apb3aclint_t* reg, uint32_t value){
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
}
//ACLINT_MTIME_LO
inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg){
inline uint32_t get_aclint_mtime_lo(volatile apb3aclint_t* reg){
return (reg->MTIME_LO >> 0) & 0xffffffff;
}
inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value){
inline void set_aclint_mtime_lo(volatile apb3aclint_t* reg, uint32_t value){
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
}
//ACLINT_MTIME_HI
inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg){
inline uint32_t get_aclint_mtime_hi(volatile apb3aclint_t* reg){
return (reg->MTIME_HI >> 0) & 0xffffffff;
}
inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value){
inline void set_aclint_mtime_hi(volatile apb3aclint_t* reg, uint32_t value){
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_ACLINT_H */
#endif /* _BSP_APB3ACLINT_H */

54
include/ehrenberg/devices/gen/Apb3Gpio.h Normal file
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@ -0,0 +1,54 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_APB3GPIO_H
#define _BSP_APB3GPIO_H
#include <stdint.h>
typedef struct __attribute((__packed__)) {
volatile uint32_t VALUE;
volatile uint32_t WRITE;
volatile uint32_t WRITEENABLE;
}apb3gpio_t;
#define GPIO_VALUE_OFFS 0
#define GPIO_VALUE_MASK 0xffffffff
#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
#define GPIO_WRITE_OFFS 0
#define GPIO_WRITE_MASK 0xffffffff
#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
#define GPIO_WRITEENABLE_OFFS 0
#define GPIO_WRITEENABLE_MASK 0xffffffff
#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
//GPIO_VALUE
inline uint32_t get_gpio_value(volatile apb3gpio_t* reg){
return (reg->VALUE >> 0) & 0xffffffff;
}
//GPIO_WRITE
inline uint32_t get_gpio_write(volatile apb3gpio_t* reg){
return (reg->WRITE >> 0) & 0xffffffff;
}
inline void set_gpio_write(volatile apb3gpio_t* reg, uint32_t value){
reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_WRITEENABLE
inline uint32_t get_gpio_writeEnable(volatile apb3gpio_t* reg){
return (reg->WRITEENABLE >> 0) & 0xffffffff;
}
inline void set_gpio_writeEnable(volatile apb3gpio_t* reg, uint32_t value){
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_APB3GPIO_H */

44
include/ehrenberg/devices/gen/Apb3IrqCtrl.h Normal file
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@ -0,0 +1,44 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_APB3IRQCTRL_H
#define _BSP_APB3IRQCTRL_H
#include <stdint.h>
typedef struct __attribute((__packed__)) {
volatile uint32_t PENDINGSREG;
volatile uint32_t MASKSREG;
}apb3irqctrl_t;
#define IRQ_PENDINGSREG_OFFS 0
#define IRQ_PENDINGSREG_MASK 0xf
#define IRQ_PENDINGSREG(V) ((V & IRQ_PENDINGSREG_MASK) << IRQ_PENDINGSREG_OFFS)
#define IRQ_MASKSREG_OFFS 0
#define IRQ_MASKSREG_MASK 0xf
#define IRQ_MASKSREG(V) ((V & IRQ_MASKSREG_MASK) << IRQ_MASKSREG_OFFS)
//IRQ_PENDINGSREG
inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t* reg){
return (reg->PENDINGSREG >> 0) & 0xf;
}
inline void set_irq_pendingsReg(volatile apb3irqctrl_t* reg, uint8_t value){
reg->PENDINGSREG = (reg->PENDINGSREG & ~(0xfU << 0)) | (value << 0);
}
//IRQ_MASKSREG
inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t* reg){
return (reg->MASKSREG >> 0) & 0xf;
}
inline void set_irq_masksReg(volatile apb3irqctrl_t* reg, uint8_t value){
reg->MASKSREG = (reg->MASKSREG & ~(0xfU << 0)) | (value << 0);
}
#endif /* _BSP_APB3IRQCTRL_H */

382
include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h Normal file
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@ -0,0 +1,382 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_APB3SPIXDRMASTERCTRL_H
#define _BSP_APB3SPIXDRMASTERCTRL_H
#include <stdint.h>
typedef struct __attribute((__packed__)) {
volatile uint32_t DATA;
volatile uint32_t STATUS;
volatile uint32_t CONFIG;
volatile uint32_t INTR;
uint8_t fill0[16];
volatile uint32_t SCLK_CONFIG;
volatile uint32_t SSGEN_SETUP;
volatile uint32_t SSGEN_HOLD;
volatile uint32_t SSGEN_DISABLE;
volatile uint32_t SSGEN_ACTIVE_HIGH;
uint8_t fill1[12];
volatile uint32_t XIP_ENABLE;
volatile uint32_t XIP_CONFIG;
volatile uint32_t XIP_MODE;
uint8_t fill2[4];
volatile uint32_t XIP_WRITE;
volatile uint32_t XIP_READ_WRITE;
volatile uint32_t XIP_READ;
}apb3spixdrmasterctrl_t;
#define SPI_DATA_DATA_OFFS 0
#define SPI_DATA_DATA_MASK 0xff
#define SPI_DATA_DATA(V) ((V & SPI_DATA_DATA_MASK) << SPI_DATA_DATA_OFFS)
#define SPI_DATA_WRITE_OFFS 8
#define SPI_DATA_WRITE_MASK 0x1
#define SPI_DATA_WRITE(V) ((V & SPI_DATA_WRITE_MASK) << SPI_DATA_WRITE_OFFS)
#define SPI_DATA_READ_OFFS 9
#define SPI_DATA_READ_MASK 0x1
#define SPI_DATA_READ(V) ((V & SPI_DATA_READ_MASK) << SPI_DATA_READ_OFFS)
#define SPI_DATA_KIND_OFFS 11
#define SPI_DATA_KIND_MASK 0x1
#define SPI_DATA_KIND(V) ((V & SPI_DATA_KIND_MASK) << SPI_DATA_KIND_OFFS)
#define SPI_DATA_RX_DATA_INVALID_OFFS 31
#define SPI_DATA_RX_DATA_INVALID_MASK 0x1
#define SPI_DATA_RX_DATA_INVALID(V) ((V & SPI_DATA_RX_DATA_INVALID_MASK) << SPI_DATA_RX_DATA_INVALID_OFFS)
#define SPI_STATUS_TX_FREE_OFFS 0
#define SPI_STATUS_TX_FREE_MASK 0x3f
#define SPI_STATUS_TX_FREE(V) ((V & SPI_STATUS_TX_FREE_MASK) << SPI_STATUS_TX_FREE_OFFS)
#define SPI_STATUS_RX_AVAIL_OFFS 16
#define SPI_STATUS_RX_AVAIL_MASK 0x3f
#define SPI_STATUS_RX_AVAIL(V) ((V & SPI_STATUS_RX_AVAIL_MASK) << SPI_STATUS_RX_AVAIL_OFFS)
#define SPI_CONFIG_KIND_OFFS 0
#define SPI_CONFIG_KIND_MASK 0x3
#define SPI_CONFIG_KIND(V) ((V & SPI_CONFIG_KIND_MASK) << SPI_CONFIG_KIND_OFFS)
#define SPI_CONFIG_MODE_OFFS 4
#define SPI_CONFIG_MODE_MASK 0x7
#define SPI_CONFIG_MODE(V) ((V & SPI_CONFIG_MODE_MASK) << SPI_CONFIG_MODE_OFFS)
#define SPI_INTR_TX_IE_OFFS 0
#define SPI_INTR_TX_IE_MASK 0x1
#define SPI_INTR_TX_IE(V) ((V & SPI_INTR_TX_IE_MASK) << SPI_INTR_TX_IE_OFFS)
#define SPI_INTR_RX_IE_OFFS 1
#define SPI_INTR_RX_IE_MASK 0x1
#define SPI_INTR_RX_IE(V) ((V & SPI_INTR_RX_IE_MASK) << SPI_INTR_RX_IE_OFFS)
#define SPI_INTR_TX_IP_OFFS 8
#define SPI_INTR_TX_IP_MASK 0x1
#define SPI_INTR_TX_IP(V) ((V & SPI_INTR_TX_IP_MASK) << SPI_INTR_TX_IP_OFFS)
#define SPI_INTR_RX_IP_OFFS 9
#define SPI_INTR_RX_IP_MASK 0x1
#define SPI_INTR_RX_IP(V) ((V & SPI_INTR_RX_IP_MASK) << SPI_INTR_RX_IP_OFFS)
#define SPI_INTR_TX_ACTIVE_OFFS 16
#define SPI_INTR_TX_ACTIVE_MASK 0x1
#define SPI_INTR_TX_ACTIVE(V) ((V & SPI_INTR_TX_ACTIVE_MASK) << SPI_INTR_TX_ACTIVE_OFFS)
#define SPI_SCLK_CONFIG_OFFS 0
#define SPI_SCLK_CONFIG_MASK 0xfff
#define SPI_SCLK_CONFIG(V) ((V & SPI_SCLK_CONFIG_MASK) << SPI_SCLK_CONFIG_OFFS)
#define SPI_SSGEN_SETUP_OFFS 0
#define SPI_SSGEN_SETUP_MASK 0xfff
#define SPI_SSGEN_SETUP(V) ((V & SPI_SSGEN_SETUP_MASK) << SPI_SSGEN_SETUP_OFFS)
#define SPI_SSGEN_HOLD_OFFS 0
#define SPI_SSGEN_HOLD_MASK 0xfff
#define SPI_SSGEN_HOLD(V) ((V & SPI_SSGEN_HOLD_MASK) << SPI_SSGEN_HOLD_OFFS)
#define SPI_SSGEN_DISABLE_OFFS 0
#define SPI_SSGEN_DISABLE_MASK 0xfff
#define SPI_SSGEN_DISABLE(V) ((V & SPI_SSGEN_DISABLE_MASK) << SPI_SSGEN_DISABLE_OFFS)
#define SPI_SSGEN_ACTIVE_HIGH_OFFS 0
#define SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
#define SPI_SSGEN_ACTIVE_HIGH(V) ((V & SPI_SSGEN_ACTIVE_HIGH_MASK) << SPI_SSGEN_ACTIVE_HIGH_OFFS)
#define SPI_XIP_ENABLE_OFFS 0
#define SPI_XIP_ENABLE_MASK 0x1
#define SPI_XIP_ENABLE(V) ((V & SPI_XIP_ENABLE_MASK) << SPI_XIP_ENABLE_OFFS)
#define SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
#define SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
#define SPI_XIP_CONFIG_INSTRUCTION(V) ((V & SPI_XIP_CONFIG_INSTRUCTION_MASK) << SPI_XIP_CONFIG_INSTRUCTION_OFFS)
#define SPI_XIP_CONFIG_ENABLE_OFFS 8
#define SPI_XIP_CONFIG_ENABLE_MASK 0x1
#define SPI_XIP_CONFIG_ENABLE(V) ((V & SPI_XIP_CONFIG_ENABLE_MASK) << SPI_XIP_CONFIG_ENABLE_OFFS)
#define SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
#define SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
#define SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
#define SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
#define SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
#define SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
#define SPI_XIP_MODE_INSTRUCTION_OFFS 0
#define SPI_XIP_MODE_INSTRUCTION_MASK 0x7
#define SPI_XIP_MODE_INSTRUCTION(V) ((V & SPI_XIP_MODE_INSTRUCTION_MASK) << SPI_XIP_MODE_INSTRUCTION_OFFS)
#define SPI_XIP_MODE_ADDRESS_OFFS 8
#define SPI_XIP_MODE_ADDRESS_MASK 0x7
#define SPI_XIP_MODE_ADDRESS(V) ((V & SPI_XIP_MODE_ADDRESS_MASK) << SPI_XIP_MODE_ADDRESS_OFFS)
#define SPI_XIP_MODE_DUMMY_OFFS 16
#define SPI_XIP_MODE_DUMMY_MASK 0x7
#define SPI_XIP_MODE_DUMMY(V) ((V & SPI_XIP_MODE_DUMMY_MASK) << SPI_XIP_MODE_DUMMY_OFFS)
#define SPI_XIP_MODE_PAYLOAD_OFFS 24
#define SPI_XIP_MODE_PAYLOAD_MASK 0x7
#define SPI_XIP_MODE_PAYLOAD(V) ((V & SPI_XIP_MODE_PAYLOAD_MASK) << SPI_XIP_MODE_PAYLOAD_OFFS)
#define SPI_XIP_WRITE_OFFS 0
#define SPI_XIP_WRITE_MASK 0xff
#define SPI_XIP_WRITE(V) ((V & SPI_XIP_WRITE_MASK) << SPI_XIP_WRITE_OFFS)
#define SPI_XIP_READ_WRITE_OFFS 0
#define SPI_XIP_READ_WRITE_MASK 0xff
#define SPI_XIP_READ_WRITE(V) ((V & SPI_XIP_READ_WRITE_MASK) << SPI_XIP_READ_WRITE_OFFS)
#define SPI_XIP_READ_OFFS 0
#define SPI_XIP_READ_MASK 0xff
#define SPI_XIP_READ(V) ((V & SPI_XIP_READ_MASK) << SPI_XIP_READ_OFFS)
//SPI_DATA
inline uint32_t get_spi_data(volatile apb3spixdrmasterctrl_t* reg){
return reg->DATA;
}
inline void set_spi_data(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->DATA = value;
}
inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_spi_data_write(volatile apb3spixdrmasterctrl_t* reg){
return (reg->DATA >> 8) & 0x1;
}
inline void set_spi_data_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_spi_data_read(volatile apb3spixdrmasterctrl_t* reg){
return (reg->DATA >> 9) & 0x1;
}
inline void set_spi_data_read(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_spi_data_kind(volatile apb3spixdrmasterctrl_t* reg){
return (reg->DATA >> 11) & 0x1;
}
inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
}
inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t* reg){
return (reg->DATA >> 31) & 0x1;
}
//SPI_STATUS
inline uint32_t get_spi_status(volatile apb3spixdrmasterctrl_t* reg){
return reg->STATUS;
}
inline void set_spi_status(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->STATUS = value;
}
inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t* reg){
return (reg->STATUS >> 0) & 0x3f;
}
inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t* reg){
return (reg->STATUS >> 16) & 0x3f;
}
//SPI_CONFIG
inline uint32_t get_spi_config(volatile apb3spixdrmasterctrl_t* reg){
return reg->CONFIG;
}
inline void set_spi_config(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->CONFIG = value;
}
inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t* reg){
return (reg->CONFIG >> 0) & 0x3;
}
inline void set_spi_config_kind(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t* reg){
return (reg->CONFIG >> 4) & 0x7;
}
inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x7U << 4)) | (value << 4);
}
//SPI_INTR
inline uint32_t get_spi_intr(volatile apb3spixdrmasterctrl_t* reg){
return reg->INTR;
}
inline void set_spi_intr(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->INTR = value;
}
inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t* reg){
return (reg->INTR >> 0) & 0x1;
}
inline void set_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t* reg){
return (reg->INTR >> 1) & 0x1;
}
inline void set_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_spi_intr_tx_ip(volatile apb3spixdrmasterctrl_t* reg){
return (reg->INTR >> 8) & 0x1;
}
inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t* reg){
return (reg->INTR >> 9) & 0x1;
}
inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t* reg){
return (reg->INTR >> 16) & 0x1;
}
//SPI_SCLK_CONFIG
inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t* reg){
return (reg->SCLK_CONFIG >> 0) & 0xfff;
}
inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
}
//SPI_SSGEN_SETUP
inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t* reg){
return (reg->SSGEN_SETUP >> 0) & 0xfff;
}
inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
}
//SPI_SSGEN_HOLD
inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t* reg){
return (reg->SSGEN_HOLD >> 0) & 0xfff;
}
inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
}
//SPI_SSGEN_DISABLE
inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t* reg){
return (reg->SSGEN_DISABLE >> 0) & 0xfff;
}
inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
}
//SPI_SSGEN_ACTIVE_HIGH
inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t* reg){
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
}
inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
}
//SPI_XIP_ENABLE
inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_ENABLE >> 0) & 0x1;
}
inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
}
//SPI_XIP_CONFIG
inline uint32_t get_spi_xip_config(volatile apb3spixdrmasterctrl_t* reg){
return reg->XIP_CONFIG;
}
inline void set_spi_xip_config(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->XIP_CONFIG = value;
}
inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_CONFIG >> 0) & 0xff;
}
inline void set_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_CONFIG >> 8) & 0x1;
}
inline void set_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_CONFIG >> 16) & 0xff;
}
inline void set_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
}
inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_CONFIG >> 24) & 0xf;
}
inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
}
//SPI_XIP_MODE
inline uint32_t get_spi_xip_mode(volatile apb3spixdrmasterctrl_t* reg){
return reg->XIP_MODE;
}
inline void set_spi_xip_mode(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
reg->XIP_MODE = value;
}
inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_MODE >> 0) & 0x7;
}
inline void set_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_MODE >> 8) & 0x7;
}
inline void set_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 8)) | (value << 8);
}
inline uint32_t get_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_MODE >> 16) & 0x7;
}
inline void set_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 16)) | (value << 16);
}
inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_MODE >> 24) & 0x7;
}
inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 24)) | (value << 24);
}
//SPI_XIP_WRITE
inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
}
//SPI_XIP_READ_WRITE
inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
}
//SPI_XIP_READ
inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t* reg){
return (reg->XIP_READ >> 0) & 0xff;
}
#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */

135
include/ehrenberg/devices/gen/Apb3Timer.h Normal file
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@ -0,0 +1,135 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_APB3TIMER_H
#define _BSP_APB3TIMER_H
#include <stdint.h>
typedef struct __attribute((__packed__)) {
volatile uint32_t PRESCALER;
volatile uint32_t T0_CTRL;
volatile uint32_t T0_OVERFLOW;
volatile uint32_t T0_VALUE;
volatile uint32_t T1_CTRL;
volatile uint32_t T1_OVERFLOW;
volatile uint32_t T1_VALUE;
}apb3timer_t;
#define TIMER_PRESCALER_OFFS 0
#define TIMER_PRESCALER_MASK 0xffff
#define TIMER_PRESCALER(V) ((V & TIMER_PRESCALER_MASK) << TIMER_PRESCALER_OFFS)
#define TIMER_T0_CTRL_ENABLE_OFFS 0
#define TIMER_T0_CTRL_ENABLE_MASK 0x7
#define TIMER_T0_CTRL_ENABLE(V) ((V & TIMER_T0_CTRL_ENABLE_MASK) << TIMER_T0_CTRL_ENABLE_OFFS)
#define TIMER_T0_CTRL_CLEAR_OFFS 3
#define TIMER_T0_CTRL_CLEAR_MASK 0x3
#define TIMER_T0_CTRL_CLEAR(V) ((V & TIMER_T0_CTRL_CLEAR_MASK) << TIMER_T0_CTRL_CLEAR_OFFS)
#define TIMER_T0_OVERFLOW_OFFS 0
#define TIMER_T0_OVERFLOW_MASK 0xffffffff
#define TIMER_T0_OVERFLOW(V) ((V & TIMER_T0_OVERFLOW_MASK) << TIMER_T0_OVERFLOW_OFFS)
#define TIMER_T0_VALUE_OFFS 0
#define TIMER_T0_VALUE_MASK 0xffffffff
#define TIMER_T0_VALUE(V) ((V & TIMER_T0_VALUE_MASK) << TIMER_T0_VALUE_OFFS)
#define TIMER_T1_CTRL_ENABLE_OFFS 0
#define TIMER_T1_CTRL_ENABLE_MASK 0x7
#define TIMER_T1_CTRL_ENABLE(V) ((V & TIMER_T1_CTRL_ENABLE_MASK) << TIMER_T1_CTRL_ENABLE_OFFS)
#define TIMER_T1_CTRL_CLEAR_OFFS 3
#define TIMER_T1_CTRL_CLEAR_MASK 0x3
#define TIMER_T1_CTRL_CLEAR(V) ((V & TIMER_T1_CTRL_CLEAR_MASK) << TIMER_T1_CTRL_CLEAR_OFFS)
#define TIMER_T1_OVERFLOW_OFFS 0
#define TIMER_T1_OVERFLOW_MASK 0xffffffff
#define TIMER_T1_OVERFLOW(V) ((V & TIMER_T1_OVERFLOW_MASK) << TIMER_T1_OVERFLOW_OFFS)
#define TIMER_T1_VALUE_OFFS 0
#define TIMER_T1_VALUE_MASK 0xffffffff
#define TIMER_T1_VALUE(V) ((V & TIMER_T1_VALUE_MASK) << TIMER_T1_VALUE_OFFS)
//TIMER_PRESCALER
inline uint32_t get_timer_prescaler(volatile apb3timer_t* reg){
return (reg->PRESCALER >> 0) & 0xffff;
}
inline void set_timer_prescaler(volatile apb3timer_t* reg, uint16_t value){
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
}
//TIMER_T0_CTRL
inline uint32_t get_timer_t0_ctrl(volatile apb3timer_t* reg){
return reg->T0_CTRL;
}
inline void set_timer_t0_ctrl(volatile apb3timer_t* reg, uint32_t value){
reg->T0_CTRL = value;
}
inline uint32_t get_timer_t0_ctrl_enable(volatile apb3timer_t* reg){
return (reg->T0_CTRL >> 0) & 0x7;
}
inline void set_timer_t0_ctrl_enable(volatile apb3timer_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timer_t0_ctrl_clear(volatile apb3timer_t* reg){
return (reg->T0_CTRL >> 3) & 0x3;
}
inline void set_timer_t0_ctrl_clear(volatile apb3timer_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
}
//TIMER_T0_OVERFLOW
inline uint32_t get_timer_t0_overflow(volatile apb3timer_t* reg){
return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timer_t0_overflow(volatile apb3timer_t* reg, uint32_t value){
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
//TIMER_T0_VALUE
inline uint32_t get_timer_t0_value(volatile apb3timer_t* reg){
return (reg->T0_VALUE >> 0) & 0xffffffff;
}
//TIMER_T1_CTRL
inline uint32_t get_timer_t1_ctrl(volatile apb3timer_t* reg){
return reg->T1_CTRL;
}
inline void set_timer_t1_ctrl(volatile apb3timer_t* reg, uint32_t value){
reg->T1_CTRL = value;
}
inline uint32_t get_timer_t1_ctrl_enable(volatile apb3timer_t* reg){
return (reg->T1_CTRL >> 0) & 0x7;
}
inline void set_timer_t1_ctrl_enable(volatile apb3timer_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timer_t1_ctrl_clear(volatile apb3timer_t* reg){
return (reg->T1_CTRL >> 3) & 0x3;
}
inline void set_timer_t1_ctrl_clear(volatile apb3timer_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
}
//TIMER_T1_OVERFLOW
inline uint32_t get_timer_t1_overflow(volatile apb3timer_t* reg){
return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timer_t1_overflow(volatile apb3timer_t* reg, uint32_t value){
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
//TIMER_T1_VALUE
inline uint32_t get_timer_t1_value(volatile apb3timer_t* reg){
return (reg->T1_VALUE >> 0) & 0xffffffff;
}
#endif /* _BSP_APB3TIMER_H */

126
include/ehrenberg/devices/gen/uart.h → include/ehrenberg/devices/gen/Apb3Uart.h
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@ -3,22 +3,22 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
* Generated at 2024-03-28 11:47:58 UTC
* by peakrdl_mnrs version 1.2.4
*/
#ifndef _BSP_UART_H
#define _BSP_UART_H
#ifndef _BSP_APB3UART_H
#define _BSP_APB3UART_H
#include <stdint.h>
typedef struct {
typedef struct __attribute((__packed__)) {
volatile uint32_t RX_TX_REG;
volatile uint32_t INT_CTRL_REG;
volatile uint32_t CLK_DIVIDER_REG;
volatile uint32_t FRAME_CONFIG_REG;
volatile uint32_t STATUS_REG;
}uart_t;
}apb3uart_t;
#define UART_RX_TX_REG_DATA_OFFS 0
#define UART_RX_TX_REG_DATA_MASK 0xff
@ -32,10 +32,6 @@ typedef struct {
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
@ -44,10 +40,6 @@ typedef struct {
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
@ -56,17 +48,13 @@ typedef struct {
#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
#define UART_CLK_DIVIDER_REG_OFFS 0
#define UART_CLK_DIVIDER_REG_MASK 0xfffff
#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
#define UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS 0
#define UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK 0x7
#define UART_FRAME_CONFIG_REG_DATA_LENGHT(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS)
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
@ -84,9 +72,9 @@ typedef struct {
#define UART_STATUS_REG_STALL_MASK 0x1
#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
#define UART_STATUS_REG_BREAK_LINE_OFFS 8
#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
#define UART_STATUS_REG_BREAK_OFFS 8
#define UART_STATUS_REG_BREAK_MASK 0x1
#define UART_STATUS_REG_BREAK(V) ((V & UART_STATUS_REG_BREAK_MASK) << UART_STATUS_REG_BREAK_OFFS)
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
@ -101,136 +89,118 @@ typedef struct {
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
//UART_RX_TX_REG
inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){
inline uint32_t get_uart_rx_tx_reg(volatile apb3uart_t* reg){
return reg->RX_TX_REG;
}
inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){
inline void set_uart_rx_tx_reg(volatile apb3uart_t* reg, uint32_t value){
reg->RX_TX_REG = value;
}
inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
inline uint32_t get_uart_rx_tx_reg_data(volatile apb3uart_t* reg){
return (reg->RX_TX_REG >> 0) & 0xff;
}
inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
inline void set_uart_rx_tx_reg_data(volatile apb3uart_t* reg, uint8_t value){
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile apb3uart_t* reg){
return (reg->RX_TX_REG >> 14) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile apb3uart_t* reg){
return (reg->RX_TX_REG >> 15) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
return (reg->RX_TX_REG >> 16) & 0x1;
}
//UART_INT_CTRL_REG
inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
inline uint32_t get_uart_int_ctrl_reg(volatile apb3uart_t* reg){
return reg->INT_CTRL_REG;
}
inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){
inline void set_uart_int_ctrl_reg(volatile apb3uart_t* reg, uint32_t value){
reg->INT_CTRL_REG = value;
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t* reg){
return (reg->INT_CTRL_REG >> 0) & 0x1;
}
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t* reg){
return (reg->INT_CTRL_REG >> 1) & 0x1;
}
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 2) & 0x1;
}
inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile apb3uart_t* reg){
return (reg->INT_CTRL_REG >> 8) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile apb3uart_t* reg){
return (reg->INT_CTRL_REG >> 9) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 10) & 0x1;
}
//UART_CLK_DIVIDER_REG
inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
return reg->CLK_DIVIDER_REG;
}
inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
reg->CLK_DIVIDER_REG = value;
}
inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg){
inline uint32_t get_uart_clk_divider_reg(volatile apb3uart_t* reg){
return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
}
inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value){
inline void set_uart_clk_divider_reg(volatile apb3uart_t* reg, uint32_t value){
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
}
//UART_FRAME_CONFIG_REG
inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){
inline uint32_t get_uart_frame_config_reg(volatile apb3uart_t* reg){
return reg->FRAME_CONFIG_REG;
}
inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){
inline void set_uart_frame_config_reg(volatile apb3uart_t* reg, uint32_t value){
reg->FRAME_CONFIG_REG = value;
}
inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg){
inline uint32_t get_uart_frame_config_reg_data_lenght(volatile apb3uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
}
inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value){
inline void set_uart_frame_config_reg_data_lenght(volatile apb3uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){
inline uint32_t get_uart_frame_config_reg_parity(volatile apb3uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
}
inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){
inline void set_uart_frame_config_reg_parity(volatile apb3uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile apb3uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
}
inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){
inline void set_uart_frame_config_reg_stop_bit(volatile apb3uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
//UART_STATUS_REG
inline uint32_t get_uart_status_reg(volatile uart_t* reg){
inline uint32_t get_uart_status_reg(volatile apb3uart_t* reg){
return reg->STATUS_REG;
}
inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){
inline void set_uart_status_reg(volatile apb3uart_t* reg, uint32_t value){
reg->STATUS_REG = value;
}
inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
inline uint32_t get_uart_status_reg_read_error(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 0) & 0x1;
}
inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
inline uint32_t get_uart_status_reg_stall(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 1) & 0x1;
}
inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
inline uint32_t get_uart_status_reg_break(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 8) & 0x1;
}
inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
inline uint32_t get_uart_status_reg_break_detected(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 9) & 0x1;
}
inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
inline void set_uart_status_reg_break_detected(volatile apb3uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){
inline uint32_t get_uart_status_reg_set_break(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 10) & 0x1;
}
inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
inline void set_uart_status_reg_set_break(volatile apb3uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
}
inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){
inline uint32_t get_uart_status_reg_clear_break(volatile apb3uart_t* reg){
return (reg->STATUS_REG >> 11) & 0x1;
}
inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
inline void set_uart_status_reg_clear_break(volatile apb3uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
}
#endif /* _BSP_UART_H */
#endif /* _BSP_APB3UART_H */

424
include/ehrenberg/devices/gen/apb3spi.h
View File

@ -1,424 +0,0 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-09-10 14:29:50 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_APB3SPI_H
#define _BSP_APB3SPI_H
#include <stdint.h>
typedef struct {
volatile uint32_t DATA;
volatile uint32_t STATUS;
volatile uint32_t CONFIG;
volatile uint32_t INTR;
uint8_t fill0[16];
volatile uint32_t SCLK_CONFIG;
volatile uint32_t SSGEN_SETUP;
volatile uint32_t SSGEN_HOLD;
volatile uint32_t SSGEN_DISABLE;
volatile uint32_t SSGEN_ACTIVE_HIGH;
uint8_t fill1[12];
volatile uint32_t XIP_ENABLE;
volatile uint32_t XIP_CONFIG;
volatile uint32_t XIP_MODE;
uint8_t fill2[4];
volatile uint32_t XIP_WRITE;
volatile uint32_t XIP_READ_WRITE;
volatile uint32_t XIP_READ;
}apb3spi_t;
#define APB3SPI_DATA_DATA_OFFS 0
#define APB3SPI_DATA_DATA_MASK 0xff
#define APB3SPI_DATA_DATA(V) ((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS)
#define APB3SPI_DATA_WRITE_OFFS 8
#define APB3SPI_DATA_WRITE_MASK 0x1
#define APB3SPI_DATA_WRITE(V) ((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS)
#define APB3SPI_DATA_READ_OFFS 9
#define APB3SPI_DATA_READ_MASK 0x1
#define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
#define APB3SPI_DATA_KIND_OFFS 11
#define APB3SPI_DATA_KIND_MASK 0x1
#define APB3SPI_DATA_KIND(V) ((V & APB3SPI_DATA_KIND_MASK) << APB3SPI_DATA_KIND_OFFS)
#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
#define APB3SPI_DATA_RX_DATA_INVALID(V) ((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS)
#define APB3SPI_STATUS_TX_FREE_OFFS 0
#define APB3SPI_STATUS_TX_FREE_MASK 0x3f
#define APB3SPI_STATUS_TX_FREE(V) ((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS)
#define APB3SPI_STATUS_RX_AVAIL_OFFS 16
#define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f
#define APB3SPI_STATUS_RX_AVAIL(V) ((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS)
#define APB3SPI_CONFIG_KIND_OFFS 0
#define APB3SPI_CONFIG_KIND_MASK 0x3
#define APB3SPI_CONFIG_KIND(V) ((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS)
#define APB3SPI_CONFIG_MODE_OFFS 4
#define APB3SPI_CONFIG_MODE_MASK 0x3
#define APB3SPI_CONFIG_MODE(V) ((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS)
#define APB3SPI_INTR_TX_IE_OFFS 0
#define APB3SPI_INTR_TX_IE_MASK 0x1
#define APB3SPI_INTR_TX_IE(V) ((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS)
#define APB3SPI_INTR_RX_IE_OFFS 1
#define APB3SPI_INTR_RX_IE_MASK 0x1
#define APB3SPI_INTR_RX_IE(V) ((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS)
#define APB3SPI_INTR_TX_IP_OFFS 8
#define APB3SPI_INTR_TX_IP_MASK 0x1
#define APB3SPI_INTR_TX_IP(V) ((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS)
#define APB3SPI_INTR_RX_IP_OFFS 9
#define APB3SPI_INTR_RX_IP_MASK 0x1
#define APB3SPI_INTR_RX_IP(V) ((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS)
#define APB3SPI_INTR_TX_ACTIVE_OFFS 16
#define APB3SPI_INTR_TX_ACTIVE_MASK 0x1
#define APB3SPI_INTR_TX_ACTIVE(V) ((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS)
#define APB3SPI_SCLK_CONFIG_OFFS 0
#define APB3SPI_SCLK_CONFIG_MASK 0xfff
#define APB3SPI_SCLK_CONFIG(V) ((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS)
#define APB3SPI_SSGEN_SETUP_OFFS 0
#define APB3SPI_SSGEN_SETUP_MASK 0xfff
#define APB3SPI_SSGEN_SETUP(V) ((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS)
#define APB3SPI_SSGEN_HOLD_OFFS 0
#define APB3SPI_SSGEN_HOLD_MASK 0xfff
#define APB3SPI_SSGEN_HOLD(V) ((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS)
#define APB3SPI_SSGEN_DISABLE_OFFS 0
#define APB3SPI_SSGEN_DISABLE_MASK 0xfff
#define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
#define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
#define APB3SPI_XIP_ENABLE_OFFS 0
#define APB3SPI_XIP_ENABLE_MASK 0x1
#define APB3SPI_XIP_ENABLE(V) ((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS)
#define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
#define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) ((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) << APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS)
#define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8
#define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1
#define APB3SPI_XIP_CONFIG_ENABLE(V) ((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS)
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
#define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0
#define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3
#define APB3SPI_XIP_MODE_INSTRUCTION(V) ((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS)
#define APB3SPI_XIP_MODE_ADDRESS_OFFS 8
#define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3
#define APB3SPI_XIP_MODE_ADDRESS(V) ((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS)
#define APB3SPI_XIP_MODE_DUMMY_OFFS 16
#define APB3SPI_XIP_MODE_DUMMY_MASK 0x3
#define APB3SPI_XIP_MODE_DUMMY(V) ((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS)
#define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24
#define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3
#define APB3SPI_XIP_MODE_PAYLOAD(V) ((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS)
#define APB3SPI_XIP_WRITE_OFFS 0
#define APB3SPI_XIP_WRITE_MASK 0xff
#define APB3SPI_XIP_WRITE(V) ((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS)
#define APB3SPI_XIP_READ_WRITE_OFFS 0
#define APB3SPI_XIP_READ_WRITE_MASK 0xff
#define APB3SPI_XIP_READ_WRITE(V) ((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS)
#define APB3SPI_XIP_READ_OFFS 0
#define APB3SPI_XIP_READ_MASK 0xff
#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
//APB3SPI_DATA
inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg){
return reg->DATA;
}
inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value){
reg->DATA = value;
}
inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg){
return (reg->DATA >> 8) & 0x1;
}
inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg){
return (reg->DATA >> 9) & 0x1;
}
inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_apb3spi_data_kind(volatile apb3spi_t* reg){
return (reg->DATA >> 11) & 0x1;
}
inline void set_apb3spi_data_kind(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
}
inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){
return (reg->DATA >> 31) & 0x1;
}
//APB3SPI_STATUS
inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg){
return reg->STATUS;
}
inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg){
return (reg->STATUS >> 0) & 0x3f;
}
inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg){
return (reg->STATUS >> 16) & 0x3f;
}
//APB3SPI_CONFIG
inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg){
return reg->CONFIG;
}
inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value){
reg->CONFIG = value;
}
inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg){
return (reg->CONFIG >> 0) & 0x3;
}
inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg){
return (reg->CONFIG >> 4) & 0x3;
}
inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
}
//APB3SPI_INTR
inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg){
return reg->INTR;
}
inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value){
reg->INTR = value;
}
inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg){
return (reg->INTR >> 0) & 0x1;
}
inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg){
return (reg->INTR >> 1) & 0x1;
}
inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg){
return (reg->INTR >> 8) & 0x1;
}
inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg){
return (reg->INTR >> 9) & 0x1;
}
inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){
return (reg->INTR >> 16) & 0x1;
}
//APB3SPI_SCLK_CONFIG
inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg){
return reg->SCLK_CONFIG;
}
inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value){
reg->SCLK_CONFIG = value;
}
inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg){
return (reg->SCLK_CONFIG >> 0) & 0xfff;
}
inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value){
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
}
//APB3SPI_SSGEN_SETUP
inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg){
return reg->SSGEN_SETUP;
}
inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_SETUP = value;
}
inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_SETUP >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
}
//APB3SPI_SSGEN_HOLD
inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg){
return reg->SSGEN_HOLD;
}
inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_HOLD = value;
}
inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_HOLD >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
}
//APB3SPI_SSGEN_DISABLE
inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg){
return reg->SSGEN_DISABLE;
}
inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_DISABLE = value;
}
inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_DISABLE >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
}
//APB3SPI_SSGEN_ACTIVE_HIGH
inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){
return reg->SSGEN_ACTIVE_HIGH;
}
inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_ACTIVE_HIGH = value;
}
inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg){
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
}
inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value){
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
}
//APB3SPI_XIP_ENABLE
inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg){
return reg->XIP_ENABLE;
}
inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_ENABLE = value;
}
inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg){
return (reg->XIP_ENABLE >> 0) & 0x1;
}
inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
}
//APB3SPI_XIP_CONFIG
inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg){
return reg->XIP_CONFIG;
}
inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_CONFIG = value;
}
inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 0) & 0xff;
}
inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 8) & 0x1;
}
inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 16) & 0xff;
}
inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
}
inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 24) & 0xf;
}
inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
}
//APB3SPI_XIP_MODE
inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg){
return reg->XIP_MODE;
}
inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_MODE = value;
}
inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 0) & 0x3;
}
inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 8) & 0x3;
}
inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 16) & 0x3;
}
inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
}
inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 24) & 0x3;
}
inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
}
//APB3SPI_XIP_WRITE
inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_WRITE = value;
}
inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
}
//APB3SPI_XIP_READ_WRITE
inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_READ_WRITE = value;
}
inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
}
//APB3SPI_XIP_READ
inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg){
return reg->XIP_READ;
}
inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg){
return (reg->XIP_READ >> 0) & 0xff;
}
#endif /* _BSP_APB3SPI_H */

127
include/ehrenberg/devices/gen/camera.h
View File

@ -1,127 +0,0 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-09-10 14:29:50 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_CAMERA_H
#define _BSP_CAMERA_H
#include <stdint.h>
typedef struct {
volatile uint32_t PIXEL;
volatile uint32_t STATUS;
volatile uint32_t CAMERA_CLOCK_CTRL;
volatile uint32_t IE;
volatile uint32_t IP;
}camera_t;
#define CAMERA_PIXEL_OFFS 0
#define CAMERA_PIXEL_MASK 0x7ff
#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
#define CAMERA_STATUS_OFFS 0
#define CAMERA_STATUS_MASK 0x1
#define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfffff
#define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
#define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1
#define CAMERA_IE_EN_PIXEL_AVAIL(V) ((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS)
#define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1
#define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1
#define CAMERA_IE_EN_FRAME_FINISHED(V) ((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS)
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1
#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) ((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) << CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS)
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
//CAMERA_PIXEL
inline uint32_t get_camera_pixel(volatile camera_t* reg){
return reg->PIXEL;
}
inline void set_camera_pixel(volatile camera_t* reg, uint32_t value){
reg->PIXEL = value;
}
inline uint32_t get_camera_pixel_data(volatile camera_t* reg){
return (reg->PIXEL >> 0) & 0x7ff;
}
inline void set_camera_pixel_data(volatile camera_t* reg, uint16_t value){
reg->PIXEL = (reg->PIXEL & ~(0x7ffU << 0)) | (value << 0);
}
//CAMERA_STATUS
inline uint32_t get_camera_status(volatile camera_t* reg){
return reg->STATUS;
}
inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
//CAMERA_CAMERA_CLOCK_CTRL
inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg){
return reg->CAMERA_CLOCK_CTRL;
}
inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value){
reg->CAMERA_CLOCK_CTRL = value;
}
inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg){
return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfffff;
}
inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint32_t value){
reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
}
//CAMERA_IE
inline uint32_t get_camera_ie(volatile camera_t* reg){
return reg->IE;
}
inline void set_camera_ie(volatile camera_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
//CAMERA_IP
inline uint32_t get_camera_ip(volatile camera_t* reg){
return reg->IP;
}
inline void set_camera_ip(volatile camera_t* reg, uint32_t value){
reg->IP = value;
}
inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value){
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg){
return (reg->IP >> 1) & 0x1;
}
inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value){
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
}
#endif /* _BSP_CAMERA_H */

454
include/ehrenberg/devices/gen/dma.h
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@ -1,454 +0,0 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_DMA_H
#define _BSP_DMA_H
#include <stdint.h>
typedef struct {
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t CH0_EVENT;
volatile uint32_t CH0_TRANSFER;
volatile uint32_t CH0_SRC_START_ADDR;
volatile uint32_t CH0_SRC_ADDR_INC;
volatile uint32_t CH0_DST_START_ADDR;
volatile uint32_t CH0_DST_ADDR_INC;
volatile uint32_t CH1_EVENT;
volatile uint32_t CH1_TRANSFER;
volatile uint32_t CH1_SRC_START_ADDR;
volatile uint32_t CH1_SRC_ADDR_INC;
volatile uint32_t CH1_DST_START_ADDR;
volatile uint32_t CH1_DST_ADDR_INC;
}dma_t;
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
#define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
#define DMA_STATUS_CH0_BUSY_OFFS 0
#define DMA_STATUS_CH0_BUSY_MASK 0x1
#define DMA_STATUS_CH0_BUSY(V) ((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS)
#define DMA_STATUS_CH1_BUSY_OFFS 1
#define DMA_STATUS_CH1_BUSY_MASK 0x1
#define DMA_STATUS_CH1_BUSY(V) ((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS)
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
#define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
#define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
#define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
#define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
#define DMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
#define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
#define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
#define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
#define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
#define DMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
#define DMA_CH0_EVENT_SELECT_OFFS 0
#define DMA_CH0_EVENT_SELECT_MASK 0x1f
#define DMA_CH0_EVENT_SELECT(V) ((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS)
#define DMA_CH0_EVENT_COMBINE_OFFS 31
#define DMA_CH0_EVENT_COMBINE_MASK 0x1
#define DMA_CH0_EVENT_COMBINE(V) ((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS)
#define DMA_CH0_TRANSFER_WIDTH_OFFS 0
#define DMA_CH0_TRANSFER_WIDTH_MASK 0x3
#define DMA_CH0_TRANSFER_WIDTH(V) ((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS)
#define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
#define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define DMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
#define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
#define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
#define DMA_CH0_TRANSFER_SEG_COUNT(V) ((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS)
#define DMA_CH0_SRC_START_ADDR_OFFS 0
#define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff
#define DMA_CH0_SRC_START_ADDR(V) ((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS)
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
#define DMA_CH0_DST_START_ADDR_OFFS 0
#define DMA_CH0_DST_START_ADDR_MASK 0xffffffff
#define DMA_CH0_DST_START_ADDR(V) ((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS)
#define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
#define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
#define DMA_CH1_EVENT_SELECT_OFFS 0
#define DMA_CH1_EVENT_SELECT_MASK 0x1f
#define DMA_CH1_EVENT_SELECT(V) ((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS)
#define DMA_CH1_EVENT_COMBINE_OFFS 31
#define DMA_CH1_EVENT_COMBINE_MASK 0x1
#define DMA_CH1_EVENT_COMBINE(V) ((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS)
#define DMA_CH1_TRANSFER_WIDTH_OFFS 0
#define DMA_CH1_TRANSFER_WIDTH_MASK 0x3
#define DMA_CH1_TRANSFER_WIDTH(V) ((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS)
#define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
#define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define DMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
#define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
#define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
#define DMA_CH1_TRANSFER_SEG_COUNT(V) ((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS)
#define DMA_CH1_SRC_START_ADDR_OFFS 0
#define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff
#define DMA_CH1_SRC_START_ADDR(V) ((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS)
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
#define DMA_CH1_DST_START_ADDR_OFFS 0
#define DMA_CH1_DST_START_ADDR_MASK 0xffffffff
#define DMA_CH1_DST_START_ADDR(V) ((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS)
#define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
#define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
//DMA_CONTROL
inline uint32_t get_dma_control(volatile dma_t* reg){
return reg->CONTROL;
}
inline void set_dma_control(volatile dma_t* reg, uint32_t value){
reg->CONTROL = value;
}
inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg){
return (reg->CONTROL >> 0) & 0x1;
}
inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg){
return (reg->CONTROL >> 1) & 0x1;
}
inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
}
//DMA_STATUS
inline uint32_t get_dma_status(volatile dma_t* reg){
return reg->STATUS;
}
inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
//DMA_IE
inline uint32_t get_dma_ie(volatile dma_t* reg){
return reg->IE;
}
inline void set_dma_ie(volatile dma_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg){
return (reg->IE >> 2) & 0x1;
}
inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg){
return (reg->IE >> 3) & 0x1;
}
inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
}
//DMA_IP
inline uint32_t get_dma_ip(volatile dma_t* reg){
return reg->IP;
}
inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg){
return (reg->IP >> 1) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg){
return (reg->IP >> 2) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg){
return (reg->IP >> 3) & 0x1;
}
//DMA_CH0_EVENT
inline uint32_t get_dma_ch0_event(volatile dma_t* reg){
return reg->CH0_EVENT;
}
inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value){
reg->CH0_EVENT = value;
}
inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg){
return (reg->CH0_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value){
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg){
return (reg->CH0_EVENT >> 31) & 0x1;
}
inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value){
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
}
//DMA_CH0_TRANSFER
inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg){
return reg->CH0_TRANSFER;
}
inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value){
reg->CH0_TRANSFER = value;
}
inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 2) & 0x3ff;
}
inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 12) & 0xfffff;
}
inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
//DMA_CH0_SRC_START_ADDR
inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg){
return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
//DMA_CH0_SRC_ADDR_INC
inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg){
return reg->CH0_SRC_ADDR_INC;
}
inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_ADDR_INC = value;
}
inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg){
return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg){
return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
//DMA_CH0_DST_START_ADDR
inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg){
return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
//DMA_CH0_DST_ADDR_INC
inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg){
return reg->CH0_DST_ADDR_INC;
}
inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH0_DST_ADDR_INC = value;
}
inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg){
return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg){
return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
//DMA_CH1_EVENT
inline uint32_t get_dma_ch1_event(volatile dma_t* reg){
return reg->CH1_EVENT;
}
inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value){
reg->CH1_EVENT = value;
}
inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg){
return (reg->CH1_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value){
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg){
return (reg->CH1_EVENT >> 31) & 0x1;
}
inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value){
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
}
//DMA_CH1_TRANSFER
inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg){
return reg->CH1_TRANSFER;
}
inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value){
reg->CH1_TRANSFER = value;
}
inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 2) & 0x3ff;
}
inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 12) & 0xfffff;
}
inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
//DMA_CH1_SRC_START_ADDR
inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg){
return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
//DMA_CH1_SRC_ADDR_INC
inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg){
return reg->CH1_SRC_ADDR_INC;
}
inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg){
return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg){
return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
//DMA_CH1_DST_START_ADDR
inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg){
return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
//DMA_CH1_DST_ADDR_INC
inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg){
return reg->CH1_DST_ADDR_INC;
}
inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg){
return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg){
return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
#endif /* _BSP_DMA_H */

119
include/ehrenberg/devices/gen/gpio.h
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-09 14:18:51 UTC
* by peakrdl_mnrs version 1.2.8
*/
#ifndef _BSP_GPIO_H
#define _BSP_GPIO_H
#include <stdint.h>
typedef struct {
volatile uint32_t VALUE;
volatile uint32_t WRITE;
volatile uint32_t WRITEENABLE;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t IRQ_TRIGGER;
volatile uint32_t IRQ_TYPE;
volatile uint32_t BOOT_SEL;
}gpio_t;
#define GPIO_VALUE_OFFS 0
#define GPIO_VALUE_MASK 0xffffffff
#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
#define GPIO_WRITE_OFFS 0
#define GPIO_WRITE_MASK 0xffffffff
#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
#define GPIO_WRITEENABLE_OFFS 0
#define GPIO_WRITEENABLE_MASK 0xffffffff
#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
#define GPIO_IE_OFFS 0
#define GPIO_IE_MASK 0xffffffff
#define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
#define GPIO_IP_OFFS 0
#define GPIO_IP_MASK 0xffffffff
#define GPIO_IP(V) ((V & GPIO_IP_MASK) << GPIO_IP_OFFS)
#define GPIO_IRQ_TRIGGER_OFFS 0
#define GPIO_IRQ_TRIGGER_MASK 0xffffffff
#define GPIO_IRQ_TRIGGER(V) ((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS)
#define GPIO_IRQ_TYPE_OFFS 0
#define GPIO_IRQ_TYPE_MASK 0xffffffff
#define GPIO_IRQ_TYPE(V) ((V & GPIO_IRQ_TYPE_MASK) << GPIO_IRQ_TYPE_OFFS)
#define GPIO_BOOT_SEL_OFFS 0
#define GPIO_BOOT_SEL_MASK 0x7
#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
//GPIO_VALUE
inline uint32_t get_gpio_value(volatile gpio_t* reg){
return (reg->VALUE >> 0) & 0xffffffff;
}
//GPIO_WRITE
inline uint32_t get_gpio_write(volatile gpio_t* reg){
return (reg->WRITE >> 0) & 0xffffffff;
}
inline void set_gpio_write(volatile gpio_t* reg, uint32_t value){
reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_WRITEENABLE
inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg){
return (reg->WRITEENABLE >> 0) & 0xffffffff;
}
inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_IE
inline uint32_t get_gpio_ie(volatile gpio_t* reg){
return (reg->IE >> 0) & 0xffffffff;
}
inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value){
reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_IP
inline uint32_t get_gpio_ip(volatile gpio_t* reg){
return (reg->IP >> 0) & 0xffffffff;
}
inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value){
reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_IRQ_TRIGGER
inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg){
return (reg->IRQ_TRIGGER >> 0) & 0xffffffff;
}
inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value){
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_IRQ_TYPE
inline uint32_t get_gpio_irq_type(volatile gpio_t* reg){
return (reg->IRQ_TYPE >> 0) & 0xffffffff;
}
inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value){
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_BOOT_SEL
inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg){
return reg->BOOT_SEL;
}
inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg){
return (reg->BOOT_SEL >> 0) & 0x7;
}
#endif /* _BSP_GPIO_H */

228
include/ehrenberg/devices/gen/i2s.h
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-09-10 14:29:50 UTC
* by peakrdl_mnrs version 1.2.9
*/
#ifndef _BSP_I2S_H
#define _BSP_I2S_H
#include <stdint.h>
typedef struct {
volatile uint32_t LEFT_CH;
volatile uint32_t RIGHT_CH;
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
volatile uint32_t I2S_CLOCK_CTRL;
volatile uint32_t PDM_CLOCK_CTRL;
volatile uint32_t IE;
volatile uint32_t IP;
}i2s_t;
#define I2S_LEFT_CH_OFFS 0
#define I2S_LEFT_CH_MASK 0xffffffff
#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)
#define I2S_RIGHT_CH_OFFS 0
#define I2S_RIGHT_CH_MASK 0xffffffff
#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)
#define I2S_CONTROL_MODE_OFFS 0
#define I2S_CONTROL_MODE_MASK 0x3
#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)
#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)
#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
#define I2S_CONTROL_IS_MASTER_OFFS 4
#define I2S_CONTROL_IS_MASTER_MASK 0x1
#define I2S_CONTROL_IS_MASTER(V) ((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS)
#define I2S_CONTROL_SAMPLE_SIZE_OFFS 5
#define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3
#define I2S_CONTROL_SAMPLE_SIZE(V) ((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS)
#define I2S_CONTROL_PDM_SCALE_OFFS 7
#define I2S_CONTROL_PDM_SCALE_MASK 0x7
#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
#define I2S_STATUS_ENABLED_OFFS 0
#define I2S_STATUS_ENABLED_MASK 0x1
#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)
#define I2S_STATUS_ACTIVE_OFFS 1
#define I2S_STATUS_ACTIVE_MASK 0x1
#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)
#define I2S_STATUS_LEFT_AVAIL_OFFS 2
#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)
#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
#define I2S_I2S_CLOCK_CTRL_OFFS 0
#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
#define I2S_PDM_CLOCK_CTRL_OFFS 0
#define I2S_PDM_CLOCK_CTRL_MASK 0x3ff
#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)
#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)
#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
//I2S_LEFT_CH
inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){
return (reg->LEFT_CH >> 0) & 0xffffffff;
}
//I2S_RIGHT_CH
inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){
return (reg->RIGHT_CH >> 0) & 0xffffffff;
}
//I2S_CONTROL
inline uint32_t get_i2s_control(volatile i2s_t* reg){
return reg->CONTROL;
}
inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){
reg->CONTROL = value;
}
inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){
return (reg->CONTROL >> 0) & 0x3;
}
inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){
return (reg->CONTROL >> 2) & 0x1;
}
inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){
return (reg->CONTROL >> 3) & 0x1;
}
inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
}
inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg){
return (reg->CONTROL >> 4) & 0x1;
}
inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
}
inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg){
return (reg->CONTROL >> 5) & 0x3;
}
inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
}
inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){
return (reg->CONTROL >> 7) & 0x7;
}
inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
}
//I2S_STATUS
inline uint32_t get_i2s_status(volatile i2s_t* reg){
return reg->STATUS;
}
inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
inline uint32_t get_i2s_status_active(volatile i2s_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
return (reg->STATUS >> 2) & 0x1;
}
inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
return (reg->STATUS >> 3) & 0x1;
}
//I2S_I2S_CLOCK_CTRL
inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
return reg->I2S_CLOCK_CTRL;
}
inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){
reg->I2S_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
}
inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value){
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
}
//I2S_PDM_CLOCK_CTRL
inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){
return reg->PDM_CLOCK_CTRL;
}
inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){
reg->PDM_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff;
}
inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint16_t value){
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0);
}
//I2S_IE
inline uint32_t get_i2s_ie(volatile i2s_t* reg){
return reg->IE;
}
inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
//I2S_IP
inline uint32_t get_i2s_ip(volatile i2s_t* reg){
return reg->IP;
}
inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){
return (reg->IP >> 1) & 0x1;
}
#endif /* _BSP_I2S_H */

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include/ehrenberg/devices/gen/msgif.h
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-11-05 12:12:15 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_MSGIF_H
#define _BSP_MSGIF_H
#include <stdint.h>
typedef struct {
volatile uint32_t REG_SEND;
volatile uint32_t REG_HEADER;
volatile uint32_t REG_ACK;
volatile uint32_t REG_RECV_ID;
volatile uint32_t REG_RECV_PAYLOAD;
uint8_t fill0[12];
volatile uint32_t REG_PAYLOAD_0;
volatile uint32_t REG_PAYLOAD_1;
volatile uint32_t REG_PAYLOAD_2;
volatile uint32_t REG_PAYLOAD_3;
volatile uint32_t REG_PAYLOAD_4;
volatile uint32_t REG_PAYLOAD_5;
volatile uint32_t REG_PAYLOAD_6;
volatile uint32_t REG_PAYLOAD_7;
}msgif_t;
#define MSGIF_REG_SEND_OFFS 0
#define MSGIF_REG_SEND_MASK 0x1
#define MSGIF_REG_SEND(V) ((V & MSGIF_REG_SEND_MASK) << MSGIF_REG_SEND_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 0
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 3
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 5
#define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) ((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) << MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS)
#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 9
#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
#define MSGIF_REG_ACK_OFFS 0
#define MSGIF_REG_ACK_MASK 0x1
#define MSGIF_REG_ACK(V) ((V & MSGIF_REG_ACK_MASK) << MSGIF_REG_ACK_OFFS)
#define MSGIF_REG_RECV_ID_OFFS 0
#define MSGIF_REG_RECV_ID_MASK 0xf
#define MSGIF_REG_RECV_ID(V) ((V & MSGIF_REG_RECV_ID_MASK) << MSGIF_REG_RECV_ID_OFFS)
#define MSGIF_REG_RECV_PAYLOAD_OFFS 0
#define MSGIF_REG_RECV_PAYLOAD_MASK 0xffffffff
#define MSGIF_REG_RECV_PAYLOAD(V) ((V & MSGIF_REG_RECV_PAYLOAD_MASK) << MSGIF_REG_RECV_PAYLOAD_OFFS)
#define MSGIF_REG_PAYLOAD_0_OFFS 0
#define MSGIF_REG_PAYLOAD_0_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_0(V) ((V & MSGIF_REG_PAYLOAD_0_MASK) << MSGIF_REG_PAYLOAD_0_OFFS)
#define MSGIF_REG_PAYLOAD_1_OFFS 0
#define MSGIF_REG_PAYLOAD_1_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_1(V) ((V & MSGIF_REG_PAYLOAD_1_MASK) << MSGIF_REG_PAYLOAD_1_OFFS)
#define MSGIF_REG_PAYLOAD_2_OFFS 0
#define MSGIF_REG_PAYLOAD_2_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_2(V) ((V & MSGIF_REG_PAYLOAD_2_MASK) << MSGIF_REG_PAYLOAD_2_OFFS)
#define MSGIF_REG_PAYLOAD_3_OFFS 0
#define MSGIF_REG_PAYLOAD_3_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_3(V) ((V & MSGIF_REG_PAYLOAD_3_MASK) << MSGIF_REG_PAYLOAD_3_OFFS)
#define MSGIF_REG_PAYLOAD_4_OFFS 0
#define MSGIF_REG_PAYLOAD_4_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_4(V) ((V & MSGIF_REG_PAYLOAD_4_MASK) << MSGIF_REG_PAYLOAD_4_OFFS)
#define MSGIF_REG_PAYLOAD_5_OFFS 0
#define MSGIF_REG_PAYLOAD_5_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_5(V) ((V & MSGIF_REG_PAYLOAD_5_MASK) << MSGIF_REG_PAYLOAD_5_OFFS)
#define MSGIF_REG_PAYLOAD_6_OFFS 0
#define MSGIF_REG_PAYLOAD_6_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_6(V) ((V & MSGIF_REG_PAYLOAD_6_MASK) << MSGIF_REG_PAYLOAD_6_OFFS)
#define MSGIF_REG_PAYLOAD_7_OFFS 0
#define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff
#define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
//MSGIF_REG_SEND
inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value){
reg->REG_SEND = value;
}
inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value){
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
}
//MSGIF_REG_HEADER
inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg){
return reg->REG_HEADER;
}
inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value){
reg->REG_HEADER = value;
}
inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg){
return (reg->REG_HEADER >> 0) & 0x7;
}
inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg){
return (reg->REG_HEADER >> 3) & 0x3;
}
inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg){
return (reg->REG_HEADER >> 5) & 0xf;
}
inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 5)) | (value << 5);
}
inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg){
return (reg->REG_HEADER >> 9) & 0xf;
}
inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 9)) | (value << 9);
}
//MSGIF_REG_ACK
inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value){
reg->REG_ACK = value;
}
inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value){
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
}
//MSGIF_REG_RECV_ID
inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg){
return reg->REG_RECV_ID;
}
inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg){
return (reg->REG_RECV_ID >> 0) & 0xf;
}
//MSGIF_REG_RECV_PAYLOAD
inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg){
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
}
//MSGIF_REG_PAYLOAD_0
inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
}
//MSGIF_REG_PAYLOAD_1
inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
}
//MSGIF_REG_PAYLOAD_2
inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
}
//MSGIF_REG_PAYLOAD_3
inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
}
//MSGIF_REG_PAYLOAD_4
inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
}
//MSGIF_REG_PAYLOAD_5
inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
}
//MSGIF_REG_PAYLOAD_6
inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
}
//MSGIF_REG_PAYLOAD_7
inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value){
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_MSGIF_H */

141
include/ehrenberg/devices/gen/timercounter.h
View File

@ -1,141 +0,0 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_TIMERCOUNTER_H
#define _BSP_TIMERCOUNTER_H
#include <stdint.h>
typedef struct {
volatile uint32_t PRESCALER;
volatile uint32_t T0_CTRL;
volatile uint32_t T0_OVERFLOW;
volatile uint32_t T0_VALUE;
volatile uint32_t T1_CTRL;
volatile uint32_t T1_OVERFLOW;
volatile uint32_t T1_VALUE;
}timercounter_t;
#define TIMERCOUNTER_PRESCALER_OFFS 0
#define TIMERCOUNTER_PRESCALER_MASK 0xffff
#define TIMERCOUNTER_PRESCALER(V) ((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS)
#define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0
#define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7
#define TIMERCOUNTER_T0_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS)
#define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3
#define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3
#define TIMERCOUNTER_T0_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS)
#define TIMERCOUNTER_T0_OVERFLOW_OFFS 0
#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
#define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
#define TIMERCOUNTER_T0_VALUE_OFFS 0
#define TIMERCOUNTER_T0_VALUE_MASK 0xffffffff
#define TIMERCOUNTER_T0_VALUE(V) ((V & TIMERCOUNTER_T0_VALUE_MASK) << TIMERCOUNTER_T0_VALUE_OFFS)
#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
#define TIMERCOUNTER_T1_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS)
#define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3
#define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3
#define TIMERCOUNTER_T1_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS)
#define TIMERCOUNTER_T1_OVERFLOW_OFFS 0
#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
#define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
#define TIMERCOUNTER_T1_VALUE_OFFS 0
#define TIMERCOUNTER_T1_VALUE_MASK 0xffffffff
#define TIMERCOUNTER_T1_VALUE(V) ((V & TIMERCOUNTER_T1_VALUE_MASK) << TIMERCOUNTER_T1_VALUE_OFFS)
//TIMERCOUNTER_PRESCALER
inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){
return reg->PRESCALER;
}
inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value){
reg->PRESCALER = value;
}
inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg){
return (reg->PRESCALER >> 0) & 0xffff;
}
inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value){
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
}
//TIMERCOUNTER_T0_CTRL
inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg){
return reg->T0_CTRL;
}
inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value){
reg->T0_CTRL = value;
}
inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg){
return (reg->T0_CTRL >> 0) & 0x7;
}
inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg){
return (reg->T0_CTRL >> 3) & 0x3;
}
inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
}
//TIMERCOUNTER_T0_OVERFLOW
inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg){
return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value){
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
//TIMERCOUNTER_T0_VALUE
inline uint32_t get_timercounter_t0_value(volatile timercounter_t* reg){
return (reg->T0_VALUE >> 0) & 0xffffffff;
}
//TIMERCOUNTER_T1_CTRL
inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg){
return reg->T1_CTRL;
}
inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value){
reg->T1_CTRL = value;
}
inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg){
return (reg->T1_CTRL >> 0) & 0x7;
}
inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg){
return (reg->T1_CTRL >> 3) & 0x3;
}
inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
}
//TIMERCOUNTER_T1_OVERFLOW
inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg){
return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value){
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
//TIMERCOUNTER_T1_VALUE
inline uint32_t get_timercounter_t1_value(volatile timercounter_t* reg){
return (reg->T1_VALUE >> 0) & 0xffffffff;
}
#endif /* _BSP_TIMERCOUNTER_H */

12
include/ehrenberg/devices/gpio.h
View File

@ -1,12 +1,14 @@
#ifndef _DEVICES_GPIO_H
#define _DEVICES_GPIO_H
#ifndef _BSP_GPIO_H
#define _BSP_GPIO_H
#include <stdint.h>
#include "gen/gpio.h"
#include "gen/Apb3Gpio.h"
inline void gpio_init(volatile gpio_t* reg) {
#define gpio_t apb3gpio_t
inline void gpio_init(gpio_t* reg) {
set_gpio_write(reg, 0);
set_gpio_writeEnable(reg, 0);
}
#endif /* _DEVICES_GPIO_H */
#endif /* _BSP_GPIO_H */

9
include/ehrenberg/devices/i2s.h
View File

@ -1,9 +0,0 @@
#ifndef _DEVICES_IIS_H
#define _DEVICES_IIS_H
#include "gen/i2s.h"
#define MODE_I2S 1
#define MODE_PDM 2
#endif /* _DEVICES_IIS_H */

13
include/ehrenberg/devices/interrupt.h
View File

@ -1,11 +1,14 @@
#ifndef _DEVICES_INTERRUPT_H
#define _DEVICES_INTERRUPT_H
#ifndef _BSP_INTERRUPT_H
#define _BSP_INTERRUPT_H
#include <stdint.h>
#include "gen/Apb3IrqCtrl.h"
#define irq_t void*
#define irq_t apb3irqctrl_t
inline void irq_init(volatile irq_t* reg){
inline void irq_init(irq_t* reg){
set_irq_masksReg(reg, 0);
set_irq_pendingsReg(reg, 0xff);
}
#endif /* _DEVICES_INTERRUPT_H */
#endif /* _BSP_INTERRUPT_H */

6
include/ehrenberg/devices/msg_if.h
View File

@ -1,6 +0,0 @@
#ifndef _DEVICES_MSG_IF_H
#define _DEVICES_MSG_IF_H
#include "gen/msgif.h"
#endif /* _DEVICES_MSG_IF_H */

72
include/ehrenberg/devices/qspi.h
View File

@ -1,10 +1,10 @@
#ifndef _DEVICES_QSPI_H
#define _DEVICES_QSPI_H
#ifndef _BSP_QSPI_H
#define _BSP_QSPI_H
#include <stdint.h>
#include "gen/apb3spi.h"
#include "gen/Apb3SpiXdrMasterCtrl.h"
#define qspi_t apb3spi_t
#define qspi_t apb3spixdrmasterctrl_t
typedef struct {
uint32_t cpol;
uint32_t cpha;
@ -26,12 +26,12 @@ typedef struct {
#define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
static inline void spi_configure(volatile qspi_t* qspi, spi_cfg *config){
set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4));
set_apb3spi_sclk_config(qspi, config->clkDivider);
set_apb3spi_ssgen_setup(qspi, config->ssSetup);
set_apb3spi_ssgen_hold(qspi, config->ssHold);
set_apb3spi_ssgen_disable(qspi, config->ssDisable);
static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
reg->CONFIG = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
reg->SCLK_CONFIG = config->clkDivider;
reg->SSGEN_SETUP = config->ssSetup;
reg->SSGEN_HOLD = config->ssHold;
reg->SSGEN_DISABLE = config->ssDisable;
}
static inline void spi_init(volatile qspi_t* spi){
@ -46,37 +46,45 @@ static inline void spi_init(volatile qspi_t* spi){
spi_configure(spi, &spiCfg);
}
static inline uint32_t spi_cmd_avail(volatile qspi_t* qspi){
return qspi->STATUS & 0xFFFF;
static inline uint32_t spi_cmd_avail(volatile qspi_t* reg){
return reg->STATUS & 0xFFFF;
}
static inline uint32_t spi_rsp_occupied(volatile qspi_t* qspi){
return qspi->STATUS >> 16;
static inline uint32_t spi_rsp_occupied(volatile qspi_t* reg){
return reg->STATUS >> 16;
}
static inline void spi_write(volatile qspi_t* qspi, uint8_t data){
while(spi_cmd_avail(qspi) == 0);
qspi->DATA = data | SPI_CMD_WRITE;
static inline void spi_write(volatile qspi_t* reg, uint8_t data){
while(spi_cmd_avail(reg) == 0);
reg->DATA = data | SPI_CMD_WRITE;
}
static inline uint8_t spi_read(volatile qspi_t* qspi){
while(spi_cmd_avail(qspi) == 0);
qspi->DATA = SPI_CMD_READ;
while(spi_rsp_occupied(qspi) == 0);
while((qspi->DATA & 0x80000000)==0);
return qspi->DATA;
static inline uint8_t spi_write_read(volatile qspi_t* reg, uint8_t data){
while(spi_cmd_avail(reg) == 0);
reg->DATA = data | SPI_CMD_READ | SPI_CMD_WRITE;
while(spi_rsp_occupied(reg) == 0);
return reg->DATA;
}
static inline void spi_select(volatile qspi_t* qspi, uint32_t slaveId){
while(spi_cmd_avail(qspi) == 0);
qspi->DATA = slaveId | 0x80 | SPI_CMD_SS;
static inline uint8_t spi_read(volatile qspi_t* reg){
while(spi_cmd_avail(reg) == 0);
reg->DATA = SPI_CMD_READ;
while(spi_rsp_occupied(reg) == 0);
while((reg->DATA & 0x80000000)==0);
return reg->DATA;
}
static inline void spi_deselect(volatile qspi_t* qspi, uint32_t slaveId){
while(spi_cmd_avail(qspi) == 0);
qspi->DATA = slaveId | SPI_CMD_SS;
static inline void spi_select(volatile qspi_t* reg, uint32_t slaveId){
while(spi_cmd_avail(reg) == 0);
reg->DATA = slaveId | 0x80 | SPI_CMD_SS;
}
static inline void spi_wait_tx_idle(volatile qspi_t* qspi){
while(spi_cmd_avail(qspi) < 0x20);
static inline void spi_deselect(volatile qspi_t* reg, uint32_t slaveId){
while(spi_cmd_avail(reg) == 0);
reg->DATA = slaveId | SPI_CMD_SS;
}
#endif /* _DEVICES_QSPI_H */
static inline void spi_wait_tx_idle(volatile qspi_t* reg){
while(spi_cmd_avail(reg) < 0x20);
}
#endif /* _BSP_QSPI_H */

20
include/ehrenberg/devices/timer.h
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@ -1,19 +1,19 @@
#ifndef _DEVICES_TIMER_H
#define _DEVICES_TIMER_H
#ifndef _BSP_TIMER_H
#define _BSP_TIMER_H
#include "gen/Apb3Timer.h"
#include <stdint.h>
#include "gen/timercounter.h"
inline void prescaler_init(timercounter_t* reg, uint16_t value){
set_timercounter_prescaler(reg, value);
inline void prescaler_init(apb3timer_t *reg, uint16_t value) {
set_timer_prescaler(reg, value);
}
inline void timer_t0__init(timercounter_t *reg){
set_timercounter_t0_overflow(reg, 0xffffffff);
inline void timer_t0__init(apb3timer_t *reg) {
set_timer_t0_overflow(reg, 0xffffffff);
}
inline void timer_t1__init(timercounter_t *reg){
set_timercounter_t1_overflow(reg, 0xffffffff);
inline void timer_t1__init(apb3timer_t *reg) {
set_timer_t1_overflow(reg, 0xffffffff);
}
#endif /* _DEVICES_TIMER_H */
#endif /* _BSP_TIMER_H */

26
include/ehrenberg/devices/uart.h
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@ -1,30 +1,28 @@
#ifndef _DEVICES_UART_H
#define _DEVICES_UART_H
#ifndef _BSP_UART_H
#define _BSP_UART_H
#include <stdint.h>
#include "gen/uart.h"
#include "gen/Apb3Uart.h"
static inline uint32_t uart_get_tx_free(volatile uart_t* reg){
return get_uart_rx_tx_reg_tx_free(reg);
#define uart_t apb3uart_t
static inline uint32_t uart_get_tx_free(volatile uart_t *reg){
return (reg->STATUS_REG >> 16) & 0xFF;
}
static inline uint32_t uart_get_tx_empty(volatile uart_t* reg){
return get_uart_rx_tx_reg_tx_empty(reg);
static inline uint32_t uart_get_rx_avail(volatile uart_t *reg){
return reg->STATUS_REG >> 24;
}
static inline uint32_t uart_get_rx_avail(volatile uart_t* reg){
return get_uart_rx_tx_reg_rx_avail(reg);
}
static inline void uart_write(volatile uart_t* reg, uint8_t data){
static inline void uart_write(volatile uart_t *reg, uint8_t data){
while(get_uart_rx_tx_reg_tx_free(reg) == 0);
set_uart_rx_tx_reg_data(reg, data);
}
static inline inline uint8_t uart_read(volatile uart_t* reg){
static inline inline uint8_t uart_read(volatile uart_t *reg){
uint32_t res = get_uart_rx_tx_reg_data(reg);
while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
return res;
}
#endif /* _DEVICES_UART_H */
#endif /* _BSP_UART_H */

77
libwrap/CMakeLists.txt
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@ -1,77 +0,0 @@
#cmake_minimum_required(VERSION 3.12)
project(libwrap)
message(STATUS " here 2 in libwrap")
set(LIBRARY_NAME libwrap)
set(STATIC_LIBRARY_FLAGS "rcs")
# Create object library for libwrap
set(LIB_SOURCES
sys/_exit.c
sys/close.c
sys/execve.c
sys/fork.c
sys/fstat.c
sys/getpid.c
sys/isatty.c
sys/kill.c
sys/link.c
sys/lseek.c
sys/open.c
sys/openat.c
sys/printf.c
sys/puts.c
sys/read.c
sys/sbrk.c
sys/stat.c
sys/times.c
sys/unlink.c
sys/wait.c
# sys/write.c
# Standard library
stdlib/malloc.c
# Miscellaneous
misc/write_hex.c
)
if(SEMIHOSTING)
list(APPEND LIB_SOURCES
semihosting/semihosting.c
semihosting/trap.c )
endif()
#add_library(${LIBRARY_NAME} OBJECT ${LIB_SOURCES})
add_library(${LIBRARY_NAME} STATIC ${LIB_SOURCES})
set_target_properties(${LIBRARY_NAME} PROPERTIES ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bare-metal-bsp/${PROJECT_NAME})
message(STATUS " CMAKE_BINARY_DIR: ${CMAKE_BINARY_DIR} ${CMAKE_LIBRARY_OUTPUT_DIRECTORY}")
# Retrieve the output directory for the library
get_target_property(LIBRARY_PATH ${LIBRARY_NAME} ARCHIVE_OUTPUT_DIRECTORY)
# Print the path to the console (for debugging purposes)
message(STATUS "The library output path is: ${LIBRARY_PATH}")
# Include directories
target_include_directories(${LIBRARY_NAME} PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}
${BSP_BASE}/include
include/
${BSP_BASE}/env
${BSP_BASE}/env/${BOARD}
${BSP_BASE}/drivers
)
#link global_compile_options to this libraries
#target_link_libraries(${PROJECT_NAME} PRIVATE global_compile_options)
# Compile definitions
#target_compile_definitions(libwrap_objects PRIVATE
# BOARD_${BOARD}
#)
# Export objects to parent scope
#set(LIBWRAP_OBJECTS $<TARGET_OBJECTS:${PROJECT_NAME}> PARENT_SCOPE)

1
libwrap/libwrap.mk
View File

@ -9,6 +9,7 @@ LIBWRAP_SRCS := \
sys/open.c \
sys/lseek.c \
sys/read.c \
sys/write.c \
sys/fstat.c \
sys/stat.c \
sys/close.c \

195
libwrap/semihosting/semihosting.c
View File

@ -1,195 +0,0 @@
#include <stdarg.h>
#include <stddef.h>
#include <stdint.h>
#include <string.h>
#include <sys/types.h>
#include "semihosting.h"
#define SEMIHOSTING_SYS_OPEN 0x01
#define SEMIHOSTING_SYS_CLOSE 0x02
#define SEMIHOSTING_SYS_WRITEC 0x03
#define SEMIHOSTING_SYS_WRITE0 0x04
#define SEMIHOSTING_SYS_WRITE 0x05
#define SEMIHOSTING_SYS_READ 0x06
#define SEMIHOSTING_SYS_READC 0x07
#define SEMIHOSTING_SYS_ISERROR 0x08
#define SEMIHOSTING_SYS_ISTTY 0x09
#define SEMIHOSTING_SYS_SEEK 0x0A
#define SEMIHOSTING_SYS_FLEN 0x0C
#define SEMIHOSTING_SYS_TMPNAM 0x0D
#define SEMIHOSTING_SYS_REMOVE 0x0E
#define SEMIHOSTING_SYS_RENAME 0x0F
#define SEMIHOSTING_SYS_CLOCK 0x10
#define SEMIHOSTING_SYS_TIME 0x11
#define SEMIHOSTING_SYS_SYSTEM 0x12
#define SEMIHOSTING_SYS_ERRNO 0x13
#define SEMIHOSTING_SYS_GET_CMDLINE 0x15
#define SEMIHOSTING_SYS_HEAPINFO 0x16
#define SEMIHOSTING_EnterSVC 0x17
#define SEMIHOSTING_SYS_EXIT 0x18
#define SEMIHOSTING_SYS_EXIT_EXTENDED 0x20
#define SEMIHOSTING_SYS_ELAPSED 0x30
#define SEMIHOSTING_SYS_TICKFREQ 0x31
#define RISCV_SEMIHOSTING_CALL_NUMBER 7
typedef struct {
char *str;
int mode;
size_t length;
} OpenVector;
typedef struct {
char *old;
int old_len;
char *new;
int new_len;
} RenameVector;
typedef struct {
char *path;
size_t len;
} RemoveVector;
typedef struct {
int fd;
off_t pos;
} SeekVector;
static inline int __attribute__((always_inline))
call_host(int reason, void *arg) {
#if 1
// This must always be set back to 0 to cover the case where a host wasn't
// initially present, but only connected while the program was already up and
// running. In that case, trap() suddenly won't be called anymore, so we have
// to clear this variable *before* EBREAK is called.
sh_missing_host = 0;
register int value asm("a0") = reason;
register void *ptr asm("a1") = arg;
asm volatile(
// Workaround for RISC-V lack of multiple EBREAKs.
" .option push \n"
" .option norvc \n"
// Force 16-byte alignment to make sure that the 3 instruction fall
// within the same virtual page. If you the instruction straddle a page
// boundary the debugger fetching the instructions could lead to a page
// fault. Note: align 4 means, align by 2 to the power of 4!
" .align 4 \n"
" slli x0, x0, 0x1f \n"
" ebreak \n"
" srai x0, x0, 0x07 \n"
" .option pop \n"
: "=r"(value) /* Outputs */
: "0"(value),
"r"(ptr), [swi] "i"(RISCV_SEMIHOSTING_CALL_NUMBER) /* Inputs */
: "memory" /* Clobbers */
);
return value;
#else
return 0;
#endif
}
int sh_errno(void) { return call_host(SEMIHOSTING_SYS_ERRNO, (void *)NULL); }
int sh_time(void) { return call_host(SEMIHOSTING_SYS_TIME, (void *)NULL); }
int sh_remove(char *path) {
size_t len = strlen(path);
RemoveVector vec = {path, len};
return call_host(SEMIHOSTING_SYS_REMOVE, &vec);
}
void sh_seek(int file_handle, off_t pos) {
SeekVector vec = {file_handle, pos};
call_host(SEMIHOSTING_SYS_SEEK, &vec);
return;
}
void sh_write(char *str, int file_handle) {
size_t length = strlen(str);
OpenVector vec = {str, file_handle, length};
call_host(SEMIHOSTING_SYS_WRITE, &vec);
return;
}
int sh_close(int file_handle) {
return call_host(SEMIHOSTING_SYS_CLOSE, file_handle);
}
void sh_exit(void) {
call_host(SEMIHOSTING_SYS_EXIT, (void *)NULL);
return;
}
void sh_exit_extended(void) {
call_host(SEMIHOSTING_SYS_EXIT_EXTENDED, (void *)NULL);
return;
}
int sh_flen(int file_handle) {
return call_host(SEMIHOSTING_SYS_FLEN, file_handle);
}
int sh_iserror(int num) { return call_host(SEMIHOSTING_SYS_ISERROR, num); }
int sh_istty(int file_handle) {
return call_host(SEMIHOSTING_SYS_ISTTY, file_handle);
}
/*
int sh_remove(char* path) {
size_t len = strlen(path);
RemoveVector vec = {path, len};
return call_host(SEMIHOSTING_SYS_REMOVE, &vec);
}*/
void sh_rename(char *old, char *new) {
int old_len = strlen(old);
int new_len = strlen(new);
RenameVector vec = {old, old_len, new, new_len};
call_host(SEMIHOSTING_SYS_RENAME, &vec);
return;
}
void sh_write0(const char *buf) {
// Print zero-terminated string
call_host(SEMIHOSTING_SYS_WRITE0, (void *)buf);
}
void sh_writec(char c) {
// Print single character
call_host(SEMIHOSTING_SYS_WRITEC, (void *)&c);
}
char sh_readc(void) {
// Read character from keyboard. (Blocking operation!)
char c = call_host(SEMIHOSTING_SYS_READC, (void *)NULL);
return c;
}
int sh_open(char *str, int mode) {
// mode = 0;
// int length = 44;
size_t length = strlen(str);
OpenVector vec = {str, mode, length};
return call_host(SEMIHOSTING_SYS_OPEN, &vec);
}
int sh_read(char *buf, int file_handle, size_t length) {
OpenVector vec = {buf, file_handle, length};
int i = call_host(SEMIHOSTING_SYS_READ, &vec);
return i;
}
int sh_clock(void) {
int clock = call_host(SEMIHOSTING_SYS_CLOCK, (void *)NULL);
return clock;
}
/*
void sh_write(char* str, int file_handle) {
return;
}*/

31
libwrap/semihosting/semihosting.h
View File

@ -1,31 +0,0 @@
#ifndef SEMIHOSTING_H
#define SEMIHOSTING_H
#include <sys/types.h>
#include <unistd.h>
// int32_t trace_write(const char* buf, uint32_t nbyte);
void sh_seek(int, off_t);
void sh_write0(const char *buf);
void sh_writec(char c);
char sh_readc(void);
int sh_clock(void);
int sh_read(char *, int, size_t);
void sh_write(char *, int);
int sh_open(char *, int);
void sh_rename(char *, char *);
int sh_remove(char *);
int sh_istty(int);
int sh_iserror(int);
int sh_flen(int);
void sh_exit(void);
void sh_exit_extended(void);
int sh_close(int);
int sh_time(void);
int sh_errno(void);
int getchar(void);
extern int sh_missing_host;
#endif

60
libwrap/semihosting/trap.c
View File

@ -1,60 +0,0 @@
#include <math.h>
#include <stdint.h>
#include <stdlib.h>
#include "encoding.h"
#if defined(SEMIHOSTING)
#define EBREAK_OPCODE 0x00100073
#define EBREAK_MCAUSE 0x00000003
#define SLLI_X0_X0_0X1F_OPCODE 0x01f01013
#define SRAI_X0_X0_0X07_OPCODE 0x40705013
int sh_missing_host = 0;
void trap() { // ToDo: Check why macro CSR_MEPC and others are not
// resolved
uint32_t mepc = read_csr(0x341); // Address of trap
uint32_t mtval = read_csr(0x343); // Instruction value of trap
uint32_t mcause = read_csr(0x342); // Reason for the trap
if (mcause == EBREAK_MCAUSE && mtval == EBREAK_OPCODE) {
// This trap was caused by an EBREAK...
int aligned = ((mepc - 4) & 0x0f) == 0;
if (aligned && *(uint32_t *)mepc == EBREAK_OPCODE &&
*(uint32_t *)(mepc - 4) == SLLI_X0_X0_0X1F_OPCODE &&
*(uint32_t *)(mepc + 4) == SRAI_X0_X0_0X07_OPCODE) {
// The EBREAK was part of the semihosting call. (See semihosting.c)
//
// If a debugger were connected, this would have resulted in a CPU halt,
// and the debugger would have serviced the the semihosting call.
//
// However, the semihosting function was called without a debugger being
// attached. The best course of action is to simply return from the trap
// and let the semihosting function continue after the call to EBREAK to
// prevent the CPU from hanging in the trap handler.
write_csr(mepc, mepc + 4);
// Set a global variable to tell the semihosting code the the semihosting
// call
// didn't execute on the host.
sh_missing_host = 1;
return;
}
// EBREAK was not part of a semihosting call. This should not have happened.
// Hang forever.
while (1)
;
}
// Trap was issued for another reason than an EBREAK.
// Replace the code below with whatever trap handler you'd normally use. (e.g.
// interrupt processing.)
while (1)
;
}
#endif

21
libwrap/sys/_exit.c
View File

@ -1,11 +1,8 @@
/* See LICENSE of license details. */
#include <unistd.h>
#include "platform.h"
#include "weak_under_alias.h"
#include <unistd.h>
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
#if defined(BOARD_hifive1)
static volatile uint32_t tohost;
@ -17,21 +14,17 @@ extern volatile uint32_t fromhost;
void write_hex(int fd, uint32_t hex);
void __wrap_exit(int code) {
/*#if defined(SEMIHOSTING)
sh_exit();
return;
#endif*/
// volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
void __wrap_exit(int code)
{
//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
const char message[] = "\nProgam has exited with code:";
//*leds = (~(code));
//*leds = (~(code));
write(STDERR_FILENO, message, sizeof(message) - 1);
write_hex(STDERR_FILENO, code);
write(STDERR_FILENO, "\n", 1);
tohost = code + 1;
tohost = code+1;
write(STDERR_FILENO, "\x04", 1);
for (;;)
;
for (;;);
}
weak_under_alias(exit);

13
libwrap/sys/close.c
View File

@ -1,18 +1,13 @@
/* See LICENSE of license details. */
#include <errno.h>
#include "stub.h"
#include "weak_under_alias.h"
#include <errno.h>
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
int __wrap_close(int fd) {
#if defined(SEMIHOTING)
int i = sh_close(fd);
return i;
#endif
int __wrap_close(int fd)
{
return _stub(EBADF);
}
weak_under_alias(close);

12
libwrap/sys/isatty.c
View File

@ -1,16 +1,10 @@
/* See LICENSE of license details. */
#include "weak_under_alias.h"
#include <unistd.h>
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
#include "weak_under_alias.h"
int __wrap_isatty(int fd) {
#if defined(SEMIHOSTING)
int i = sh_istty(fd);
return i;
#endif
int __wrap_isatty(int fd)
{
if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
return 1;

19
libwrap/sys/lseek.c
View File

@ -1,21 +1,13 @@
/* See LICENSE of license details. */
#include <errno.h>
#include <unistd.h>
#include <sys/types.h>
#include "stub.h"
#include "weak_under_alias.h"
#include <errno.h>
#include <sys/types.h>
#include <unistd.h>
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
off_t __wrap_lseek(int fd, off_t ptr, int dir) {
#if defined(SEMIHOSTING)
if (sh_istty(fd))
return 0;
sh_seek(fd, ptr);
return ptr;
#endif
off_t __wrap_lseek(int fd, off_t ptr, int dir)
{
if (isatty(fd))
return 0;
@ -23,3 +15,4 @@ off_t __wrap_lseek(int fd, off_t ptr, int dir) {
}
weak_under_alias(lseek);

12
libwrap/sys/open.c
View File

@ -1,17 +1,11 @@
/* See LICENSE of license details. */
#include <errno.h>
#include "stub.h"
#include "weak_under_alias.h"
#include <errno.h>
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
int __wrap_open(const char *name, int flags, int mode) {
#if defined(SEMIHOSTING)
int fd = sh_open(name, mode);
return fd;
#endif
int __wrap_open(const char* name, int flags, int mode)
{
return _stub(ENOENT);
}
weak_under_alias(open);

108
libwrap/sys/printf.c
View File

@ -3,49 +3,59 @@
#include <stdarg.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <unistd.h>
#undef putchar
int putchar(int ch) { return write(STDOUT_FILENO, &ch, 1) == 1 ? ch : -1; }
int putchar(int ch)
{
return write(STDOUT_FILENO, &ch, 1) == 1 ? ch : -1;
}
size_t strnlen(const char *str, size_t n) {
size_t strnlen (const char *str, size_t n)
{
const char *start = str;
while (n-- > 0 && *str)
str++;
while (n-- > 0 && *str) str++;
return str - start;
}
static void fprintf_putch(int ch, void **data) { putchar(ch); }
static void sprintf_putch(int ch, void **data) {
char **pstr = (char **)data;
static void fprintf_putch(int ch, void** data)
{
putchar(ch);
}
static void sprintf_putch(int ch, void** data)
{
char** pstr = (char**)data;
**pstr = ch;
(*pstr)++;
}
static unsigned long getuint(va_list *ap, int lflag) {
static unsigned long getuint(va_list *ap, int lflag)
{
if (lflag)
return va_arg(*ap, unsigned long);
else
return va_arg(*ap, unsigned int);
}
static long getint(va_list *ap, int lflag) {
static long getint(va_list *ap, int lflag)
{
if (lflag)
return va_arg(*ap, long);
else
return va_arg(*ap, int);
}
static inline void printnum(void (*putch)(int, void **), void **putdat,
unsigned long num, unsigned base, int width,
int padc) {
unsigned digs[sizeof(num) * 8];
static inline void printnum(void (*putch)(int, void**), void **putdat,
unsigned long num, unsigned base, int width, int padc)
{
unsigned digs[sizeof(num)*8];
int pos = 0;
while (1) {
while (1)
{
digs[pos++] = num % base;
if (num < base)
break;
@ -59,8 +69,9 @@ static inline void printnum(void (*putch)(int, void **), void **putdat,
putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat);
}
static inline void print_double(void (*putch)(int, void **), void **putdat,
double num, int width, int prec) {
static inline void print_double(void (*putch)(int, void**), void **putdat,
double num, int width, int prec)
{
union {
double d;
uint64_t u;
@ -76,30 +87,30 @@ static inline void print_double(void (*putch)(int, void **), void **putdat,
u.d *= 10;
char buf[32], *pbuf = buf;
printnum(sprintf_putch, (void **)&pbuf, (unsigned long)u.d, 10, 0, 0);
printnum(sprintf_putch, (void**)&pbuf, (unsigned long)u.d, 10, 0, 0);
if (prec > 0) {
for (int i = 0; i < prec; i++) {
pbuf[-i] = pbuf[-i - 1];
pbuf[-i] = pbuf[-i-1];
}
pbuf[-prec] = '.';
pbuf++;
}
for (char *p = buf; p < pbuf; p++)
for (char* p = buf; p < pbuf; p++)
putch(*p, putdat);
}
static void vprintfmt(void (*putch)(int, void **), void **putdat,
const char *fmt, va_list ap) {
register const char *p;
const char *last_fmt;
static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap)
{
register const char* p;
const char* last_fmt;
register int ch;
unsigned long num;
int base, lflag, width, precision;
char padc;
while (1) {
while ((ch = *(const char *)fmt) != '%') {
while ((ch = *(const char *) fmt) != '%') {
if (ch == '\0')
return;
fmt++;
@ -114,13 +125,13 @@ static void vprintfmt(void (*putch)(int, void **), void **putdat,
precision = -1;
lflag = 0;
reswitch:
switch (ch = *(const char *)fmt++) {
switch (ch = *(const char *) fmt++) {
// flag to pad on the right
case '-':
padc = '-';
goto reswitch;
// flag to pad with 0's instead of spaces
case '0':
padc = '0';
@ -136,7 +147,7 @@ static void vprintfmt(void (*putch)(int, void **), void **putdat,
case '7':
case '8':
case '9':
for (precision = 0;; ++fmt) {
for (precision = 0; ; ++fmt) {
precision = precision * 10 + ch - '0';
ch = *fmt;
if (ch < '0' || ch > '9')
@ -161,62 +172,61 @@ static void vprintfmt(void (*putch)(int, void **), void **putdat,
width = precision, precision = -1;
goto reswitch;
case 'l': // long flag
case 'l': // long flag
if (lflag)
goto bad;
goto reswitch;
case 'c': // character
case 'c': // character
putch(va_arg(ap, int), putdat);
break;
case 'f': // double
case 'f': // double
print_double(putch, putdat, va_arg(ap, double), width, precision);
break;
case 's': // string
case 's': // string
if ((p = va_arg(ap, char *)) == NULL)
p = "(null)";
if (width > 0 && padc != '-')
for (width -= strnlen(p, precision); width > 0; width--)
putch(padc, putdat);
for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0);
width--) {
for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) {
putch(ch, putdat);
p++;
}
for (; width > 0; width--)
putch(' ', putdat);
break;
case 'd': // (signed) decimal
case 'd': // (signed) decimal
num = getint(&ap, lflag);
if ((long)num < 0) {
if ((long) num < 0) {
putch('-', putdat);
num = -(long)num;
num = -(long) num;
}
base = 10;
goto signed_number;
case 'u': // unsigned decimal
case 'u': // unsigned decimal
base = 10;
goto unsigned_number;
case 'o': // (unsigned) octal
// should do something with padding so it's always 3 octits
base = 8;
goto unsigned_number;
case 'p': // pointer
case 'p':// pointer
lflag = 1;
putch('0', putdat);
putch('x', putdat);
/* fall through to 'x' */
__attribute__((fallthrough));
case 'x': // (unsigned) hexadecimal
case 'x': // (unsigned) hexadecimal
base = 16;
unsigned_number:
unsigned_number:
num = getuint(&ap, lflag);
signed_number:
signed_number:
printnum(putch, putdat, num, base, width, padc);
break;
case '%': // escaped '%' character
case '%': // escaped '%' character
putch(ch, putdat);
break;
default: // unrecognized escape sequence - just print it literally
default: // unrecognized escape sequence - just print it literally
bad:
putch('%', putdat);
fmt = last_fmt;
@ -225,7 +235,8 @@ static void vprintfmt(void (*putch)(int, void **), void **putdat,
}
}
int __wrap_printf(const char *fmt, ...) {
int __wrap_printf(const char* fmt, ...)
{
va_list ap;
va_start(ap, fmt);
@ -235,12 +246,13 @@ int __wrap_printf(const char *fmt, ...) {
return 0; // incorrect return value, but who cares, anyway?
}
int __wrap_sprintf(char *str, const char *fmt, ...) {
int __wrap_sprintf(char* str, const char* fmt, ...)
{
va_list ap;
char *str0 = str;
char* str0 = str;
va_start(ap, fmt);
vprintfmt(sprintf_putch, (void **)&str, fmt, ap);
vprintfmt(sprintf_putch, (void**)&str, fmt, ap);
*str = 0;
va_end(ap);

7
libwrap/sys/puts.c
View File

@ -8,15 +8,8 @@
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
int __wrap_puts(const char *s) {
#if defined(SEMIHOSTING)
sh_write0(s);
return 0;
#endif
while (*s != '\0') {
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
while (get_uart_rx_tx_reg_tx_free(uart) == 0)

14
libwrap/sys/read.c
View File

@ -1,23 +1,15 @@
/* See LICENSE of license details. */
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
#include <errno.h>
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
ssize_t __wrap_read(int fd, void *ptr, size_t len) {
uint8_t *current = (uint8_t *)ptr;
#if defined(SEMIHOSTING)
int i = sh_read(current, fd, len);
return i;
#endif
#if defined(BOARD_hifive1)
volatile uint32_t *uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO);
volatile uint8_t *uart_rx_cnt =

11
libwrap/sys/unlink.c
View File

@ -1,16 +1,11 @@
/* See LICENSE of license details. */
#include <errno.h>
#include "stub.h"
#include "weak_under_alias.h"
#include <errno.h>
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
int __wrap_unlink(const char *name) {
#if defined(SEMIHOSTING)
return sh_remove(name);
#endif
int __wrap_unlink(const char* name)
{
return _stub(ENOENT);
}
weak_under_alias(unlink);

20
libwrap/sys/write.c
View File

@ -8,24 +8,8 @@
#include "platform.h"
#include "stub.h"
#include "weak_under_alias.h"
#if defined(SEMIHOSTING)
#include "semihosting.h"
#endif
ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
const uint8_t *current = (const uint8_t *)ptr;
#if defined(SEMIHOSTING)
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
sh_writec(current[jj]);
}
return len;
} else {
sh_write(current, fd);
return len;
}
// return len;
#endif
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
@ -38,9 +22,7 @@ ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
uart_write(uart, '\r');
}
#elif defined(BOARD_iss)
*((uint32_t *)0xFFFF0000) = current[jj];
#elif defined(BOARD_TGCP)
// TODO: implement
*((uint32_t*) 0xFFFF0000) = current[jj];
#else
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000)
;