Revert remove of fmcdiv in sysctrl

env/common-clang.mk

@@ -63,10 +63,6 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)
 
 .PHONY: clean
 clean:
-	rm -f $(TARGET) $(LINK_OBJS)
+	rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf *.o
-
-.PHONY: clean-all
-clean-all:
-	rm -f $(CLEAN_OBJS) $(LIBWRAP)
 
 endif

env/common-gcc.mk

@@ -79,6 +79,6 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)
 
 .PHONY: clean
 clean:
-	rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf
+	rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf *.o
 
 endif

env/ehrenberg/link.lds

@@ -4,10 +4,10 @@ ENTRY( _start )
 
 MEMORY
 {
-  rom   (rxai!w) : ORIGIN = 0xFFFFE000, LENGTH = 4k
+  rom   (rxai!w) : ORIGIN = 0xFFFFE000, LENGTH = 2k
-  flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 4M
+  flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 16M
-  ram (wxa!ri) :   ORIGIN = 0x80000000, LENGTH = 32K
+  ram   (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128K
-  dram (wxa!ri) :  ORIGIN = 0x00000000, LENGTH = 256M
+  dram  (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 2048M
 }
 
 PHDRS
@@ -107,6 +107,11 @@ SECTIONS
     KEEP (*(.dtors))
   } >flash AT>flash :flash
 
+  .dummy          :
+  {
+	*(.comment.*)
+
+  }
   .lalign         :
   {
     . = ALIGN(4);
@@ -126,6 +131,13 @@ SECTIONS
     *(.gnu.linkonce.d.*)
   } >ram AT>flash :ram_init
 
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>flash :ram_init
+
   .srodata        :
   {
     *(.srodata.cst16)
@@ -135,13 +147,6 @@ SECTIONS
     *(.srodata .srodata.*)
   } >ram AT>flash :ram_init
 
-  .sdata          :
-  {
-    __SDATA_BEGIN__ = .;
-    *(.sdata .sdata.*)
-    *(.gnu.linkonce.s.*)
-  } >ram AT>flash :ram_init
-
   . = ALIGN(4);
   PROVIDE( _edata = . );
   PROVIDE( edata = . );

env/ehrenberg/platform.h

@@ -16,6 +16,7 @@
 #include "ehrenberg/devices/aclint.h"
 #include "ehrenberg/devices/camera.h"
 #include "ehrenberg/devices/dma.h"
+#include "ehrenberg/devices/gen/sysctrl.h"
 #include "ehrenberg/devices/gpio.h"
 #include "ehrenberg/devices/i2s.h"
 #include "ehrenberg/devices/msg_if.h"
@@ -31,15 +32,22 @@
 #define uart PERIPH(uart_t, APB_BASE + 0x01000)
 #define timer PERIPH(timercounter_t, APB_BASE + 0x20000)
 #define aclint PERIPH(aclint_t, APB_BASE + 0x30000)
-// #define irq         PERIPH(irq_t,          APB_BASE+0x40000)
+#define sysctrl PERIPH(sysctrl_t, APB_BASE + 0x40000)
 #define qspi PERIPH(qspi_t, APB_BASE + 0x50000)
 #define i2s PERIPH(i2s_t, APB_BASE + 0x90000)
 #define camera PERIPH(camera_t, APB_BASE + 0xA0000)
 #define dma PERIPH(dma_t, APB_BASE + 0xB0000)
-#define msgif PERIPH(msgif_t, APB_BASE + 0xC0000)
+#define msgif PERIPH(mkcontrolclusterstreamcontroller_t, APB_BASE + 0xC0000)
 
-#define XIP_START_LOC 0xE0040000
+#include "ehrenberg/devices/fki_cluster_info.h"
-#define RAM_START_LOC 0x80000000
+#include "ehrenberg/devices/flexki_messages.h"
+
+#ifndef XIP_START_LOC
+#define XIP_START_LOC 0xE0000000
+#endif
+#ifndef RAM_START_LOC
+#define RAM_START_LOC 0xC0000000
+#endif
 
 // Misc
 

env/ehrenberg/ram.lds

@@ -4,8 +4,8 @@ ENTRY( _start )
 
 MEMORY
 {
-  rom (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64k
+  rom (rxai!w) : ORIGIN = 0xC0000000, LENGTH = 64k
-  ram (wxa!ri) : ORIGIN = 0x80010000, LENGTH = 64k
+  ram (wxa!ri) : ORIGIN = 0xC0010000, LENGTH = 64k
 }
 
 PHDRS
@@ -118,10 +118,18 @@ SECTIONS
 
   .data          :
   {
+    __DATA_BEGIN__ = .;
     *(.data .data.*)
     *(.gnu.linkonce.d.*)
   } >ram AT>rom :ram_init
 
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
+
   .srodata        :
   {
     PROVIDE( __global_pointer$ = . + 0x800 );
@@ -132,12 +140,6 @@ SECTIONS
     *(.srodata .srodata.*)
   } >ram AT>rom :ram_init
 
-  .sdata          :
-  {
-    *(.sdata .sdata.*)
-    *(.gnu.linkonce.s.*)
-  } >ram AT>rom :ram_init
-
   . = ALIGN(4);
   PROVIDE( _edata = . );
   PROVIDE( edata = . );
@@ -155,6 +157,7 @@ SECTIONS
   } >ram AT>ram :ram
 
   . = ALIGN(8);
+  __BSS_END__ = .;
   PROVIDE( _end = . );
   PROVIDE( end = . );
 
@@ -164,4 +167,7 @@ SECTIONS
     . = __stack_size;
     PROVIDE( _sp = . );
   } >ram AT>ram :ram
+
+  PROVIDE( tohost = 0xfffffff0 );
+  PROVIDE( fromhost = 0xfffffff8 );
 }

env/ehrenberg/rom.lds

@@ -4,8 +4,8 @@ ENTRY( _start )
 
 MEMORY
 {
-  rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 4k
+  rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 2k
-  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32k
+  ram (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128k
 }
 
 PHDRS
@@ -118,13 +118,20 @@ SECTIONS
 
   .data          :
   {
+    __DATA_BEGIN__ = .;
     *(.data .data.*)
     *(.gnu.linkonce.d.*)
   } >ram AT>rom :ram_init
 
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>rom :ram_init
+
   .srodata        :
   {
-    PROVIDE( __global_pointer$ = . + 0x800 );
     *(.srodata.cst16)
     *(.srodata.cst8)
     *(.srodata.cst4)
@@ -132,12 +139,6 @@ SECTIONS
     *(.srodata .srodata.*)
   } >ram AT>rom :ram_init
 
-  .sdata          :
-  {
-    *(.sdata .sdata.*)
-    *(.gnu.linkonce.s.*)
-  } >ram AT>rom :ram_init
-
   . = ALIGN(4);
   PROVIDE( _edata = . );
   PROVIDE( edata = . );
@@ -155,6 +156,8 @@ SECTIONS
   } >ram AT>ram :ram
 
   . = ALIGN(8);
+  __BSS_END__ = .;
+  __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,  MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
   PROVIDE( _end = . );
   PROVIDE( end = . );
 

env/ehrenberg/spi_flash.lds

@@ -0,0 +1,180 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 16M
+  ram   (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128K
+  dram  (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 2048M
+}
+
+PHDRS
+{
+  flash PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+  dram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init ORIGIN(flash)        :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash :flash
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash :flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash :flash
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >flash AT>flash :flash
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash :flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash :flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash :flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash :flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash :flash
+
+  .dummy          :
+  {
+	*(.comment.*)
+
+  }
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash :flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash :ram_init
+
+  .data          :
+  {
+    __DATA_BEGIN__ = .;
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+  } >ram AT>flash :ram_init
+
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>flash :ram_init
+
+  .srodata        :
+  {
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  __BSS_END__ = .;
+  __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,  MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+
+  PROVIDE( tohost = 0xfffffff0 );
+  PROVIDE( fromhost = 0xfffffff8 );
+}

env/start.S

@@ -8,11 +8,13 @@ _start:
 .option push
 .option norelax
 .option norvc
+//#ifdef WITH_SIGNATURE
 	j 1f
 	.2byte	0x4e4d
 	.2byte	0x5352
 	.4byte  0x669
 1:
+//#endif
     la gp, __global_pointer$
 .option pop
 	la sp, _sp

include/ehrenberg/devices/fki_cluster_info.h

@@ -0,0 +1,409 @@
+#ifndef _FKI_CLUSTER_INFO_H
+#define _FKI_CLUSTER_INFO_H
+
+
+static uint8_t fki_ccc(uint8_t cluster);
+static uint8_t fki_dma(uint8_t cluster);
+static uint8_t fki_axi2stream(uint8_t cluster);
+static uint8_t fki_stream2axi(uint8_t cluster);
+static uint8_t fki_dma_adapter(uint8_t cluster);
+static inline uint32_t fki_addr_ccc_peMapping(uint8_t cluster);
+static inline uint32_t fki_addr_sram1(uint8_t cluster);
+static inline uint32_t fki_addr_sram2(uint8_t cluster);
+static inline uint32_t fki_addr_cntrl_cva5(uint8_t cluster);
+static inline uint32_t fki_addr_cntrl_tgc(uint8_t cluster);
+static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster);
+static inline uint32_t fki_addr_cacheFlushControl(uint8_t cluster);
+static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster);
+static inline uint32_t fki_addr_ccc_idxJobs(uint8_t cluster);
+static inline uint32_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster);
+static inline uint32_t fki_addr_ccc_configMem(uint8_t cluster);
+static inline uint32_t fki_addr_aes_adapter(uint8_t cluster);
+static inline uint32_t fki_addr_ut_adapter(uint8_t cluster);
+static inline uint32_t fki_addr_sram0(uint8_t cluster);
+static inline uint32_t fki_addr_sram3(uint8_t cluster);
+
+#define Compute0 2
+#define Compute0_ccc 2,0
+#define Compute0_stream2axi 2,1
+#define Compute0_axi2stream 2,2
+#define Compute0_dma 2,4
+#define Compute0_dma_adapter 2,5
+#define ADDR_Compute0_ccc_idxJobs 0x80004000
+#define BYTES_Compute0_ccc_idxJobs 4096
+#define HIGH_Compute0_ccc_idxJobs 0x80004fff
+#define ADDR_Compute0_ccc_idxTasks 0x80005000
+#define BYTES_Compute0_ccc_idxTasks 4096
+#define HIGH_Compute0_ccc_idxTasks 0x80005fff
+#define ADDR_Compute0_ccc_configMem 0x80000000
+#define BYTES_Compute0_ccc_configMem 16384
+#define HIGH_Compute0_ccc_configMem 0x80003fff
+#define ADDR_Compute0_ccc_peMapping 0x80006000
+#define BYTES_Compute0_ccc_peMapping 4096
+#define HIGH_Compute0_ccc_peMapping 0x80006fff
+#define ADDR_Compute0_aes_adapter 0x80007000
+#define BYTES_Compute0_aes_adapter 4096
+#define HIGH_Compute0_aes_adapter 0x80007fff
+#define ADDR_Compute0_cntrl_cva5_clusterReg 0x8000a000
+#define BYTES_Compute0_cntrl_cva5_clusterReg 4096
+#define HIGH_Compute0_cntrl_cva5_clusterReg 0x8000afff
+#define ADDR_Compute0_cntrl_cva5 0x80008000
+#define BYTES_Compute0_cntrl_cva5 8192
+#define HIGH_Compute0_cntrl_cva5 0x80009fff
+#define ADDR_Compute0_cntrl_tgc_clusterReg 0x8000d000
+#define BYTES_Compute0_cntrl_tgc_clusterReg 4096
+#define HIGH_Compute0_cntrl_tgc_clusterReg 0x8000dfff
+#define ADDR_Compute0_cntrl_tgc 0x8000b000
+#define BYTES_Compute0_cntrl_tgc 8192
+#define HIGH_Compute0_cntrl_tgc 0x8000cfff
+#define ADDR_Compute0_ut_adapter 0x8000e000
+#define BYTES_Compute0_ut_adapter 4096
+#define HIGH_Compute0_ut_adapter 0x8000efff
+#define ADDR_Compute0_cacheFlushControl 0x8000f000
+#define BYTES_Compute0_cacheFlushControl 4096
+#define HIGH_Compute0_cacheFlushControl 0x8000ffff
+#define ADDR_Compute0_sram0 0x80010000
+#define BYTES_Compute0_sram0 524288
+#define HIGH_Compute0_sram0 0x8008ffff
+#define ADDR_Compute0_sram1 0x80090000
+#define BYTES_Compute0_sram1 262144
+#define HIGH_Compute0_sram1 0x800cffff
+#define ADDR_Compute0_sram2 0x800d0000
+#define BYTES_Compute0_sram2 262144
+#define HIGH_Compute0_sram2 0x8010ffff
+#define ADDR_Compute0_sram3 0x80110000
+#define BYTES_Compute0_sram3 262144
+#define HIGH_Compute0_sram3 0x8014ffff
+#define Compute1 3
+#define Compute1_ccc 3,0
+#define Compute1_stream2axi 3,1
+#define Compute1_axi2stream 3,2
+#define Compute1_dma 3,4
+#define Compute1_dma_adapter 3,5
+#define ADDR_Compute1_ccc_idxJobs 0x90004000
+#define BYTES_Compute1_ccc_idxJobs 4096
+#define HIGH_Compute1_ccc_idxJobs 0x90004fff
+#define ADDR_Compute1_ccc_idxTasks 0x90005000
+#define BYTES_Compute1_ccc_idxTasks 4096
+#define HIGH_Compute1_ccc_idxTasks 0x90005fff
+#define ADDR_Compute1_ccc_configMem 0x90000000
+#define BYTES_Compute1_ccc_configMem 16384
+#define HIGH_Compute1_ccc_configMem 0x90003fff
+#define ADDR_Compute1_ccc_peMapping 0x90006000
+#define BYTES_Compute1_ccc_peMapping 4096
+#define HIGH_Compute1_ccc_peMapping 0x90006fff
+#define ADDR_Compute1_aes_adapter 0x90007000
+#define BYTES_Compute1_aes_adapter 4096
+#define HIGH_Compute1_aes_adapter 0x90007fff
+#define ADDR_Compute1_cntrl_cva5_clusterReg 0x8000a000
+#define BYTES_Compute1_cntrl_cva5_clusterReg 4096
+#define HIGH_Compute1_cntrl_cva5_clusterReg 0x8000afff
+#define ADDR_Compute1_cntrl_cva5 0x90008000
+#define BYTES_Compute1_cntrl_cva5 12288
+#define HIGH_Compute1_cntrl_cva5 0x9000afff
+#define ADDR_Compute1_cntrl_tgc_clusterReg 0x8000d000
+#define BYTES_Compute1_cntrl_tgc_clusterReg 4096
+#define HIGH_Compute1_cntrl_tgc_clusterReg 0x8000dfff
+#define ADDR_Compute1_cntrl_tgc 0x9000b000
+#define BYTES_Compute1_cntrl_tgc 12288
+#define HIGH_Compute1_cntrl_tgc 0x9000dfff
+#define ADDR_Compute1_ut_adapter 0x9000e000
+#define BYTES_Compute1_ut_adapter 4096
+#define HIGH_Compute1_ut_adapter 0x9000efff
+#define ADDR_Compute1_cacheFlushControl 0x9000f000
+#define BYTES_Compute1_cacheFlushControl 4096
+#define HIGH_Compute1_cacheFlushControl 0x9000ffff
+#define ADDR_Compute1_sram0 0x90010000
+#define BYTES_Compute1_sram0 524288
+#define HIGH_Compute1_sram0 0x9008ffff
+#define ADDR_Compute1_sram1 0x90090000
+#define BYTES_Compute1_sram1 262144
+#define HIGH_Compute1_sram1 0x900cffff
+#define ADDR_Compute1_sram2 0x900d0000
+#define BYTES_Compute1_sram2 262144
+#define HIGH_Compute1_sram2 0x9010ffff
+#define ADDR_Compute1_sram3 0x90110000
+#define BYTES_Compute1_sram3 262144
+#define HIGH_Compute1_sram3 0x9014ffff
+
+static uint8_t fki_ccc(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0;
+		}
+		case 3: {
+			return 0;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_dma(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 4;
+		}
+		case 2: {
+			return 4;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_axi2stream(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 2;
+		}
+		case 2: {
+			return 2;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_stream2axi(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 1;
+		}
+		case 2: {
+			return 1;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static uint8_t fki_dma_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 5;
+		}
+		case 3: {
+			return 5;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_ccc_peMapping(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80006000;
+		}
+		case 3: {
+			return 0x90006000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_sram1(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x90090000;
+		}
+		case 2: {
+			return 0x80090000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_sram2(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x800d0000;
+		}
+		case 3: {
+			return 0x900d0000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_cntrl_cva5(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80008000;
+		}
+		case 3: {
+			return 0x90008000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_cntrl_tgc(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8000b000;
+		}
+		case 3: {
+			return 0x9000b000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80005000;
+		}
+		case 3: {
+			return 0x90005000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_cacheFlushControl(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x9000f000;
+		}
+		case 2: {
+			return 0x8000f000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x8000d000;
+		}
+		case 2: {
+			return 0x8000d000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_ccc_idxJobs(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80004000;
+		}
+		case 3: {
+			return 0x90004000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x8000a000;
+		}
+		case 3: {
+			return 0x8000a000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_ccc_configMem(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x90000000;
+		}
+		case 2: {
+			return 0x80000000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_aes_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80007000;
+		}
+		case 3: {
+			return 0x90007000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_ut_adapter(uint8_t cluster) {
+	switch(cluster) {
+		case 3: {
+			return 0x9000e000;
+		}
+		case 2: {
+			return 0x8000e000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_sram0(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80010000;
+		}
+		case 3: {
+			return 0x90010000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+static inline uint32_t fki_addr_sram3(uint8_t cluster) {
+	switch(cluster) {
+		case 2: {
+			return 0x80110000;
+		}
+		case 3: {
+			return 0x90110000;
+		}
+		default: {
+			return -1;
+		}
+	}
+}
+
+#endif //_FKI_CLUSTER_INFO_H

include/ehrenberg/devices/flexki_messages.h

@@ -0,0 +1,98 @@
+#ifndef _FLEXKI_MESSAGES_H
+#define _FLEXKI_MESSAGES_H
+
+#include "fki_cluster_info.h"
+
+#include <stdbool.h>
+
+static void send_msg(uint32_t cluster, uint32_t component, uint32_t msg_len, uint32_t msg_id, uint32_t* words) {
+    set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(msgif, component);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(msgif, cluster);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(msgif, msg_len);
+	set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(msgif, msg_id);
+    for (uint32_t i = 0; i < msg_len; i = i + 1) {
+        switch (i) {
+            case 0:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(msgif, words[i]);
+                break;
+            case 1:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(msgif, words[i]);
+                break;
+            case 2:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(msgif, words[i]);
+                break;
+            case 3:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(msgif, words[i]);
+                break;
+            case 4:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(msgif, words[i]);
+                break;
+            case 5:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(msgif, words[i]);
+                break;
+            case 6:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(msgif, words[i]);
+                break;
+            case 7:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(msgif, words[i]);
+                break;
+            case 8:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(msgif, words[i]);
+                break;
+            case 9:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(msgif, words[i]);
+                break;
+            case 10:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(msgif, words[i]);
+                break;
+            case 11:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(msgif, words[i]);
+                break;
+            case 12:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(msgif, words[i]);
+                break;
+            case 13:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(msgif, words[i]);
+                break;
+            case 14:
+                set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(msgif, words[i]);
+                break;
+            default:
+                break;
+        }
+    }
+    set_mkcontrolclusterstreamcontroller_REG_SEND(msgif, 1);
+}
+
+static uint32_t check_response(void) {
+    while (true) {
+        if (get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(msgif) != 0) {
+            return get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(msgif);
+        }
+    }
+}
+
+static uint32_t wait_response(uint32_t msg_id) {
+    while (true) {
+        if (get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(msgif) != 0) {
+            if (get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(msgif) == msg_id) {
+                break;
+            }
+        }
+    }
+	uint32_t response_payload = get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(msgif);
+	set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(msgif, 1);
+	return response_payload;
+}
+
+static void fki_dma_transfer(uint32_t cluster, uint32_t msg_id, uint32_t srcAddr, uint32_t destAddr, uint32_t bytes) {
+    uint32_t values[] = {
+        0,
+        srcAddr,
+        destAddr,
+        bytes
+    };
+    send_msg(cluster, fki_dma(cluster), 4, msg_id, values);
+}
+
+#endif /* _FLEXKI_MESSAGES_H */

include/ehrenberg/devices/gen/aclint.h

@@ -1,10 +1,10 @@
 /*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-08-02 08:46:07 UTC 
+* Generated at 2025-07-01 11:20:43 UTC 
-* by peakrdl_mnrs version 1.2.7
+* by peakrdl_mnrs version 1.2.9
 */
 
 #ifndef _BSP_ACLINT_H
@@ -88,4 +88,4 @@ inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value){
     reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
 }
 
-#endif /* _BSP_ACLINT_H */
+#endif /* _BSP_ACLINT_H */

include/ehrenberg/devices/gen/apb3spi.h

@@ -3,7 +3,7 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2025-02-17 15:56:47 UTC 
+* Generated at 2025-07-01 11:20:43 UTC 
 * by peakrdl_mnrs version 1.2.9
 */
 
@@ -106,7 +106,7 @@ typedef struct {
 #define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
 
 #define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
-#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
+#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0xf
 #define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
 
 #define APB3SPI_XIP_ENABLE_OFFS 0
@@ -319,10 +319,10 @@ inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t valu
      reg->SSGEN_ACTIVE_HIGH = value;
 }
 inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg){
-    return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
+    return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0xf;
 }
 inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value){
-    reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
+    reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0xfU << 0)) | (value << 0);
 }
 
 //APB3SPI_XIP_ENABLE

include/ehrenberg/devices/gen/camera.h

@@ -1,10 +1,10 @@
 /*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-11-27 09:36:49 UTC 
+* Generated at 2025-07-01 11:20:43 UTC 
-* by peakrdl_mnrs version 1.2.7
+* by peakrdl_mnrs version 1.2.9
 */
 
 #ifndef _BSP_CAMERA_H
@@ -15,6 +15,7 @@
 typedef struct {
     volatile uint32_t PIXEL;
     volatile uint32_t CONFIG;
+    volatile uint32_t CONFIG2;
     volatile uint32_t DATA_SIZE;
     volatile uint32_t START;
     volatile uint32_t STATUS;
@@ -27,61 +28,69 @@ typedef struct {
 #define CAMERA_PIXEL_MASK 0xffffffff
 #define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
 
-#define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 0
+#define CAMERA_CONFIG_OUTPUT_CURR_OFFS 0
-#define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff
-#define CAMERA_CONFIG_ROWS_IN_RESET(V) ((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS)
-
-#define CAMERA_CONFIG_VRST_PIX_OFFS 8
-#define CAMERA_CONFIG_VRST_PIX_MASK 0x3
-#define CAMERA_CONFIG_VRST_PIX(V) ((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS)
-
-#define CAMERA_CONFIG_RAMP_GAIN_OFFS 10
-#define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3
-#define CAMERA_CONFIG_RAMP_GAIN(V) ((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS)
-
-#define CAMERA_CONFIG_OFFSET_RAMP_OFFS 12
-#define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3
-#define CAMERA_CONFIG_OFFSET_RAMP(V) ((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS)
-
-#define CAMERA_CONFIG_OUTPUT_CURR_OFFS 14
 #define CAMERA_CONFIG_OUTPUT_CURR_MASK 0x3
 #define CAMERA_CONFIG_OUTPUT_CURR(V) ((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS)
 
-#define CAMERA_CONFIG_ROWS_DELAY_OFFS 16
+#define CAMERA_CONFIG_OFFSET_RAMP_OFFS 2
-#define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f
+#define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3
-#define CAMERA_CONFIG_ROWS_DELAY(V) ((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS)
+#define CAMERA_CONFIG_OFFSET_RAMP(V) ((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS)
 
-#define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 21
+#define CAMERA_CONFIG_RAMP_GAIN_OFFS 4
-#define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1
+#define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3
-#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) ((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) << CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS)
+#define CAMERA_CONFIG_RAMP_GAIN(V) ((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS)
 
-#define CAMERA_CONFIG_CDS_GAIN_OFFS 22
+#define CAMERA_CONFIG_VRST_PIX_OFFS 6
-#define CAMERA_CONFIG_CDS_GAIN_MASK 0x1
+#define CAMERA_CONFIG_VRST_PIX_MASK 0x3
-#define CAMERA_CONFIG_CDS_GAIN(V) ((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS)
+#define CAMERA_CONFIG_VRST_PIX(V) ((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS)
 
-#define CAMERA_CONFIG_OUTPUT_MODE_OFFS 23
+#define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 8
-#define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1
+#define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff
-#define CAMERA_CONFIG_OUTPUT_MODE(V) ((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS)
+#define CAMERA_CONFIG_ROWS_IN_RESET(V) ((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS)
 
-#define CAMERA_CONFIG_MCLK_MODE_OFFS 24
+#define CAMERA_CONFIG_HIGH_SPEED_OFFS 16
-#define CAMERA_CONFIG_MCLK_MODE_MASK 0x3
+#define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1
-#define CAMERA_CONFIG_MCLK_MODE(V) ((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS)
+#define CAMERA_CONFIG_HIGH_SPEED(V) ((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS)
 
-#define CAMERA_CONFIG_VREF_OFFS 26
+#define CAMERA_CONFIG_IDLE_MODE_OFFS 17
-#define CAMERA_CONFIG_VREF_MASK 0x3
-#define CAMERA_CONFIG_VREF(V) ((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS)
-
-#define CAMERA_CONFIG_CVC_CURR_OFFS 28
-#define CAMERA_CONFIG_CVC_CURR_MASK 0x3
-#define CAMERA_CONFIG_CVC_CURR(V) ((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS)
-
-#define CAMERA_CONFIG_IDLE_MODE_OFFS 30
 #define CAMERA_CONFIG_IDLE_MODE_MASK 0x1
 #define CAMERA_CONFIG_IDLE_MODE(V) ((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS)
 
-#define CAMERA_CONFIG_HIGH_SPEED_OFFS 31
+#define CAMERA_CONFIG_CVC_CURR_OFFS 18
-#define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1
+#define CAMERA_CONFIG_CVC_CURR_MASK 0x3
-#define CAMERA_CONFIG_HIGH_SPEED(V) ((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS)
+#define CAMERA_CONFIG_CVC_CURR(V) ((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS)
+
+#define CAMERA_CONFIG_VREF_OFFS 20
+#define CAMERA_CONFIG_VREF_MASK 0x3
+#define CAMERA_CONFIG_VREF(V) ((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS)
+
+#define CAMERA_CONFIG_MCLK_MODE_OFFS 22
+#define CAMERA_CONFIG_MCLK_MODE_MASK 0x3
+#define CAMERA_CONFIG_MCLK_MODE(V) ((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS)
+
+#define CAMERA_CONFIG_OUTPUT_MODE_OFFS 24
+#define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1
+#define CAMERA_CONFIG_OUTPUT_MODE(V) ((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS)
+
+#define CAMERA_CONFIG_CDS_GAIN_OFFS 25
+#define CAMERA_CONFIG_CDS_GAIN_MASK 0x1
+#define CAMERA_CONFIG_CDS_GAIN(V) ((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS)
+
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 26
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1
+#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) ((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) << CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS)
+
+#define CAMERA_CONFIG_ROWS_DELAY_OFFS 27
+#define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f
+#define CAMERA_CONFIG_ROWS_DELAY(V) ((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS)
+
+#define CAMERA_CONFIG2_AUTO_IDLE_OFFS 0
+#define CAMERA_CONFIG2_AUTO_IDLE_MASK 0x1
+#define CAMERA_CONFIG2_AUTO_IDLE(V) ((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS)
+
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS 1
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK 0x1
+#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) ((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) << CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS)
 
 #define CAMERA_DATA_SIZE_OFFS 0
 #define CAMERA_DATA_SIZE_MASK 0x3
@@ -96,7 +105,7 @@ typedef struct {
 #define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
 
 #define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
-#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfffff
+#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfff
 #define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
 
 #define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
@@ -119,9 +128,6 @@ typedef struct {
 inline uint32_t get_camera_pixel(volatile camera_t* reg){
     return (reg->PIXEL >> 0) & 0xffffffff;
 }
-inline void set_camera_pixel(volatile camera_t* reg, uint32_t value){
-    reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
-}
 
 //CAMERA_CONFIG
 inline uint32_t get_camera_config(volatile camera_t* reg){
@@ -130,89 +136,109 @@ inline uint32_t get_camera_config(volatile camera_t* reg){
 inline void set_camera_config(volatile camera_t* reg, uint32_t value){
      reg->CONFIG = value;
 }
-inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg){
-    return (reg->CONFIG >> 0) & 0xff;
-}
-inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0xffU << 0)) | (value << 0);
-}
-inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg){
-    return (reg->CONFIG >> 8) & 0x3;
-}
-inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x3U << 8)) | (value << 8);
-}
-inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg){
-    return (reg->CONFIG >> 10) & 0x3;
-}
-inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x3U << 10)) | (value << 10);
-}
-inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg){
-    return (reg->CONFIG >> 12) & 0x3;
-}
-inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x3U << 12)) | (value << 12);
-}
 inline uint32_t get_camera_config_output_curr(volatile camera_t* reg){
-    return (reg->CONFIG >> 14) & 0x3;
+    return (reg->CONFIG >> 0) & 0x3;
 }
 inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x3U << 14)) | (value << 14);
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
 }
-inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg){
+inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg){
-    return (reg->CONFIG >> 16) & 0x1f;
+    return (reg->CONFIG >> 2) & 0x3;
 }
-inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value){
+inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x1fU << 16)) | (value << 16);
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
 }
-inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg){
+inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg){
-    return (reg->CONFIG >> 21) & 0x1;
+    return (reg->CONFIG >> 4) & 0x3;
 }
-inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value){
+inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x1U << 21)) | (value << 21);
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
 }
-inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg){
+inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg){
-    return (reg->CONFIG >> 22) & 0x1;
+    return (reg->CONFIG >> 6) & 0x3;
 }
-inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value){
+inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x1U << 22)) | (value << 22);
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
 }
-inline uint32_t get_camera_config_output_mode(volatile camera_t* reg){
+inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg){
-    return (reg->CONFIG >> 23) & 0x1;
+    return (reg->CONFIG >> 8) & 0xff;
 }
-inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value){
+inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x1U << 23)) | (value << 23);
+    reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
-}
-inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg){
-    return (reg->CONFIG >> 24) & 0x3;
-}
-inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x3U << 24)) | (value << 24);
-}
-inline uint32_t get_camera_config_vref(volatile camera_t* reg){
-    return (reg->CONFIG >> 26) & 0x3;
-}
-inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x3U << 26)) | (value << 26);
-}
-inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg){
-    return (reg->CONFIG >> 28) & 0x3;
-}
-inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x3U << 28)) | (value << 28);
-}
-inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg){
-    return (reg->CONFIG >> 30) & 0x1;
-}
-inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x1U << 30)) | (value << 30);
 }
 inline uint32_t get_camera_config_high_speed(volatile camera_t* reg){
-    return (reg->CONFIG >> 31) & 0x1;
+    return (reg->CONFIG >> 16) & 0x1;
 }
 inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value){
-    reg->CONFIG = (reg->CONFIG & ~(0x1U << 31)) | (value << 31);
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
+}
+inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg){
+    return (reg->CONFIG >> 17) & 0x1;
+}
+inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
+}
+inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg){
+    return (reg->CONFIG >> 18) & 0x3;
+}
+inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
+}
+inline uint32_t get_camera_config_vref(volatile camera_t* reg){
+    return (reg->CONFIG >> 20) & 0x3;
+}
+inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
+}
+inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg){
+    return (reg->CONFIG >> 22) & 0x3;
+}
+inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
+}
+inline uint32_t get_camera_config_output_mode(volatile camera_t* reg){
+    return (reg->CONFIG >> 24) & 0x1;
+}
+inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
+}
+inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg){
+    return (reg->CONFIG >> 25) & 0x1;
+}
+inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
+}
+inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg){
+    return (reg->CONFIG >> 26) & 0x1;
+}
+inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
+}
+inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg){
+    return (reg->CONFIG >> 27) & 0x1f;
+}
+inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
+}
+
+//CAMERA_CONFIG2
+inline uint32_t get_camera_config2(volatile camera_t* reg){
+     return reg->CONFIG2;
+}
+inline void set_camera_config2(volatile camera_t* reg, uint32_t value){
+     reg->CONFIG2 = value;
+}
+inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg){
+    return (reg->CONFIG2 >> 0) & 0x1;
+}
+inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg){
+    return (reg->CONFIG2 >> 1) & 0x1;
+}
+inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value){
+    reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
 }
 
 //CAMERA_DATA_SIZE
@@ -259,10 +285,10 @@ inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value)
      reg->CAMERA_CLOCK_CTRL = value;
 }
 inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg){
-    return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfffff;
+    return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff;
 }
-inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint32_t value){
+inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value){
-    reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
+    reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
 }
 
 //CAMERA_IE

include/ehrenberg/devices/gen/dma.h

@@ -1,10 +1,10 @@
 /*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-08-02 08:46:07 UTC 
+* Generated at 2025-07-01 11:20:43 UTC 
-* by peakrdl_mnrs version 1.2.7
+* by peakrdl_mnrs version 1.2.9
 */
 
 #ifndef _BSP_DMA_H
@@ -451,4 +451,4 @@ inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t va
     reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
 }
 
-#endif /* _BSP_DMA_H */
+#endif /* _BSP_DMA_H */

include/ehrenberg/devices/gen/gpio.h

@@ -1,9 +1,9 @@
 /*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-12-06 09:43:24 UTC 
+* Generated at 2025-07-01 11:20:43 UTC 
 * by peakrdl_mnrs version 1.2.9
 */
 

include/ehrenberg/devices/gen/i2s.h

@@ -1,9 +1,9 @@
 /*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-12-28 11:01:24 UTC 
+* Generated at 2025-07-01 11:20:43 UTC 
 * by peakrdl_mnrs version 1.2.9
 */
 

include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h

@@ -3,7 +3,7 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2025-02-18 11:11:47 UTC 
+* Generated at 2025-07-01 11:20:43 UTC 
 * by peakrdl_mnrs version 1.2.9
 */
 
@@ -27,6 +27,13 @@ typedef struct {
     volatile uint32_t REG_PAYLOAD_5;
     volatile uint32_t REG_PAYLOAD_6;
     volatile uint32_t REG_PAYLOAD_7;
+    volatile uint32_t REG_PAYLOAD_8;
+    volatile uint32_t REG_PAYLOAD_9;
+    volatile uint32_t REG_PAYLOAD_10;
+    volatile uint32_t REG_PAYLOAD_11;
+    volatile uint32_t REG_PAYLOAD_12;
+    volatile uint32_t REG_PAYLOAD_13;
+    volatile uint32_t REG_PAYLOAD_14;
 }mkcontrolclusterstreamcontroller_t;
 
 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
@@ -97,6 +104,34 @@ typedef struct {
 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
 
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS)
+
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS 0
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK 0xffffffff
+#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS)
+
 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
 inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
      reg->REG_SEND = value;
@@ -204,4 +239,39 @@ inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontro
     reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
 }
 
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_8 = (reg->REG_PAYLOAD_8 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_9 = (reg->REG_PAYLOAD_9 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_10 = (reg->REG_PAYLOAD_10 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_11 = (reg->REG_PAYLOAD_11 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_12 = (reg->REG_PAYLOAD_12 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_13 = (reg->REG_PAYLOAD_13 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14
+inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_14 = (reg->REG_PAYLOAD_14 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
 #endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */

include/ehrenberg/devices/gen/msgif.h

@@ -1,11 +1,11 @@
 /*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+ * Copyright (c) 2023 - 2024 MINRES Technologies GmbH
-*
+ *
-* SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0
-*
+ *
-* Generated at 2024-11-20 11:54:52 UTC 
+ * Generated at 2024-11-20 11:54:52 UTC
-* by peakrdl_mnrs version 1.2.7
+ * by peakrdl_mnrs version 1.2.7
-*/
+ */
 
 #ifndef _BSP_MSGIF_H
 #define _BSP_MSGIF_H
@@ -13,21 +13,21 @@
 #include <stdint.h>
 
 typedef struct {
-    volatile uint32_t REG_SEND;
+  volatile uint32_t REG_SEND;
-    volatile uint32_t REG_HEADER;
+  volatile uint32_t REG_HEADER;
-    volatile uint32_t REG_ACK;
+  volatile uint32_t REG_ACK;
-    volatile uint32_t REG_RECV_ID;
+  volatile uint32_t REG_RECV_ID;
-    volatile uint32_t REG_RECV_PAYLOAD;
+  volatile uint32_t REG_RECV_PAYLOAD;
-    uint8_t fill0[12];
+  uint8_t fill0[12];
-    volatile uint32_t REG_PAYLOAD_0;
+  volatile uint32_t REG_PAYLOAD_0;
-    volatile uint32_t REG_PAYLOAD_1;
+  volatile uint32_t REG_PAYLOAD_1;
-    volatile uint32_t REG_PAYLOAD_2;
+  volatile uint32_t REG_PAYLOAD_2;
-    volatile uint32_t REG_PAYLOAD_3;
+  volatile uint32_t REG_PAYLOAD_3;
-    volatile uint32_t REG_PAYLOAD_4;
+  volatile uint32_t REG_PAYLOAD_4;
-    volatile uint32_t REG_PAYLOAD_5;
+  volatile uint32_t REG_PAYLOAD_5;
-    volatile uint32_t REG_PAYLOAD_6;
+  volatile uint32_t REG_PAYLOAD_6;
-    volatile uint32_t REG_PAYLOAD_7;
+  volatile uint32_t REG_PAYLOAD_7;
-}msgif_t;
+} msgif_t;
 
 #define MSGIF_REG_SEND_OFFS 0
 #define MSGIF_REG_SEND_MASK 0x1
@@ -43,7 +43,8 @@ typedef struct {
 
 #define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
 #define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
-#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \
+  ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
 
 #define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
 #define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
@@ -93,105 +94,83 @@ typedef struct {
 #define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff
 #define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
 
-//MSGIF_REG_SEND
+// MSGIF_REG_SEND
-inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value){
+static inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value) { reg->REG_SEND = value; }
-     reg->REG_SEND = value;
+static inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value) {
-}
+  reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
-inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value){
-    reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
 }
 
-//MSGIF_REG_HEADER
+// MSGIF_REG_HEADER
-inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg){
+static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg) { return reg->REG_HEADER; }
-     return reg->REG_HEADER;
+static inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value) { reg->REG_HEADER = value; }
+static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg) { return (reg->REG_HEADER >> 0) & 0xf; }
+static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
 }
-inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value){
+static inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg) { return (reg->REG_HEADER >> 4) & 0xf; }
-     reg->REG_HEADER = value;
+static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
 }
-inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg){
+static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg) { return (reg->REG_HEADER >> 8) & 0x7; }
-    return (reg->REG_HEADER >> 0) & 0xf;
+static inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value) {
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
 }
-inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value){
+static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg) { return (reg->REG_HEADER >> 11) & 0x3; }
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
+static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value) {
-}
+  reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
-inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg){
-    return (reg->REG_HEADER >> 4) & 0xf;
-}
-inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value){
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
-}
-inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg){
-    return (reg->REG_HEADER >> 8) & 0x7;
-}
-inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value){
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
-}
-inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg){
-    return (reg->REG_HEADER >> 11) & 0x3;
-}
-inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value){
-    reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
 }
 
-//MSGIF_REG_ACK
+// MSGIF_REG_ACK
-inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value){
+static inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value) { reg->REG_ACK = value; }
-     reg->REG_ACK = value;
+static inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value) {
-}
+  reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
-inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value){
-    reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
 }
 
-//MSGIF_REG_RECV_ID
+// MSGIF_REG_RECV_ID
-inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg){
+static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg) { return reg->REG_RECV_ID; }
-     return reg->REG_RECV_ID;
+static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg) { return (reg->REG_RECV_ID >> 0) & 0xf; }
-}
+
-inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg){
+// MSGIF_REG_RECV_PAYLOAD
-    return (reg->REG_RECV_ID >> 0) & 0xf;
+static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg) { return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; }
+
+// MSGIF_REG_PAYLOAD_0
+static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value) {
+  reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
 }
 
-//MSGIF_REG_RECV_PAYLOAD
+// MSGIF_REG_PAYLOAD_1
-inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg){
+static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value) {
-    return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
+  reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
 }
 
-//MSGIF_REG_PAYLOAD_0
+// MSGIF_REG_PAYLOAD_2
-inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value){
+static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
+  reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
 }
 
-//MSGIF_REG_PAYLOAD_1
+// MSGIF_REG_PAYLOAD_3
-inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value){
+static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
+  reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
 }
 
-//MSGIF_REG_PAYLOAD_2
+// MSGIF_REG_PAYLOAD_4
-inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value){
+static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
+  reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
 }
 
-//MSGIF_REG_PAYLOAD_3
+// MSGIF_REG_PAYLOAD_5
-inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value){
+static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
+  reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
 }
 
-//MSGIF_REG_PAYLOAD_4
+// MSGIF_REG_PAYLOAD_6
-inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value){
+static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
+  reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
 }
 
-//MSGIF_REG_PAYLOAD_5
+// MSGIF_REG_PAYLOAD_7
-inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value){
+static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value) {
-    reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
+  reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MSGIF_REG_PAYLOAD_6
-inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value){
-    reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
-}
-
-//MSGIF_REG_PAYLOAD_7
-inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value){
-    reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
 }
 
 #endif /* _BSP_MSGIF_H */

include/ehrenberg/devices/gen/sysctrl.h

@@ -3,7 +3,7 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2025-02-18 11:11:47 UTC 
+* Generated at 2025-06-23 15:39:49 UTC 
 * by peakrdl_mnrs version 1.2.9
 */
 
@@ -16,13 +16,18 @@ typedef struct {
     volatile uint32_t SYSCTRL;
     volatile uint32_t PLLCTRL;
     volatile uint32_t AXI_BACKUP;
+    volatile uint32_t FMCDIV;
 }sysctrl_t;
 
-#define SYSCTRL_SYSCTRL_CC_RESET_OFFS 0
+#define SYSCTRL_SYSCTRL_CC0_RESET_OFFS 0
-#define SYSCTRL_SYSCTRL_CC_RESET_MASK 0x3
+#define SYSCTRL_SYSCTRL_CC0_RESET_MASK 0x3
-#define SYSCTRL_SYSCTRL_CC_RESET(V) ((V & SYSCTRL_SYSCTRL_CC_RESET_MASK) << SYSCTRL_SYSCTRL_CC_RESET_OFFS)
+#define SYSCTRL_SYSCTRL_CC0_RESET(V) ((V & SYSCTRL_SYSCTRL_CC0_RESET_MASK) << SYSCTRL_SYSCTRL_CC0_RESET_OFFS)
 
-#define SYSCTRL_SYSCTRL_MEM_RESET_OFFS 2
+#define SYSCTRL_SYSCTRL_CC1_RESET_OFFS 2
+#define SYSCTRL_SYSCTRL_CC1_RESET_MASK 0x3
+#define SYSCTRL_SYSCTRL_CC1_RESET(V) ((V & SYSCTRL_SYSCTRL_CC1_RESET_MASK) << SYSCTRL_SYSCTRL_CC1_RESET_OFFS)
+
+#define SYSCTRL_SYSCTRL_MEM_RESET_OFFS 4
 #define SYSCTRL_SYSCTRL_MEM_RESET_MASK 0x1
 #define SYSCTRL_SYSCTRL_MEM_RESET(V) ((V & SYSCTRL_SYSCTRL_MEM_RESET_MASK) << SYSCTRL_SYSCTRL_MEM_RESET_OFFS)
 
@@ -46,6 +51,14 @@ typedef struct {
 #define SYSCTRL_AXI_BACKUP_MASK 0x1f
 #define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS)
 
+#define SYSCTRL_FMCDIV_FMCDIVVALID_OFFS 0
+#define SYSCTRL_FMCDIV_FMCDIVVALID_MASK 0x1
+#define SYSCTRL_FMCDIV_FMCDIVVALID(V) ((V & SYSCTRL_FMCDIV_FMCDIVVALID_MASK) << SYSCTRL_FMCDIV_FMCDIVVALID_OFFS)
+
+#define SYSCTRL_FMCDIV_FMCDIVFACTOR_OFFS 1
+#define SYSCTRL_FMCDIV_FMCDIVFACTOR_MASK 0xf
+#define SYSCTRL_FMCDIV_FMCDIVFACTOR(V) ((V & SYSCTRL_FMCDIV_FMCDIVFACTOR_MASK) << SYSCTRL_FMCDIV_FMCDIVFACTOR_OFFS)
+
 //SYSCTRL_SYSCTRL
 inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){
      return reg->SYSCTRL;
@@ -53,17 +66,23 @@ inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){
 inline void set_sysctrl_sysctrl(volatile sysctrl_t* reg, uint32_t value){
      reg->SYSCTRL = value;
 }
-inline uint32_t get_sysctrl_sysctrl_cc_reset(volatile sysctrl_t* reg){
+inline uint32_t get_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg){
     return (reg->SYSCTRL >> 0) & 0x3;
 }
-inline void set_sysctrl_sysctrl_cc_reset(volatile sysctrl_t* reg, uint8_t value){
+inline void set_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg, uint8_t value){
     reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 0)) | (value << 0);
 }
+inline uint32_t get_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg){
+    return (reg->SYSCTRL >> 2) & 0x3;
+}
+inline void set_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg, uint8_t value){
+    reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 2)) | (value << 2);
+}
 inline uint32_t get_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg){
-    return (reg->SYSCTRL >> 2) & 0x1;
+    return (reg->SYSCTRL >> 4) & 0x1;
 }
 inline void set_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg, uint8_t value){
-    reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 2)) | (value << 2);
+    reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 4)) | (value << 4);
 }
 
 //SYSCTRL_PLLCTRL
@@ -109,4 +128,15 @@ inline void set_sysctrl_axi_backup_page(volatile sysctrl_t* reg, uint8_t value){
     reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0x1fU << 0)) | (value << 0);
 }
 
+//SYSCTRL_FMCDIV
+inline void set_sysctrl_fmcdiv(volatile sysctrl_t* reg, uint32_t value){
+     reg->FMCDIV = value;
+}
+inline void set_sysctrl_fmcdiv_fmcDivValid(volatile sysctrl_t* reg, uint8_t value){
+    reg->FMCDIV = (reg->FMCDIV & ~(0x1U << 0)) | (value << 0);
+}
+inline void set_sysctrl_fmcdiv_fmcDivFactor(volatile sysctrl_t* reg, uint8_t value){
+    reg->FMCDIV = (reg->FMCDIV & ~(0xfU << 1)) | (value << 1);
+}
+
 #endif /* _BSP_SYSCTRL_H */

include/ehrenberg/devices/gen/timercounter.h

@@ -1,9 +1,9 @@
 /*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-12-26 18:07:07 UTC 
+* Generated at 2025-07-01 11:20:43 UTC 
 * by peakrdl_mnrs version 1.2.9
 */
 

include/ehrenberg/devices/gen/uart.h

@@ -1,10 +1,10 @@
 /*
-* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+* Copyright (c) 2023 - 2025 MINRES Technologies GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-08-02 08:46:07 UTC 
+* Generated at 2025-07-01 11:20:43 UTC 
-* by peakrdl_mnrs version 1.2.7
+* by peakrdl_mnrs version 1.2.9
 */
 
 #ifndef _BSP_UART_H
@@ -20,21 +20,9 @@ typedef struct {
     volatile uint32_t STATUS_REG;
 }uart_t;
 
-#define UART_RX_TX_REG_DATA_OFFS 0
+#define UART_RX_TX_REG_OFFS 0
-#define UART_RX_TX_REG_DATA_MASK 0xff
+#define UART_RX_TX_REG_MASK 0xff
-#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
+#define UART_RX_TX_REG(V) ((V & UART_RX_TX_REG_MASK) << UART_RX_TX_REG_OFFS)
-
-#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
-#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
-#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
-
-#define UART_RX_TX_REG_TX_FREE_OFFS 15
-#define UART_RX_TX_REG_TX_FREE_MASK 0x1
-#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
-
-#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
-#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
-#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
 
 #define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
 #define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
@@ -76,27 +64,39 @@ typedef struct {
 #define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
 #define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
 
-#define UART_STATUS_REG_READ_ERROR_OFFS 0
+#define UART_STATUS_REG_RX_AVAIL_OFFS 0
+#define UART_STATUS_REG_RX_AVAIL_MASK 0x1
+#define UART_STATUS_REG_RX_AVAIL(V) ((V & UART_STATUS_REG_RX_AVAIL_MASK) << UART_STATUS_REG_RX_AVAIL_OFFS)
+
+#define UART_STATUS_REG_TX_FREE_OFFS 1
+#define UART_STATUS_REG_TX_FREE_MASK 0x1
+#define UART_STATUS_REG_TX_FREE(V) ((V & UART_STATUS_REG_TX_FREE_MASK) << UART_STATUS_REG_TX_FREE_OFFS)
+
+#define UART_STATUS_REG_TX_EMPTY_OFFS 2
+#define UART_STATUS_REG_TX_EMPTY_MASK 0x1
+#define UART_STATUS_REG_TX_EMPTY(V) ((V & UART_STATUS_REG_TX_EMPTY_MASK) << UART_STATUS_REG_TX_EMPTY_OFFS)
+
+#define UART_STATUS_REG_READ_ERROR_OFFS 8
 #define UART_STATUS_REG_READ_ERROR_MASK 0x1
 #define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
 
-#define UART_STATUS_REG_STALL_OFFS 1
+#define UART_STATUS_REG_STALL_OFFS 9
 #define UART_STATUS_REG_STALL_MASK 0x1
 #define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
 
-#define UART_STATUS_REG_BREAK_LINE_OFFS 8
+#define UART_STATUS_REG_BREAK_LINE_OFFS 16
 #define UART_STATUS_REG_BREAK_LINE_MASK 0x1
 #define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
 
-#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
+#define UART_STATUS_REG_BREAK_DETECTED_OFFS 17
 #define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
 #define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
 
-#define UART_STATUS_REG_SET_BREAK_OFFS 10
+#define UART_STATUS_REG_SET_BREAK_OFFS 18
 #define UART_STATUS_REG_SET_BREAK_MASK 0x1
 #define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
 
-#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
+#define UART_STATUS_REG_CLEAR_BREAK_OFFS 19
 #define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
 #define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
 
@@ -113,15 +113,6 @@ inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
 inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
     reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
 }
-inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
-    return (reg->RX_TX_REG >> 14) & 0x1;
-}
-inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
-    return (reg->RX_TX_REG >> 15) & 0x1;
-}
-inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
-    return (reg->RX_TX_REG >> 16) & 0x1;
-}
 
 //UART_INT_CTRL_REG
 inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
@@ -151,6 +142,9 @@ inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_
 inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){
     return (reg->INT_CTRL_REG >> 8) & 0x1;
 }
+inline void set_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 8)) | (value << 8);
+}
 inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
     return (reg->INT_CTRL_REG >> 9) & 0x1;
 }
@@ -205,32 +199,41 @@ inline uint32_t get_uart_status_reg(volatile uart_t* reg){
 inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){
      reg->STATUS_REG = value;
 }
-inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
+inline uint32_t get_uart_status_reg_rx_avail(volatile uart_t* reg){
     return (reg->STATUS_REG >> 0) & 0x1;
 }
-inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
+inline uint32_t get_uart_status_reg_tx_free(volatile uart_t* reg){
     return (reg->STATUS_REG >> 1) & 0x1;
 }
-inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
+inline uint32_t get_uart_status_reg_tx_empty(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 2) & 0x1;
+}
+inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
     return (reg->STATUS_REG >> 8) & 0x1;
 }
-inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
+inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
     return (reg->STATUS_REG >> 9) & 0x1;
 }
+inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 16) & 0x1;
+}
+inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 17) & 0x1;
+}
 inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
-    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 17)) | (value << 17);
 }
 inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){
-    return (reg->STATUS_REG >> 10) & 0x1;
+    return (reg->STATUS_REG >> 18) & 0x1;
 }
 inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
-    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 18)) | (value << 18);
 }
 inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){
-    return (reg->STATUS_REG >> 11) & 0x1;
+    return (reg->STATUS_REG >> 19) & 0x1;
 }
 inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
-    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 19)) | (value << 19);
 }
 
-#endif /* _BSP_UART_H */
+#endif /* _BSP_UART_H */

include/ehrenberg/devices/gpio.h

@@ -2,11 +2,12 @@
 #define _DEVICES_GPIO_H
 
 #include <stdint.h>
+
 #include "gen/gpio.h"
 
-inline void gpio_init(volatile gpio_t* reg) {
+static inline void gpio_init(volatile gpio_t* reg) {
-    set_gpio_write(reg, 0);
+  set_gpio_write(reg, 0);
-    set_gpio_writeEnable(reg, 0);
+  set_gpio_writeEnable(reg, 0);
 }
 
 #endif /* _DEVICES_GPIO_H */

include/ehrenberg/devices/interrupt.h

@@ -5,7 +5,6 @@
 
 #define irq_t void*
 
-inline void irq_init(volatile irq_t* reg){
+static inline void irq_init(volatile irq_t* reg) {}
-}
 
 #endif /* _DEVICES_INTERRUPT_H */

include/ehrenberg/devices/msg_if.h

@@ -1,6 +1,6 @@
 #ifndef _DEVICES_MSG_IF_H
 #define _DEVICES_MSG_IF_H
 
-#include "gen/msgif.h"
+#include "gen/mkcontrolclusterstreamcontroller.h"
 
 #endif /* _DEVICES_MSG_IF_H */

include/ehrenberg/devices/qspi.h

@@ -1,18 +1,18 @@
 #ifndef _DEVICES_QSPI_H
 #define _DEVICES_QSPI_H
 
-#include <stdint.h>
 #include "gen/apb3spi.h"
+#include <stdint.h>
 
 #define qspi_t apb3spi_t
 typedef struct {
-    uint32_t cpol;
+  uint32_t cpol;
-    uint32_t cpha;
+  uint32_t cpha;
-    uint32_t mode;
+  uint32_t mode;
-    uint32_t clkDivider;
+  uint32_t clkDivider;
-    uint32_t ssSetup;
+  uint32_t ssSetup;
-    uint32_t ssHold;
+  uint32_t ssHold;
-    uint32_t ssDisable;
+  uint32_t ssDisable;
 } spi_cfg;
 
 #define SPI_CMD_WRITE (1 << 8)
@@ -26,57 +26,65 @@ typedef struct {
 #define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
 #define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
 
-static inline void spi_configure(volatile qspi_t* qspi, spi_cfg *config){
+static inline void spi_configure(volatile qspi_t *qspi, spi_cfg *config) {
-    set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4));
+  set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) |
-    set_apb3spi_sclk_config(qspi, config->clkDivider);
+                               (config->mode << 4));
-    set_apb3spi_ssgen_setup(qspi, config->ssSetup);
+  set_apb3spi_sclk_config(qspi, config->clkDivider);
-    set_apb3spi_ssgen_hold(qspi, config->ssHold);
+  set_apb3spi_ssgen_setup(qspi, config->ssSetup);
-    set_apb3spi_ssgen_disable(qspi, config->ssDisable);
+  set_apb3spi_ssgen_hold(qspi, config->ssHold);
+  set_apb3spi_ssgen_disable(qspi, config->ssDisable);
 }
 
-static inline void spi_init(volatile qspi_t* spi){
+static inline void spi_init(volatile qspi_t *spi) {
-    spi_cfg spiCfg;
+  spi_cfg spiCfg;
-    spiCfg.cpol = 0;
+  spiCfg.cpol = 0;
-    spiCfg.cpha = 0;
+  spiCfg.cpha = 0;
-    spiCfg.mode = 0;
+  spiCfg.mode = 0;
-    spiCfg.clkDivider = 2;
+  spiCfg.clkDivider = 2;
-    spiCfg.ssSetup = 2;
+  spiCfg.ssSetup = 2;
-    spiCfg.ssHold = 2;
+  spiCfg.ssHold = 2;
-    spiCfg.ssDisable = 2;
+  spiCfg.ssDisable = 2;
-    spi_configure(spi, &spiCfg);
+  spi_configure(spi, &spiCfg);
 }
 
-static inline uint32_t spi_cmd_avail(volatile qspi_t* qspi){
+static inline uint32_t spi_cmd_avail(volatile qspi_t *qspi) {
-    return qspi->STATUS & 0xFFFF;
+  return qspi->STATUS & 0xFFFF;
 }
-static inline uint32_t spi_rsp_occupied(volatile qspi_t* qspi){
+static inline uint32_t spi_rsp_occupied(volatile qspi_t *qspi) {
-    return qspi->STATUS >> 16;
+  return qspi->STATUS >> 16;
 }
 
-static inline void spi_write(volatile qspi_t* qspi, uint8_t data){
+static inline void spi_write(volatile qspi_t *qspi, uint8_t data) {
-    while(spi_cmd_avail(qspi) == 0);
+  while (spi_cmd_avail(qspi) == 0)
-    qspi->DATA = data | SPI_CMD_WRITE;
+    ;
+  qspi->DATA = data | SPI_CMD_WRITE;
 }
 
-static inline uint8_t spi_read(volatile qspi_t* qspi){
+static inline uint8_t spi_read(volatile qspi_t *qspi) {
-    while(spi_cmd_avail(qspi) == 0);
+  while (spi_cmd_avail(qspi) == 0)
-    qspi->DATA = SPI_CMD_READ;
+    ;
-    while(spi_rsp_occupied(qspi) == 0);
+  qspi->DATA = SPI_CMD_READ;
-    while((qspi->DATA & 0x80000000)==0);
+  while (spi_rsp_occupied(qspi) == 0)
-    return qspi->DATA;
+    ;
+  while ((qspi->DATA & 0x80000000) == 0)
+    ;
+  return qspi->DATA;
 }
 
-static inline void spi_select(volatile qspi_t* qspi, uint32_t slaveId){
+static inline void spi_select(volatile qspi_t *qspi, uint32_t slaveId) {
-    while(spi_cmd_avail(qspi) == 0);
+  while (spi_cmd_avail(qspi) == 0)
-    qspi->DATA = slaveId | 0x80 | SPI_CMD_SS;
+    ;
+  qspi->DATA = (slaveId & 0x3) | 0x80 | SPI_CMD_SS;
 }
 
-static inline void spi_deselect(volatile qspi_t* qspi, uint32_t slaveId){
+static inline void spi_deselect(volatile qspi_t *qspi, uint32_t slaveId) {
-    while(spi_cmd_avail(qspi) == 0);
+  while (spi_cmd_avail(qspi) == 0)
-    qspi->DATA = slaveId | SPI_CMD_SS;
+    ;
+  qspi->DATA = (slaveId & 0x3) | SPI_CMD_SS;
 }
 
-static inline void spi_wait_tx_idle(volatile qspi_t* qspi){
+static inline void spi_wait_tx_idle(volatile qspi_t *qspi) {
-    while(spi_cmd_avail(qspi) < 0x20);
+  while (spi_cmd_avail(qspi) < 0x20)
+    ;
 }
 #endif /* _DEVICES_QSPI_H */

include/ehrenberg/devices/sysctrl.h

@@ -0,0 +1,6 @@
+#ifndef _DEVICES_SYSCTRL_IF_H
+#define _DEVICES_SYSCTRL_IF_H
+
+#include "gen/sysctrl.h"
+
+#endif /* _DEVICES_sysctrl_IF_H */

include/ehrenberg/devices/timer.h

@@ -2,18 +2,13 @@
 #define _DEVICES_TIMER_H
 
 #include <stdint.h>
+
 #include "gen/timercounter.h"
 
-inline void prescaler_init(timercounter_t* reg, uint16_t value){
+static inline void prescaler_init(timercounter_t *reg, uint16_t value) { set_timercounter_prescaler(reg, value); }
-    set_timercounter_prescaler(reg, value);
-}
 
-inline void timer_t0__init(timercounter_t *reg){
+static inline void timer_t0__init(timercounter_t *reg) { set_timercounter_t0_overflow(reg, 0xffffffff); }
-    set_timercounter_t0_overflow(reg, 0xffffffff);
-}
 
-inline void timer_t1__init(timercounter_t *reg){
+static inline void timer_t1__init(timercounter_t *reg) { set_timercounter_t1_overflow(reg, 0xffffffff); }
-    set_timercounter_t1_overflow(reg, 0xffffffff);
-}
 
 #endif /* _DEVICES_TIMER_H */

include/ehrenberg/devices/uart.h

@@ -5,19 +5,19 @@
 #include "gen/uart.h"
 
 static inline uint32_t uart_get_tx_free(volatile uart_t* reg){
-    return get_uart_rx_tx_reg_tx_free(reg);
+    return get_uart_status_reg_tx_free(reg);
 }
 
 static inline uint32_t uart_get_tx_empty(volatile uart_t* reg){
-    return get_uart_rx_tx_reg_tx_empty(reg);
+    return get_uart_status_reg_tx_empty(reg);
 }
 
 static inline uint32_t uart_get_rx_avail(volatile uart_t* reg){
-    return get_uart_rx_tx_reg_rx_avail(reg);
+    return get_uart_status_reg_rx_avail(reg);
 }
 
 static inline void uart_write(volatile uart_t* reg, uint8_t data){
-    while(get_uart_rx_tx_reg_tx_free(reg) == 0);
+    while(get_uart_status_reg_tx_free(reg) == 0);
     set_uart_rx_tx_reg_data(reg, data);
 }
 

libwrap/stdlib/malloc.c

@@ -2,16 +2,15 @@
 
 /* These functions are intended for embedded RV32 systems and are
    obviously incorrect in general. */
+void *__wrap_malloc(unsigned long sz);
+void __wrap_free(void *ptr);
 
-void* __wrap_malloc(unsigned long sz)
+void *__wrap_malloc(unsigned long sz) {
-{
+  extern void *sbrk(long);
-  extern void* sbrk(long);
+  void *res = sbrk(sz);
-  void* res = sbrk(sz);
   if ((long)res == -1)
     return 0;
   return res;
 }
 
-void __wrap_free(void* ptr)
+void __wrap_free(void *ptr) { (void)(ptr); }
-{
-}

libwrap/sys/puts.c

@@ -19,7 +19,7 @@ int __wrap_puts(const char *s) {
 #endif
   while (*s != '\0') {
 #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
-    while (get_uart_rx_tx_reg_tx_free(uart) == 0)
+    while (get_uart_status_reg_tx_free(uart) == 0)
       ;
     uart_write(uart, *s);
 #elif defined(BOARD_iss)

libwrap/sys/read.c

@@ -35,7 +35,7 @@ ssize_t __wrap_read(int fd, void *ptr, size_t len) {
   if (isatty(fd)) {
 #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
     for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
-                                   (get_uart_rx_tx_reg_rx_avail(uart) > 0);
+                                   (get_uart_status_reg_rx_avail(uart) > 0);
          current++) {
       *current = uart_read(uart);
       result++;

libwrap/sys/write.c

@@ -4,6 +4,7 @@
 #include <stdint.h>
 #include <sys/types.h>
 #include <unistd.h>
+#include <stdint.h>
 
 #include "platform.h"
 #include "stub.h"
@@ -12,6 +13,8 @@
 #include "semihosting.h"
 #endif
 
+extern uint32_t tohost;
+
 ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
   const uint8_t *current = (const uint8_t *)ptr;
 #if defined(SEMIHOSTING)
@@ -25,20 +28,28 @@ ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
     return len;
   }
   // return len;
+#elif defined(BOARD_iss)
+  volatile uint64_t payload[4];
+  payload[0]= 64;
+  payload[1]= 0;
+  payload[2]= (uintptr_t)ptr;
+  payload[3]= len;
+  tohost = (uint32_t)payload;
+  return len;
 #endif
   if (isatty(fd)) {
     for (size_t jj = 0; jj < len; jj++) {
 #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
-      while (get_uart_rx_tx_reg_tx_free(uart) == 0)
+      while (get_uart_status_reg_tx_free(uart) == 0)
         ;
       uart_write(uart, current[jj]);
       if (current[jj] == '\n') {
-        while (get_uart_rx_tx_reg_tx_free(uart) == 0)
+        while (get_uart_status_reg_tx_free(uart) == 0)
           ;
         uart_write(uart, '\r');
       }
 #elif defined(BOARD_iss)
-      *((uint32_t *)0xFFFF0000) = current[jj];
+      // *((uint32_t *)0xFFFF0000) = current[jj];
 #elif defined(BOARD_TGCP)
       // TODO: implement
 #else