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base: Firmware:428d3ac28556bf6d2229dd1b767bcd46008f7552
Branches Tags
Firmware:main Firmware:flexki Firmware:develop Firmware:cmake_flow
...
compare: Firmware:flexki
Branches Tags
Firmware:flexki Firmware:develop Firmware:cmake_flow Firmware:main

17 Commits
428d3ac285 ... flexki

Author SHA1 Message Date
Johannes Wirth
b375ff4a72 Add fmc clock divider to sysctrl 2025-06-24 17:00:24 +02:00
Johannes Wirth
5f26d9081c add cache flush to cluster info 2025-05-15 20:11:55 +02:00
Johannes Wirth
30cebaa066 support up to 15 words per message 2025-05-05 15:53:39 +02:00
Eyck Jentzsch
546851f509 disables start.S defines 2025-04-13 21:09:37 +02:00
Eyck Jentzsch
569df1536a adds *.o file sto cleanup 2025-04-13 18:15:06 +02:00
Eyck Jentzsch
e1ea5a98d6 fixes inline declarations of functions 2025-04-13 18:13:31 +02:00
Eyck Jentzsch
c73bc9e144 changes XIP start address 2025-04-12 09:39:49 +02:00
Johannes Wirth
cb6be16832 update cluster info 2025-04-10 16:59:33 +02:00
Johannes Wirth
2ab28cf7f7 update address map 2025-04-10 13:05:58 +02:00
Johannes Wirth
263d7d9074 Update cluster_info header 2025-04-08 21:40:46 +02:00
Johannes Wirth
aca6bc8a20 Update compute cluster addresses 2025-04-08 11:36:50 +02:00
Eyck Jentzsch
c88caf9906 adds mask for ssid number 2025-04-06 19:36:37 +02:00
Eyck Jentzsch
39969f0e29 fixes compiler warnings 2025-03-20 09:31:17 +01:00
Johannes Wirth
e7a21b627e Update cluster info for new address map 2025-03-18 13:44:11 +01:00
Eyck Jentzsch
f21ea46bef uses htif in iss setting 2025-03-14 11:44:03 +01:00
Eyck Jentzsch
b9b8c51957 updates and unifies linkerscript 2025-03-07 20:52:30 +01:00
Florian Kriebel
b6ce43f57a updates ram start location 2025-03-07 11:54:30 +01:00
27 changed files with 1644 additions and 1840 deletions
Expand all files Collapse all files

6
env/common-clang.mk vendored
View File

@ -63,10 +63,6 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)
.PHONY: clean
clean:
rm -f $(TARGET) $(LINK_OBJS)
.PHONY: clean-all
clean-all:
rm -f $(CLEAN_OBJS) $(LIBWRAP)
rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf *.o
endif

2
env/common-gcc.mk vendored
View File

@ -79,6 +79,6 @@ $(CXX_OBJS): %.o: %.cpp $(HEADERS)
.PHONY: clean
clean:
rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf
rm -f $(CLEAN_OBJS) $(LIBWRAP) *.a *.hex *.map *.dis *.elf *.o
endif

14
env/ehrenberg/link.lds vendored
View File

@ -131,6 +131,13 @@ SECTIONS
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
.srodata :
{
*(.srodata.cst16)
@ -140,13 +147,6 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );

10
env/ehrenberg/platform.h vendored
View File

@ -39,11 +39,15 @@
#define dma PERIPH(dma_t, APB_BASE + 0xB0000)
#define msgif PERIPH(mkcontrolclusterstreamcontroller_t, APB_BASE + 0xC0000)
#include "ehrenberg/devices/flexki_messages.h"
#include "ehrenberg/devices/fki_cluster_info.h"
#include "ehrenberg/devices/flexki_messages.h"
#define XIP_START_LOC 0xE0040000
#define RAM_START_LOC 0x80000000
#ifndef XIP_START_LOC
#define XIP_START_LOC 0xE0000000
#endif
#ifndef RAM_START_LOC
#define RAM_START_LOC 0xC0000000
#endif
// Misc

18
env/ehrenberg/ram.lds vendored
View File

@ -118,10 +118,18 @@ SECTIONS
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>rom :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
.srodata :
{
PROVIDE( __global_pointer$ = . + 0x800 );
@ -132,12 +140,6 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>rom :ram_init
.sdata :
{
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
@ -155,6 +157,7 @@ SECTIONS
} >ram AT>ram :ram
. = ALIGN(8);
__BSS_END__ = .;
PROVIDE( _end = . );
PROVIDE( end = . );
@ -164,4 +167,7 @@ SECTIONS
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
}

21
env/ehrenberg/rom.lds vendored
View File

@ -4,8 +4,8 @@ ENTRY( _start )
MEMORY
{
rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 4k
ram (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 32k
rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 2k
ram (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128k
}
PHDRS
@ -118,13 +118,20 @@ SECTIONS
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>rom :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
.srodata :
{
PROVIDE( __global_pointer$ = . + 0x800 );
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
@ -132,12 +139,6 @@ SECTIONS
*(.srodata .srodata.*)
} >ram AT>rom :ram_init
.sdata :
{
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>rom :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
@ -155,6 +156,8 @@ SECTIONS
} >ram AT>ram :ram
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );

180
env/ehrenberg/spi_flash.lds vendored Normal file
View File

@ -0,0 +1,180 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
flash (rxai!w) : ORIGIN = 0xE0000000, LENGTH = 16M
ram (wxa!ri) : ORIGIN = 0xC0000000, LENGTH = 128K
dram (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 2048M
}
PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
dram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init ORIGIN(flash) :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash :flash
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >flash AT>flash :flash
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash :flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash :flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash :flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash :flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash :flash
.dummy :
{
*(.comment.*)
}
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash :flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
} >ram AT>flash :ram_init
.sdata :
{
__SDATA_BEGIN__ = .;
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
} >ram AT>flash :ram_init
.srodata :
{
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
__BSS_END__ = .;
__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
PROVIDE( tohost = 0xfffffff0 );
PROVIDE( fromhost = 0xfffffff8 );
}

2
env/start.S vendored
View File

@ -8,11 +8,13 @@ _start:
.option push
.option norelax
.option norvc
//#ifdef WITH_SIGNATURE
j 1f
.2byte 0x4e4d
.2byte 0x5352
.4byte 0x669
1:
//#endif
la gp, __global_pointer$
.option pop
la sp, _sp

425
include/ehrenberg/devices/fki_cluster_info.h
View File

@ -1,4 +1,3 @@
#pragma once
#ifndef _FKI_CLUSTER_INFO_H
#define _FKI_CLUSTER_INFO_H
@ -8,19 +7,21 @@ static uint8_t fki_dma(uint8_t cluster);
static uint8_t fki_axi2stream(uint8_t cluster);
static uint8_t fki_stream2axi(uint8_t cluster);
static uint8_t fki_dma_adapter(uint8_t cluster);
static uint64_t fki_addr_ccc_peMapping(uint8_t cluster);
static uint64_t fki_addr_sram1(uint8_t cluster);
static uint64_t fki_addr_ccc_configMem(uint8_t cluster);
static uint64_t fki_addr_sram2(uint8_t cluster);
static uint64_t fki_addr_cntrl_cva5(uint8_t cluster);
static uint64_t fki_addr_cntrl_tgc(uint8_t cluster);
static uint64_t fki_addr_ccc_idxTasks(uint8_t cluster);
static uint64_t fki_addr_ccc_idxJobs(uint8_t cluster);
static uint64_t fki_addr_aes_adapter(uint8_t cluster);
static uint64_t fki_addr_ut_adapter(uint8_t cluster);
static uint64_t fki_addr_sram0(uint8_t cluster);
static uint64_t fki_addr_sram3(uint8_t cluster);
static uint64_t fki_addr_hide_adapter(uint8_t cluster);
static inline uint32_t fki_addr_ccc_peMapping(uint8_t cluster);
static inline uint32_t fki_addr_sram1(uint8_t cluster);
static inline uint32_t fki_addr_sram2(uint8_t cluster);
static inline uint32_t fki_addr_cntrl_cva5(uint8_t cluster);
static inline uint32_t fki_addr_cntrl_tgc(uint8_t cluster);
static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster);
static inline uint32_t fki_addr_cacheFlushControl(uint8_t cluster);
static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster);
static inline uint32_t fki_addr_ccc_idxJobs(uint8_t cluster);
static inline uint32_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster);
static inline uint32_t fki_addr_ccc_configMem(uint8_t cluster);
static inline uint32_t fki_addr_aes_adapter(uint8_t cluster);
static inline uint32_t fki_addr_ut_adapter(uint8_t cluster);
static inline uint32_t fki_addr_sram0(uint8_t cluster);
static inline uint32_t fki_addr_sram3(uint8_t cluster);
#define Compute0 2
#define Compute0_ccc 2,0
@ -29,18 +30,50 @@ static uint64_t fki_addr_hide_adapter(uint8_t cluster);
#define Compute0_dma 2,4
#define Compute0_dma_adapter 2,5
#define ADDR_Compute0_ccc_idxJobs 0x80004000
#define BYTES_Compute0_ccc_idxJobs 4096
#define HIGH_Compute0_ccc_idxJobs 0x80004fff
#define ADDR_Compute0_ccc_idxTasks 0x80005000
#define BYTES_Compute0_ccc_idxTasks 4096
#define HIGH_Compute0_ccc_idxTasks 0x80005fff
#define ADDR_Compute0_ccc_configMem 0x80000000
#define BYTES_Compute0_ccc_configMem 16384
#define HIGH_Compute0_ccc_configMem 0x80003fff
#define ADDR_Compute0_ccc_peMapping 0x80006000
#define BYTES_Compute0_ccc_peMapping 4096
#define HIGH_Compute0_ccc_peMapping 0x80006fff
#define ADDR_Compute0_aes_adapter 0x80007000
#define ADDR_Compute0_hide_adapter 0x80008000
#define ADDR_Compute0_cntrl_cva5 0x80009000
#define ADDR_Compute0_cntrl_tgc 0x8000a000
#define ADDR_Compute0_ut_adapter 0x8000b000
#define ADDR_Compute0_sram0 0x8000c000
#define ADDR_Compute0_sram1 0x8010c000
#define ADDR_Compute0_sram2 0x8018c000
#define ADDR_Compute0_sram3 0x8020c000
#define BYTES_Compute0_aes_adapter 4096
#define HIGH_Compute0_aes_adapter 0x80007fff
#define ADDR_Compute0_cntrl_cva5_clusterReg 0x8000a000
#define BYTES_Compute0_cntrl_cva5_clusterReg 4096
#define HIGH_Compute0_cntrl_cva5_clusterReg 0x8000afff
#define ADDR_Compute0_cntrl_cva5 0x80008000
#define BYTES_Compute0_cntrl_cva5 8192
#define HIGH_Compute0_cntrl_cva5 0x80009fff
#define ADDR_Compute0_cntrl_tgc_clusterReg 0x8000d000
#define BYTES_Compute0_cntrl_tgc_clusterReg 4096
#define HIGH_Compute0_cntrl_tgc_clusterReg 0x8000dfff
#define ADDR_Compute0_cntrl_tgc 0x8000b000
#define BYTES_Compute0_cntrl_tgc 8192
#define HIGH_Compute0_cntrl_tgc 0x8000cfff
#define ADDR_Compute0_ut_adapter 0x8000e000
#define BYTES_Compute0_ut_adapter 4096
#define HIGH_Compute0_ut_adapter 0x8000efff
#define ADDR_Compute0_cacheFlushControl 0x8000f000
#define BYTES_Compute0_cacheFlushControl 4096
#define HIGH_Compute0_cacheFlushControl 0x8000ffff
#define ADDR_Compute0_sram0 0x80010000
#define BYTES_Compute0_sram0 524288
#define HIGH_Compute0_sram0 0x8008ffff
#define ADDR_Compute0_sram1 0x80090000
#define BYTES_Compute0_sram1 262144
#define HIGH_Compute0_sram1 0x800cffff
#define ADDR_Compute0_sram2 0x800d0000
#define BYTES_Compute0_sram2 262144
#define HIGH_Compute0_sram2 0x8010ffff
#define ADDR_Compute0_sram3 0x80110000
#define BYTES_Compute0_sram3 262144
#define HIGH_Compute0_sram3 0x8014ffff
#define Compute1 3
#define Compute1_ccc 3,0
#define Compute1_stream2axi 3,1
@ -48,18 +81,50 @@ static uint64_t fki_addr_hide_adapter(uint8_t cluster);
#define Compute1_dma 3,4
#define Compute1_dma_adapter 3,5
#define ADDR_Compute1_ccc_idxJobs 0x90004000
#define BYTES_Compute1_ccc_idxJobs 4096
#define HIGH_Compute1_ccc_idxJobs 0x90004fff
#define ADDR_Compute1_ccc_idxTasks 0x90005000
#define BYTES_Compute1_ccc_idxTasks 4096
#define HIGH_Compute1_ccc_idxTasks 0x90005fff
#define ADDR_Compute1_ccc_configMem 0x90000000
#define BYTES_Compute1_ccc_configMem 16384
#define HIGH_Compute1_ccc_configMem 0x90003fff
#define ADDR_Compute1_ccc_peMapping 0x90006000
#define BYTES_Compute1_ccc_peMapping 4096
#define HIGH_Compute1_ccc_peMapping 0x90006fff
#define ADDR_Compute1_aes_adapter 0x90007000
#define ADDR_Compute1_hide_adapter 0x90008000
#define ADDR_Compute1_cntrl_cva5 0x90009000
#define ADDR_Compute1_cntrl_tgc 0x9000a000
#define ADDR_Compute1_ut_adapter 0x9000b000
#define ADDR_Compute1_sram0 0x9000c000
#define ADDR_Compute1_sram1 0x9010c000
#define ADDR_Compute1_sram2 0x9018c000
#define ADDR_Compute1_sram3 0x9020c000
#define BYTES_Compute1_aes_adapter 4096
#define HIGH_Compute1_aes_adapter 0x90007fff
#define ADDR_Compute1_cntrl_cva5_clusterReg 0x8000a000
#define BYTES_Compute1_cntrl_cva5_clusterReg 4096
#define HIGH_Compute1_cntrl_cva5_clusterReg 0x8000afff
#define ADDR_Compute1_cntrl_cva5 0x90008000
#define BYTES_Compute1_cntrl_cva5 12288
#define HIGH_Compute1_cntrl_cva5 0x9000afff
#define ADDR_Compute1_cntrl_tgc_clusterReg 0x8000d000
#define BYTES_Compute1_cntrl_tgc_clusterReg 4096
#define HIGH_Compute1_cntrl_tgc_clusterReg 0x8000dfff
#define ADDR_Compute1_cntrl_tgc 0x9000b000
#define BYTES_Compute1_cntrl_tgc 12288
#define HIGH_Compute1_cntrl_tgc 0x9000dfff
#define ADDR_Compute1_ut_adapter 0x9000e000
#define BYTES_Compute1_ut_adapter 4096
#define HIGH_Compute1_ut_adapter 0x9000efff
#define ADDR_Compute1_cacheFlushControl 0x9000f000
#define BYTES_Compute1_cacheFlushControl 4096
#define HIGH_Compute1_cacheFlushControl 0x9000ffff
#define ADDR_Compute1_sram0 0x90010000
#define BYTES_Compute1_sram0 524288
#define HIGH_Compute1_sram0 0x9008ffff
#define ADDR_Compute1_sram1 0x90090000
#define BYTES_Compute1_sram1 262144
#define HIGH_Compute1_sram1 0x900cffff
#define ADDR_Compute1_sram2 0x900d0000
#define BYTES_Compute1_sram2 262144
#define HIGH_Compute1_sram2 0x9010ffff
#define ADDR_Compute1_sram3 0x90110000
#define BYTES_Compute1_sram3 262144
#define HIGH_Compute1_sram3 0x9014ffff
static uint8_t fki_ccc(uint8_t cluster) {
switch(cluster) {
@ -131,7 +196,7 @@ static uint8_t fki_dma_adapter(uint8_t cluster) {
}
}
static uint64_t fki_addr_ccc_peMapping(uint8_t cluster) {
static inline uint32_t fki_addr_ccc_peMapping(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80006000;
@ -145,13 +210,13 @@ static uint64_t fki_addr_ccc_peMapping(uint8_t cluster) {
}
}
static uint64_t fki_addr_sram1(uint8_t cluster) {
static inline uint32_t fki_addr_sram1(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x9010c000;
return 0x90090000;
}
case 2: {
return 0x8010c000;
return 0x80090000;
}
default: {
return -1;
@ -159,13 +224,13 @@ static uint64_t fki_addr_sram1(uint8_t cluster) {
}
}
static uint64_t fki_addr_ccc_configMem(uint8_t cluster) {
static inline uint32_t fki_addr_sram2(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x90000000;
}
case 2: {
return 0x80000000;
return 0x800d0000;
}
case 3: {
return 0x900d0000;
}
default: {
return -1;
@ -173,133 +238,7 @@ static uint64_t fki_addr_ccc_configMem(uint8_t cluster) {
}
}
static uint64_t fki_addr_sram2(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x8018c000;
}
case 3: {
return 0x9018c000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_cntrl_cva5(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80009000;
}
case 3: {
return 0x90009000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_cntrl_tgc(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x8000a000;
}
case 3: {
return 0x9000a000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_ccc_idxTasks(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80005000;
}
case 3: {
return 0x90005000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_ccc_idxJobs(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80004000;
}
case 3: {
return 0x90004000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_aes_adapter(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80007000;
}
case 3: {
return 0x90007000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_ut_adapter(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x9000b000;
}
case 2: {
return 0x8000b000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_sram0(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x8000c000;
}
case 3: {
return 0x9000c000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_sram3(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x8020c000;
}
case 3: {
return 0x9020c000;
}
default: {
return -1;
}
}
}
static uint64_t fki_addr_hide_adapter(uint8_t cluster) {
static inline uint32_t fki_addr_cntrl_cva5(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80008000;
@ -313,4 +252,158 @@ static uint64_t fki_addr_hide_adapter(uint8_t cluster) {
}
}
static inline uint32_t fki_addr_cntrl_tgc(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x8000b000;
}
case 3: {
return 0x9000b000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80005000;
}
case 3: {
return 0x90005000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_cacheFlushControl(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x9000f000;
}
case 2: {
return 0x8000f000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x8000d000;
}
case 2: {
return 0x8000d000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_ccc_idxJobs(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80004000;
}
case 3: {
return 0x90004000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x8000a000;
}
case 3: {
return 0x8000a000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_ccc_configMem(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x90000000;
}
case 2: {
return 0x80000000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_aes_adapter(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80007000;
}
case 3: {
return 0x90007000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_ut_adapter(uint8_t cluster) {
switch(cluster) {
case 3: {
return 0x9000e000;
}
case 2: {
return 0x8000e000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_sram0(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80010000;
}
case 3: {
return 0x90010000;
}
default: {
return -1;
}
}
}
static inline uint32_t fki_addr_sram3(uint8_t cluster) {
switch(cluster) {
case 2: {
return 0x80110000;
}
case 3: {
return 0x90110000;
}
default: {
return -1;
}
}
}
#endif //_FKI_CLUSTER_INFO_H

21
include/ehrenberg/devices/flexki_messages.h
View File

@ -36,6 +36,27 @@ static void send_msg(uint32_t cluster, uint32_t component, uint32_t msg_len, uin
case 7:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(msgif, words[i]);
break;
case 8:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(msgif, words[i]);
break;
case 9:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(msgif, words[i]);
break;
case 10:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(msgif, words[i]);
break;
case 11:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(msgif, words[i]);
break;
case 12:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(msgif, words[i]);
break;
case 13:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(msgif, words[i]);
break;
case 14:
set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(msgif, words[i]);
break;
default:
break;
}

40
include/ehrenberg/devices/gen/aclint.h
View File

@ -43,48 +43,32 @@ typedef struct {
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
// ACLINT_MSIP0
inline uint32_t get_aclint_msip0(volatile aclint_t* reg){
return reg->MSIP0;
}
inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value){
reg->MSIP0 = value;
}
inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg){
return (reg->MSIP0 >> 0) & 0x1;
}
inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value){
reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP0; }
static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP0 = value; }
static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP0 >> 0) & 0x1; }
static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) { reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); }
// ACLINT_MTIMECMP0LO
inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg){
return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
}
inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value){
static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0HI
inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg){
return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
}
inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value){
static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_LO
inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg){
return (reg->MTIME_LO >> 0) & 0xffffffff;
}
inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value){
static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_HI
inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg){
return (reg->MTIME_HI >> 0) & 0xffffffff;
}
inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value){
static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
}

280
include/ehrenberg/devices/gen/apb3spi.h
View File

@ -158,273 +158,153 @@ typedef struct {
#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
// APB3SPI_DATA
inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg){
return reg->DATA;
}
inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value){
reg->DATA = value;
}
inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg){
return (reg->DATA >> 8) & 0x1;
}
inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg){
return (reg->DATA >> 9) & 0x1;
}
inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg){
return (reg->DATA >> 11) & 0x1;
}
inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg) { return reg->DATA; }
static inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value) { reg->DATA = value; }
static inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); }
static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg) { return (reg->DATA >> 8) & 0x1; }
static inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); }
static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg) { return (reg->DATA >> 9) & 0x1; }
static inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); }
static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg) { return (reg->DATA >> 11) & 0x1; }
static inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value) {
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
}
inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){
return (reg->DATA >> 31) & 0x1;
}
static inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg) { return (reg->DATA >> 31) & 0x1; }
// APB3SPI_STATUS
inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg){
return reg->STATUS;
}
inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg){
return (reg->STATUS >> 0) & 0x3f;
}
inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg){
return (reg->STATUS >> 16) & 0x3f;
}
static inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg) { return reg->STATUS; }
static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg) { return (reg->STATUS >> 0) & 0x3f; }
static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg) { return (reg->STATUS >> 16) & 0x3f; }
// APB3SPI_CONFIG
inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg){
return reg->CONFIG;
}
inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value){
reg->CONFIG = value;
}
inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg){
return (reg->CONFIG >> 0) & 0x3;
}
inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg) { return reg->CONFIG; }
static inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value) { reg->CONFIG = value; }
static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
static inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg){
return (reg->CONFIG >> 4) & 0x3;
}
inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
static inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
}
// APB3SPI_INTR
inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg){
return reg->INTR;
}
inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value){
reg->INTR = value;
}
inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg){
return (reg->INTR >> 0) & 0x1;
}
inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg){
return (reg->INTR >> 1) & 0x1;
}
inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg){
return (reg->INTR >> 8) & 0x1;
}
inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg){
return (reg->INTR >> 9) & 0x1;
}
inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){
return (reg->INTR >> 16) & 0x1;
}
static inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg) { return reg->INTR; }
static inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value) { reg->INTR = value; }
static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 0) & 0x1; }
static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); }
static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 1) & 0x1; }
static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); }
static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 8) & 0x1; }
static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8); }
static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 9) & 0x1; }
static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9); }
static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg) { return (reg->INTR >> 16) & 0x1; }
// APB3SPI_SCLK_CONFIG
inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg){
return reg->SCLK_CONFIG;
}
inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value){
reg->SCLK_CONFIG = value;
}
inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg){
return (reg->SCLK_CONFIG >> 0) & 0xfff;
}
inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value){
static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg) { return reg->SCLK_CONFIG; }
static inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value) { reg->SCLK_CONFIG = value; }
static inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg) { return (reg->SCLK_CONFIG >> 0) & 0xfff; }
static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value) {
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_SETUP
inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg){
return reg->SSGEN_SETUP;
}
inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_SETUP = value;
}
inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_SETUP >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value){
static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg) { return reg->SSGEN_SETUP; }
static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_SETUP = value; }
static inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_SETUP >> 0) & 0xfff; }
static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_HOLD
inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg){
return reg->SSGEN_HOLD;
}
inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_HOLD = value;
}
inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_HOLD >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value){
static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg) { return reg->SSGEN_HOLD; }
static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_HOLD = value; }
static inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_HOLD >> 0) & 0xfff; }
static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_DISABLE
inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg){
return reg->SSGEN_DISABLE;
}
inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_DISABLE = value;
}
inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_DISABLE >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value){
static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg) { return reg->SSGEN_DISABLE; }
static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_DISABLE = value; }
static inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_DISABLE >> 0) & 0xfff; }
static inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
}
// APB3SPI_SSGEN_ACTIVE_HIGH
inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){
return reg->SSGEN_ACTIVE_HIGH;
}
inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_ACTIVE_HIGH = value;
}
inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg){
static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg) { return reg->SSGEN_ACTIVE_HIGH; }
static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_ACTIVE_HIGH = value; }
static inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg) {
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
}
inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value){
static inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value) {
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
}
// APB3SPI_XIP_ENABLE
inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg){
return reg->XIP_ENABLE;
}
inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_ENABLE = value;
}
inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg){
return (reg->XIP_ENABLE >> 0) & 0x1;
}
inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg) { return reg->XIP_ENABLE; }
static inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_ENABLE = value; }
static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg) { return (reg->XIP_ENABLE >> 0) & 0x1; }
static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
}
// APB3SPI_XIP_CONFIG
inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg){
return reg->XIP_CONFIG;
}
inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_CONFIG = value;
}
inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 0) & 0xff;
}
inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg) { return reg->XIP_CONFIG; }
static inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_CONFIG = value; }
static inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 0) & 0xff; }
static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 8) & 0x1;
}
inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 8) & 0x1; }
static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 16) & 0xff;
}
inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 16) & 0xff; }
static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
}
inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 24) & 0xf;
}
inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 24) & 0xf; }
static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
}
// APB3SPI_XIP_MODE
inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg){
return reg->XIP_MODE;
}
inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_MODE = value;
}
inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 0) & 0x3;
}
inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg) { return reg->XIP_MODE; }
static inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_MODE = value; }
static inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 0) & 0x3; }
static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 8) & 0x3;
}
inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 8) & 0x3; }
static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 16) & 0x3;
}
inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 16) & 0x3; }
static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
}
inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 24) & 0x3;
}
inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value){
static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 24) & 0x3; }
static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
}
// APB3SPI_XIP_WRITE
inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_WRITE = value;
}
inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value){
static inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_WRITE = value; }
static inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
}
// APB3SPI_XIP_READ_WRITE
inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_READ_WRITE = value;
}
inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value){
static inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_READ_WRITE = value; }
static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
}
// APB3SPI_XIP_READ
inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg){
return reg->XIP_READ;
}
inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg){
return (reg->XIP_READ >> 0) & 0xff;
}
static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg) { return reg->XIP_READ; }
static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg) { return (reg->XIP_READ >> 0) & 0xff; }
#endif /* _BSP_APB3SPI_H */

208
include/ehrenberg/devices/gen/camera.h
View File

@ -125,212 +125,132 @@ typedef struct {
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
// CAMERA_PIXEL
inline uint32_t get_camera_pixel(volatile camera_t* reg){
return (reg->PIXEL >> 0) & 0xffffffff;
}
inline void set_camera_pixel(volatile camera_t* reg, uint32_t value){
static inline uint32_t get_camera_pixel(volatile camera_t* reg) { return (reg->PIXEL >> 0) & 0xffffffff; }
static inline void set_camera_pixel(volatile camera_t* reg, uint32_t value) {
reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
}
// CAMERA_CONFIG
inline uint32_t get_camera_config(volatile camera_t* reg){
return reg->CONFIG;
}
inline void set_camera_config(volatile camera_t* reg, uint32_t value){
reg->CONFIG = value;
}
inline uint32_t get_camera_config_output_curr(volatile camera_t* reg){
return (reg->CONFIG >> 0) & 0x3;
}
inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config(volatile camera_t* reg) { return reg->CONFIG; }
static inline void set_camera_config(volatile camera_t* reg, uint32_t value) { reg->CONFIG = value; }
static inline uint32_t get_camera_config_output_curr(volatile camera_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
static inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg){
return (reg->CONFIG >> 2) & 0x3;
}
inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg) { return (reg->CONFIG >> 2) & 0x3; }
static inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
}
inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg){
return (reg->CONFIG >> 4) & 0x3;
}
inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
static inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
}
inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg){
return (reg->CONFIG >> 6) & 0x3;
}
inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg) { return (reg->CONFIG >> 6) & 0x3; }
static inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
}
inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg){
return (reg->CONFIG >> 8) & 0xff;
}
inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg) { return (reg->CONFIG >> 8) & 0xff; }
static inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
}
inline uint32_t get_camera_config_high_speed(volatile camera_t* reg){
return (reg->CONFIG >> 16) & 0x1;
}
inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_high_speed(volatile camera_t* reg) { return (reg->CONFIG >> 16) & 0x1; }
static inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
}
inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg){
return (reg->CONFIG >> 17) & 0x1;
}
inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg) { return (reg->CONFIG >> 17) & 0x1; }
static inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
}
inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg){
return (reg->CONFIG >> 18) & 0x3;
}
inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg) { return (reg->CONFIG >> 18) & 0x3; }
static inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
}
inline uint32_t get_camera_config_vref(volatile camera_t* reg){
return (reg->CONFIG >> 20) & 0x3;
}
inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_vref(volatile camera_t* reg) { return (reg->CONFIG >> 20) & 0x3; }
static inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
}
inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg){
return (reg->CONFIG >> 22) & 0x3;
}
inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg) { return (reg->CONFIG >> 22) & 0x3; }
static inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
}
inline uint32_t get_camera_config_output_mode(volatile camera_t* reg){
return (reg->CONFIG >> 24) & 0x1;
}
inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_output_mode(volatile camera_t* reg) { return (reg->CONFIG >> 24) & 0x1; }
static inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
}
inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg){
return (reg->CONFIG >> 25) & 0x1;
}
inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg) { return (reg->CONFIG >> 25) & 0x1; }
static inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
}
inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg){
return (reg->CONFIG >> 26) & 0x1;
}
inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg) { return (reg->CONFIG >> 26) & 0x1; }
static inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
}
inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg){
return (reg->CONFIG >> 27) & 0x1f;
}
inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg) { return (reg->CONFIG >> 27) & 0x1f; }
static inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
}
// CAMERA_CONFIG2
inline uint32_t get_camera_config2(volatile camera_t* reg){
return reg->CONFIG2;
}
inline void set_camera_config2(volatile camera_t* reg, uint32_t value){
reg->CONFIG2 = value;
}
inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg){
return (reg->CONFIG2 >> 0) & 0x1;
}
inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config2(volatile camera_t* reg) { return reg->CONFIG2; }
static inline void set_camera_config2(volatile camera_t* reg, uint32_t value) { reg->CONFIG2 = value; }
static inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg) { return (reg->CONFIG2 >> 0) & 0x1; }
static inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value) {
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg){
return (reg->CONFIG2 >> 1) & 0x1;
}
inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg) { return (reg->CONFIG2 >> 1) & 0x1; }
static inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value) {
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
}
// CAMERA_DATA_SIZE
inline uint32_t get_camera_data_size(volatile camera_t* reg){
return reg->DATA_SIZE;
}
inline void set_camera_data_size(volatile camera_t* reg, uint32_t value){
reg->DATA_SIZE = value;
}
inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg){
return (reg->DATA_SIZE >> 0) & 0x3;
}
inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_data_size(volatile camera_t* reg) { return reg->DATA_SIZE; }
static inline void set_camera_data_size(volatile camera_t* reg, uint32_t value) { reg->DATA_SIZE = value; }
static inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg) { return (reg->DATA_SIZE >> 0) & 0x3; }
static inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value) {
reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
}
// CAMERA_START
inline uint32_t get_camera_start(volatile camera_t* reg){
return reg->START;
}
inline void set_camera_start(volatile camera_t* reg, uint32_t value){
reg->START = value;
}
inline uint32_t get_camera_start_start(volatile camera_t* reg){
return (reg->START >> 0) & 0x1;
}
inline void set_camera_start_start(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_start(volatile camera_t* reg) { return reg->START; }
static inline void set_camera_start(volatile camera_t* reg, uint32_t value) { reg->START = value; }
static inline uint32_t get_camera_start_start(volatile camera_t* reg) { return (reg->START >> 0) & 0x1; }
static inline void set_camera_start_start(volatile camera_t* reg, uint8_t value) {
reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
}
// CAMERA_STATUS
inline uint32_t get_camera_status(volatile camera_t* reg){
return reg->STATUS;
}
inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
static inline uint32_t get_camera_status(volatile camera_t* reg) { return reg->STATUS; }
static inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg) { return (reg->STATUS >> 0) & 0x1; }
// CAMERA_CAMERA_CLOCK_CTRL
inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg){
return reg->CAMERA_CLOCK_CTRL;
}
inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value){
reg->CAMERA_CLOCK_CTRL = value;
}
inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg){
return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff;
}
inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value){
static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg) { return reg->CAMERA_CLOCK_CTRL; }
static inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value) { reg->CAMERA_CLOCK_CTRL = value; }
static inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg) { return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff; }
static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value) {
reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
}
// CAMERA_IE
inline uint32_t get_camera_ie(volatile camera_t* reg){
return reg->IE;
}
inline void set_camera_ie(volatile camera_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_ie(volatile camera_t* reg) { return reg->IE; }
static inline void set_camera_ie(volatile camera_t* reg, uint32_t value) { reg->IE = value; }
static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg) { return (reg->IE >> 1) & 0x1; }
static inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
// CAMERA_IP
inline uint32_t get_camera_ip(volatile camera_t* reg){
return reg->IP;
}
inline void set_camera_ip(volatile camera_t* reg, uint32_t value){
reg->IP = value;
}
inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_ip(volatile camera_t* reg) { return reg->IP; }
static inline void set_camera_ip(volatile camera_t* reg, uint32_t value) { reg->IP = value; }
static inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg) { return (reg->IP >> 0) & 0x1; }
static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value) {
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg){
return (reg->IP >> 1) & 0x1;
}
inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value){
static inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg) { return (reg->IP >> 1) & 0x1; }
static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value) {
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
}

280
include/ehrenberg/devices/gen/dma.h
View File

@ -168,286 +168,174 @@ typedef struct {
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
// DMA_CONTROL
inline uint32_t get_dma_control(volatile dma_t* reg){
return reg->CONTROL;
}
inline void set_dma_control(volatile dma_t* reg, uint32_t value){
reg->CONTROL = value;
}
inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg){
return (reg->CONTROL >> 0) & 0x1;
}
inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_control(volatile dma_t* reg) { return reg->CONTROL; }
static inline void set_dma_control(volatile dma_t* reg, uint32_t value) { reg->CONTROL = value; }
static inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 0) & 0x1; }
static inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg){
return (reg->CONTROL >> 1) & 0x1;
}
inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 1) & 0x1; }
static inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
}
// DMA_STATUS
inline uint32_t get_dma_status(volatile dma_t* reg){
return reg->STATUS;
}
inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
static inline uint32_t get_dma_status(volatile dma_t* reg) { return reg->STATUS; }
static inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg) { return (reg->STATUS >> 0) & 0x1; }
static inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg) { return (reg->STATUS >> 1) & 0x1; }
// DMA_IE
inline uint32_t get_dma_ie(volatile dma_t* reg){
return reg->IE;
}
inline void set_dma_ie(volatile dma_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_ie(volatile dma_t* reg) { return reg->IE; }
static inline void set_dma_ie(volatile dma_t* reg, uint32_t value) { reg->IE = value; }
static inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 1) & 0x1; }
static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg){
return (reg->IE >> 2) & 0x1;
}
inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 2) & 0x1; }
static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg){
return (reg->IE >> 3) & 0x1;
}
inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 3) & 0x1; }
static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
}
// DMA_IP
inline uint32_t get_dma_ip(volatile dma_t* reg){
return reg->IP;
}
inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg){
return (reg->IP >> 1) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg){
return (reg->IP >> 2) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg){
return (reg->IP >> 3) & 0x1;
}
static inline uint32_t get_dma_ip(volatile dma_t* reg) { return reg->IP; }
static inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 0) & 0x1; }
static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 1) & 0x1; }
static inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 2) & 0x1; }
static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 3) & 0x1; }
// DMA_CH0_EVENT
inline uint32_t get_dma_ch0_event(volatile dma_t* reg){
return reg->CH0_EVENT;
}
inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value){
reg->CH0_EVENT = value;
}
inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg){
return (reg->CH0_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_ch0_event(volatile dma_t* reg) { return reg->CH0_EVENT; }
static inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value) { reg->CH0_EVENT = value; }
static inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg) { return (reg->CH0_EVENT >> 0) & 0x1f; }
static inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value) {
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg){
return (reg->CH0_EVENT >> 31) & 0x1;
}
inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg) { return (reg->CH0_EVENT >> 31) & 0x1; }
static inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value) {
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
}
// DMA_CH0_TRANSFER
inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg){
return reg->CH0_TRANSFER;
}
inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value){
reg->CH0_TRANSFER = value;
}
inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg) { return reg->CH0_TRANSFER; }
static inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value) { reg->CH0_TRANSFER = value; }
static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 0) & 0x3; }
static inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 2) & 0x3ff;
}
inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value){
static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 2) & 0x3ff; }
static inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 12) & 0xfffff;
}
inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value){
static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 12) & 0xfffff; }
static inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH0_SRC_START_ADDR
inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg){
return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value){
static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg) { return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH0_SRC_ADDR_INC
inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg){
return reg->CH0_SRC_ADDR_INC;
}
inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_ADDR_INC = value;
}
inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg){
return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg) { return reg->CH0_SRC_ADDR_INC; }
static inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_SRC_ADDR_INC = value; }
static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg){
return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
static inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH0_DST_START_ADDR
inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg){
return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value){
static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg) { return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH0_DST_ADDR_INC
inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg){
return reg->CH0_DST_ADDR_INC;
}
inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH0_DST_ADDR_INC = value;
}
inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg){
return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg) { return reg->CH0_DST_ADDR_INC; }
static inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_DST_ADDR_INC = value; }
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg){
return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_EVENT
inline uint32_t get_dma_ch1_event(volatile dma_t* reg){
return reg->CH1_EVENT;
}
inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value){
reg->CH1_EVENT = value;
}
inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg){
return (reg->CH1_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_ch1_event(volatile dma_t* reg) { return reg->CH1_EVENT; }
static inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value) { reg->CH1_EVENT = value; }
static inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg) { return (reg->CH1_EVENT >> 0) & 0x1f; }
static inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value) {
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg){
return (reg->CH1_EVENT >> 31) & 0x1;
}
inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg) { return (reg->CH1_EVENT >> 31) & 0x1; }
static inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value) {
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
}
// DMA_CH1_TRANSFER
inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg){
return reg->CH1_TRANSFER;
}
inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value){
reg->CH1_TRANSFER = value;
}
inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value){
static inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg) { return reg->CH1_TRANSFER; }
static inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value) { reg->CH1_TRANSFER = value; }
static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 0) & 0x3; }
static inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 2) & 0x3ff;
}
inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value){
static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 2) & 0x3ff; }
static inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 12) & 0xfffff;
}
inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value){
static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 12) & 0xfffff; }
static inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_SRC_START_ADDR
inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg){
return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value){
static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg) { return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH1_SRC_ADDR_INC
inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg){
return reg->CH1_SRC_ADDR_INC;
}
inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg){
return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg) { return reg->CH1_SRC_ADDR_INC; }
static inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_SRC_ADDR_INC = value; }
static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg){
return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
static inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
// DMA_CH1_DST_START_ADDR
inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg){
return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value){
static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg) { return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff; }
static inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value) {
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
// DMA_CH1_DST_ADDR_INC
inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg){
return reg->CH1_DST_ADDR_INC;
}
inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg){
return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg) { return reg->CH1_DST_ADDR_INC; }
static inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_DST_ADDR_INC = value; }
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg){
return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff; }
static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}

290
include/ehrenberg/devices/gen/gpio.h
View File

@ -198,304 +198,196 @@ typedef struct {
#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
// GPIO_VALUE
inline uint32_t get_gpio_value(volatile gpio_t* reg){
return (reg->VALUE >> 0) & 0xffffffff;
}
static inline uint32_t get_gpio_value(volatile gpio_t* reg) { return (reg->VALUE >> 0) & 0xffffffff; }
// GPIO_WRITE
inline uint32_t get_gpio_write(volatile gpio_t* reg){
return (reg->WRITE >> 0) & 0xffffffff;
}
inline void set_gpio_write(volatile gpio_t* reg, uint32_t value){
reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
}
static inline uint32_t get_gpio_write(volatile gpio_t* reg) { return (reg->WRITE >> 0) & 0xffffffff; }
static inline void set_gpio_write(volatile gpio_t* reg, uint32_t value) { reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); }
// GPIO_WRITEENABLE
inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg){
return (reg->WRITEENABLE >> 0) & 0xffffffff;
}
inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
static inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg) { return (reg->WRITEENABLE >> 0) & 0xffffffff; }
static inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value) {
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_PULLUP
inline uint32_t get_gpio_pullup(volatile gpio_t* reg){
return (reg->PULLUP >> 0) & 0xffffffff;
}
inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value){
static inline uint32_t get_gpio_pullup(volatile gpio_t* reg) { return (reg->PULLUP >> 0) & 0xffffffff; }
static inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value) {
reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_PULDOWN
inline uint32_t get_gpio_puldown(volatile gpio_t* reg){
return (reg->PULDOWN >> 0) & 0xffffffff;
}
inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value){
static inline uint32_t get_gpio_puldown(volatile gpio_t* reg) { return (reg->PULDOWN >> 0) & 0xffffffff; }
static inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value) {
reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_DRIVESTRENGTH_0
inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg){
return reg->DRIVESTRENGTH_0;
}
inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value){
reg->DRIVESTRENGTH_0 = value;
}
inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 0) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_0; }
static inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_0 = value; }
static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 4) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
}
inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 8) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
}
inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 12) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
}
inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 16) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
}
inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 20) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
}
inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 24) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
}
inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 28) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_DRIVESTRENGTH_1
inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg){
return reg->DRIVESTRENGTH_1;
}
inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value){
reg->DRIVESTRENGTH_1 = value;
}
inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 0) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_1; }
static inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_1 = value; }
static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 4) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
}
inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 8) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
}
inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 12) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
}
inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 16) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
}
inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 20) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
}
inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 24) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
}
inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 28) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_DRIVESTRENGTH_2
inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg){
return reg->DRIVESTRENGTH_2;
}
inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value){
reg->DRIVESTRENGTH_2 = value;
}
inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 0) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_2; }
static inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_2 = value; }
static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 4) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
}
inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 8) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
}
inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 12) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
}
inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 16) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
}
inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 20) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
}
inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 24) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
}
inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 28) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_DRIVESTRENGTH_3
inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg){
return reg->DRIVESTRENGTH_3;
}
inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value){
reg->DRIVESTRENGTH_3 = value;
}
inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 0) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_3; }
static inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_3 = value; }
static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 4) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 4) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
}
inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 8) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
}
inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 12) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
}
inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 16) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
}
inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 20) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
}
inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 24) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
}
inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 28) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value){
static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
}
// GPIO_IE
inline uint32_t get_gpio_ie(volatile gpio_t* reg){
return (reg->IE >> 0) & 0xffffffff;
}
inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value){
reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0);
}
static inline uint32_t get_gpio_ie(volatile gpio_t* reg) { return (reg->IE >> 0) & 0xffffffff; }
static inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value) { reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0); }
// GPIO_IP
inline uint32_t get_gpio_ip(volatile gpio_t* reg){
return (reg->IP >> 0) & 0xffffffff;
}
inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value){
reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0);
}
static inline uint32_t get_gpio_ip(volatile gpio_t* reg) { return (reg->IP >> 0) & 0xffffffff; }
static inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value) { reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0); }
// GPIO_IRQ_TRIGGER
inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg){
return (reg->IRQ_TRIGGER >> 0) & 0xffffffff;
}
inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value){
static inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg) { return (reg->IRQ_TRIGGER >> 0) & 0xffffffff; }
static inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value) {
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_IRQ_TYPE
inline uint32_t get_gpio_irq_type(volatile gpio_t* reg){
return (reg->IRQ_TYPE >> 0) & 0xffffffff;
}
inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value){
static inline uint32_t get_gpio_irq_type(volatile gpio_t* reg) { return (reg->IRQ_TYPE >> 0) & 0xffffffff; }
static inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value) {
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_BOOT_SEL
inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg){
return reg->BOOT_SEL;
}
inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg){
return (reg->BOOT_SEL >> 0) & 0x7;
}
static inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg) { return reg->BOOT_SEL; }
static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg) { return (reg->BOOT_SEL >> 0) & 0x7; }
#endif /* _BSP_GPIO_H */

164
include/ehrenberg/devices/gen/i2s.h
View File

@ -109,162 +109,92 @@ typedef struct {
#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
// I2S_LEFT_CH
inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){
return (reg->LEFT_CH >> 0) & 0xffffffff;
}
static inline uint32_t get_i2s_left_ch(volatile i2s_t* reg) { return (reg->LEFT_CH >> 0) & 0xffffffff; }
// I2S_RIGHT_CH
inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){
return (reg->RIGHT_CH >> 0) & 0xffffffff;
}
static inline uint32_t get_i2s_right_ch(volatile i2s_t* reg) { return (reg->RIGHT_CH >> 0) & 0xffffffff; }
// I2S_CONTROL
inline uint32_t get_i2s_control(volatile i2s_t* reg){
return reg->CONTROL;
}
inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){
reg->CONTROL = value;
}
inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){
return (reg->CONTROL >> 0) & 0x3;
}
inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){
return (reg->CONTROL >> 2) & 0x1;
}
inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){
static inline uint32_t get_i2s_control(volatile i2s_t* reg) { return reg->CONTROL; }
static inline void set_i2s_control(volatile i2s_t* reg, uint32_t value) { reg->CONTROL = value; }
static inline uint32_t get_i2s_control_mode(volatile i2s_t* reg) { return (reg->CONTROL >> 0) & 0x3; }
static inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); }
static inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg) { return (reg->CONTROL >> 2) & 0x1; }
static inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){
return (reg->CONTROL >> 3) & 0x1;
}
inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
static inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg) { return (reg->CONTROL >> 3) & 0x1; }
static inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
}
inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg){
return (reg->CONTROL >> 4) & 0x1;
}
inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value){
static inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg) { return (reg->CONTROL >> 4) & 0x1; }
static inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
}
inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg){
return (reg->CONTROL >> 5) & 0x3;
}
inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value){
static inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg) { return (reg->CONTROL >> 5) & 0x3; }
static inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
}
inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){
return (reg->CONTROL >> 7) & 0x7;
}
inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg) { return (reg->CONTROL >> 7) & 0x7; }
static inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
}
// I2S_STATUS
inline uint32_t get_i2s_status(volatile i2s_t* reg){
return reg->STATUS;
}
inline void set_i2s_status(volatile i2s_t* reg, uint32_t value){
reg->STATUS = value;
}
inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
inline uint32_t get_i2s_status_active(volatile i2s_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
return (reg->STATUS >> 2) & 0x1;
}
inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
return (reg->STATUS >> 3) & 0x1;
}
inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg){
return (reg->STATUS >> 4) & 0x1;
}
inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value){
static inline uint32_t get_i2s_status(volatile i2s_t* reg) { return reg->STATUS; }
static inline void set_i2s_status(volatile i2s_t* reg, uint32_t value) { reg->STATUS = value; }
static inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg) { return (reg->STATUS >> 0) & 0x1; }
static inline uint32_t get_i2s_status_active(volatile i2s_t* reg) { return (reg->STATUS >> 1) & 0x1; }
static inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg) { return (reg->STATUS >> 2) & 0x1; }
static inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg) { return (reg->STATUS >> 3) & 0x1; }
static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 4) & 0x1; }
static inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value) {
reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
}
inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg){
return (reg->STATUS >> 5) & 0x1;
}
inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value){
static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 5) & 0x1; }
static inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value) {
reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
}
// I2S_I2S_CLOCK_CTRL
inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
return reg->I2S_CLOCK_CTRL;
}
inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){
reg->I2S_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
}
inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value){
static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg) { return reg->I2S_CLOCK_CTRL; }
static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->I2S_CLOCK_CTRL = value; }
static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; }
static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value) {
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
}
// I2S_PDM_CLOCK_CTRL
inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){
return reg->PDM_CLOCK_CTRL;
}
inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){
reg->PDM_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->PDM_CLOCK_CTRL >> 0) & 0xff;
}
inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value){
static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg) { return reg->PDM_CLOCK_CTRL; }
static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_CLOCK_CTRL = value; }
static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->PDM_CLOCK_CTRL >> 0) & 0xff; }
static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value) {
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
}
// I2S_PDM_FILTER_CTRL
inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg){
return reg->PDM_FILTER_CTRL;
}
inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value){
reg->PDM_FILTER_CTRL = value;
}
inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg){
return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff;
}
inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value){
static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg) { return reg->PDM_FILTER_CTRL; }
static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_FILTER_CTRL = value; }
static inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg) { return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff; }
static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value) {
reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
}
// I2S_IE
inline uint32_t get_i2s_ie(volatile i2s_t* reg){
return reg->IE;
}
inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){
static inline uint32_t get_i2s_ie(volatile i2s_t* reg) { return reg->IE; }
static inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value) { reg->IE = value; }
static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){
static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 1) & 0x1; }
static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
// I2S_IP
inline uint32_t get_i2s_ip(volatile i2s_t* reg){
return reg->IP;
}
inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){
return (reg->IP >> 1) & 0x1;
}
static inline uint32_t get_i2s_ip(volatile i2s_t* reg) { return reg->IP; }
static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 0) & 0x1; }
static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 1) & 0x1; }
#endif /* _BSP_I2S_H */

145
include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h
View File

@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2025-02-18 11:11:47 UTC
* Generated at 2025-05-05 14:06:05 UTC
* by peakrdl_mnrs version 1.2.9
*/
@ -27,19 +27,30 @@ typedef struct {
volatile uint32_t REG_PAYLOAD_5;
volatile uint32_t REG_PAYLOAD_6;
volatile uint32_t REG_PAYLOAD_7;
volatile uint32_t REG_PAYLOAD_8;
volatile uint32_t REG_PAYLOAD_9;
volatile uint32_t REG_PAYLOAD_10;
volatile uint32_t REG_PAYLOAD_11;
volatile uint32_t REG_PAYLOAD_12;
volatile uint32_t REG_PAYLOAD_13;
volatile uint32_t REG_PAYLOAD_14;
volatile uint32_t REG_PAYLOAD_15;
} mkcontrolclusterstreamcontroller_t;
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
@ -97,111 +108,183 @@ typedef struct {
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS)
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_SEND = value;
}
inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg){
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg) {
return reg->REG_HEADER;
}
inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_HEADER = value;
}
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 0) & 0xf;
}
inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
}
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg){
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 4) & 0xf;
}
inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
}
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg){
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 8) & 0x7;
}
inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
}
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg){
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 11) & 0x3;
}
inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg){
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg) {
return reg->REG_ACK;
}
inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_ACK = value;
}
inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg){
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_ACK >> 1) & 0x1;
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
return reg->REG_RECV_ID;
}
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_RECV_ID >> 0) & 0xf;
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg){
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_8 = (reg->REG_PAYLOAD_8 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_9 = (reg->REG_PAYLOAD_9 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_10 = (reg->REG_PAYLOAD_10 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_11 = (reg->REG_PAYLOAD_11 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_12 = (reg->REG_PAYLOAD_12 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_13 = (reg->REG_PAYLOAD_13 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_14 = (reg->REG_PAYLOAD_14 & ~(0xffffffffU << 0)) | (value << 0);
}
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_15(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_15 = (reg->REG_PAYLOAD_15 & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */

75
include/ehrenberg/devices/gen/msgif.h
View File

@ -43,7 +43,8 @@ typedef struct {
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \
((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
@ -94,103 +95,81 @@ typedef struct {
#define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
// MSGIF_REG_SEND
inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value){
reg->REG_SEND = value;
}
inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value){
static inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value) { reg->REG_SEND = value; }
static inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value) {
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
}
// MSGIF_REG_HEADER
inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg){
return reg->REG_HEADER;
}
inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value){
reg->REG_HEADER = value;
}
inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg){
return (reg->REG_HEADER >> 0) & 0xf;
}
inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value){
static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg) { return reg->REG_HEADER; }
static inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value) { reg->REG_HEADER = value; }
static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg) { return (reg->REG_HEADER >> 0) & 0xf; }
static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
}
inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg){
return (reg->REG_HEADER >> 4) & 0xf;
}
inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value){
static inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg) { return (reg->REG_HEADER >> 4) & 0xf; }
static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
}
inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg){
return (reg->REG_HEADER >> 8) & 0x7;
}
inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value){
static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg) { return (reg->REG_HEADER >> 8) & 0x7; }
static inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
}
inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg){
return (reg->REG_HEADER >> 11) & 0x3;
}
inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value){
static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg) { return (reg->REG_HEADER >> 11) & 0x3; }
static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
}
// MSGIF_REG_ACK
inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value){
reg->REG_ACK = value;
}
inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value){
static inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value) { reg->REG_ACK = value; }
static inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value) {
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
}
// MSGIF_REG_RECV_ID
inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg){
return reg->REG_RECV_ID;
}
inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg){
return (reg->REG_RECV_ID >> 0) & 0xf;
}
static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg) { return reg->REG_RECV_ID; }
static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg) { return (reg->REG_RECV_ID >> 0) & 0xf; }
// MSGIF_REG_RECV_PAYLOAD
inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg){
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
}
static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg) { return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; }
// MSGIF_REG_PAYLOAD_0
inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value){
static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_1
inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value){
static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_2
inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value){
static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_3
inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value){
static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_4
inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value){
static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_5
inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value){
static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_6
inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value){
static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
}
// MSGIF_REG_PAYLOAD_7
inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value){
static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
}

22
include/ehrenberg/devices/gen/sysctrl.h
View File

@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2025-02-19 17:15:41 UTC
* Generated at 2025-06-23 15:39:49 UTC
* by peakrdl_mnrs version 1.2.9
*/
@ -16,6 +16,7 @@ typedef struct {
volatile uint32_t SYSCTRL;
volatile uint32_t PLLCTRL;
volatile uint32_t AXI_BACKUP;
volatile uint32_t FMCDIV;
}sysctrl_t;
#define SYSCTRL_SYSCTRL_CC0_RESET_OFFS 0
@ -50,6 +51,14 @@ typedef struct {
#define SYSCTRL_AXI_BACKUP_MASK 0x1f
#define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS)
#define SYSCTRL_FMCDIV_FMCDIVVALID_OFFS 0
#define SYSCTRL_FMCDIV_FMCDIVVALID_MASK 0x1
#define SYSCTRL_FMCDIV_FMCDIVVALID(V) ((V & SYSCTRL_FMCDIV_FMCDIVVALID_MASK) << SYSCTRL_FMCDIV_FMCDIVVALID_OFFS)
#define SYSCTRL_FMCDIV_FMCDIVFACTOR_OFFS 1
#define SYSCTRL_FMCDIV_FMCDIVFACTOR_MASK 0xf
#define SYSCTRL_FMCDIV_FMCDIVFACTOR(V) ((V & SYSCTRL_FMCDIV_FMCDIVFACTOR_MASK) << SYSCTRL_FMCDIV_FMCDIVFACTOR_OFFS)
//SYSCTRL_SYSCTRL
inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){
return reg->SYSCTRL;
@ -119,4 +128,15 @@ inline void set_sysctrl_axi_backup_page(volatile sysctrl_t* reg, uint8_t value){
reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0x1fU << 0)) | (value << 0);
}
//SYSCTRL_FMCDIV
inline void set_sysctrl_fmcdiv(volatile sysctrl_t* reg, uint32_t value){
reg->FMCDIV = value;
}
inline void set_sysctrl_fmcdiv_fmcDivValid(volatile sysctrl_t* reg, uint8_t value){
reg->FMCDIV = (reg->FMCDIV & ~(0x1U << 0)) | (value << 0);
}
inline void set_sysctrl_fmcdiv_fmcDivFactor(volatile sysctrl_t* reg, uint8_t value){
reg->FMCDIV = (reg->FMCDIV & ~(0xfU << 1)) | (value << 1);
}
#endif /* _BSP_SYSCTRL_H */

74
include/ehrenberg/devices/gen/timercounter.h
View File

@ -59,83 +59,53 @@ typedef struct {
#define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
// TIMERCOUNTER_PRESCALER
inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){
return reg->PRESCALER;
}
inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value){
reg->PRESCALER = value;
}
inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg){
return (reg->PRESCALER >> 0) & 0xffff;
}
inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value){
static inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg) { return reg->PRESCALER; }
static inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value) { reg->PRESCALER = value; }
static inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg) { return (reg->PRESCALER >> 0) & 0xffff; }
static inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value) {
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T0_CTRL
inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg){
return reg->T0_CTRL;
}
inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value){
reg->T0_CTRL = value;
}
inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg){
return (reg->T0_CTRL >> 0) & 0x7;
}
inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg) { return reg->T0_CTRL; }
static inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T0_CTRL = value; }
static inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 0) & 0x7; }
static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg){
return (reg->T0_CTRL >> 3) & 0x3;
}
inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
static inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 3) & 0x3; }
static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
}
// TIMERCOUNTER_T0_OVERFLOW
inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg){
return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value){
static inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg) { return (reg->T0_OVERFLOW >> 0) & 0xffffffff; }
static inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value) {
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T0_COUNTER
inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg){
return (reg->T0_COUNTER >> 0) & 0xffffffff;
}
static inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg) { return (reg->T0_COUNTER >> 0) & 0xffffffff; }
// TIMERCOUNTER_T1_CTRL
inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg){
return reg->T1_CTRL;
}
inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value){
reg->T1_CTRL = value;
}
inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg){
return (reg->T1_CTRL >> 0) & 0x7;
}
inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg) { return reg->T1_CTRL; }
static inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T1_CTRL = value; }
static inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 0) & 0x7; }
static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg){
return (reg->T1_CTRL >> 3) & 0x3;
}
inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
static inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 3) & 0x3; }
static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
}
// TIMERCOUNTER_T1_OVERFLOW
inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg){
return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value){
static inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg) { return (reg->T1_OVERFLOW >> 0) & 0xffffffff; }
static inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value) {
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
// TIMERCOUNTER_T1_COUNTER
inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg){
return (reg->T1_COUNTER >> 0) & 0xffffffff;
}
static inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg) { return (reg->T1_COUNTER >> 0) & 0xffffffff; }
#endif /* _BSP_TIMERCOUNTER_H */

142
include/ehrenberg/devices/gen/uart.h
View File

@ -101,135 +101,75 @@ typedef struct {
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
// UART_RX_TX_REG
inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){
return reg->RX_TX_REG;
}
inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){
reg->RX_TX_REG = value;
}
inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
return (reg->RX_TX_REG >> 0) & 0xff;
}
inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; }
static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; }
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
return (reg->RX_TX_REG >> 14) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
return (reg->RX_TX_REG >> 15) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
return (reg->RX_TX_REG >> 16) & 0x1;
}
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
// UART_INT_CTRL_REG
inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
return reg->INT_CTRL_REG;
}
inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){
reg->INT_CTRL_REG = value;
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 0) & 0x1;
}
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 1) & 0x1;
}
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){
static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; }
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 2) & 0x1;
}
inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){
static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; }
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 8) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 9) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 10) & 0x1;
}
static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
// UART_CLK_DIVIDER_REG
inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
return reg->CLK_DIVIDER_REG;
}
inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
reg->CLK_DIVIDER_REG = value;
}
inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg){
return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
}
inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value){
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
}
// UART_FRAME_CONFIG_REG
inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){
return reg->FRAME_CONFIG_REG;
}
inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){
reg->FRAME_CONFIG_REG = value;
}
inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
}
inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value){
static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; }
static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; }
static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
}
inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; }
static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
}
inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){
static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; }
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
// UART_STATUS_REG
inline uint32_t get_uart_status_reg(volatile uart_t* reg){
return reg->STATUS_REG;
}
inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){
reg->STATUS_REG = value;
}
inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
return (reg->STATUS_REG >> 0) & 0x1;
}
inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
return (reg->STATUS_REG >> 1) & 0x1;
}
inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
return (reg->STATUS_REG >> 8) & 0x1;
}
inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
return (reg->STATUS_REG >> 9) & 0x1;
}
inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; }
static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; }
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){
return (reg->STATUS_REG >> 10) & 0x1;
}
inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; }
static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
}
inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){
return (reg->STATUS_REG >> 11) & 0x1;
}
inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; }
static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
}

3
include/ehrenberg/devices/gpio.h
View File

@ -2,9 +2,10 @@
#define _DEVICES_GPIO_H
#include <stdint.h>
#include "gen/gpio.h"
inline void gpio_init(volatile gpio_t* reg) {
static inline void gpio_init(volatile gpio_t* reg) {
set_gpio_write(reg, 0);
set_gpio_writeEnable(reg, 0);
}

3
include/ehrenberg/devices/interrupt.h
View File

@ -5,7 +5,6 @@
#define irq_t void*
inline void irq_init(volatile irq_t* reg){
}
static inline void irq_init(volatile irq_t* reg) {}
#endif /* _DEVICES_INTERRUPT_H */

30
include/ehrenberg/devices/qspi.h
View File

@ -1,8 +1,8 @@
#ifndef _DEVICES_QSPI_H
#define _DEVICES_QSPI_H
#include <stdint.h>
#include "gen/apb3spi.h"
#include <stdint.h>
#define qspi_t apb3spi_t
typedef struct {
@ -27,7 +27,8 @@ typedef struct {
#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
static inline void spi_configure(volatile qspi_t *qspi, spi_cfg *config) {
set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4));
set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) |
(config->mode << 4));
set_apb3spi_sclk_config(qspi, config->clkDivider);
set_apb3spi_ssgen_setup(qspi, config->ssSetup);
set_apb3spi_ssgen_hold(qspi, config->ssHold);
@ -54,29 +55,36 @@ static inline uint32_t spi_rsp_occupied(volatile qspi_t* qspi){
}
static inline void spi_write(volatile qspi_t *qspi, uint8_t data) {
while(spi_cmd_avail(qspi) == 0);
while (spi_cmd_avail(qspi) == 0)
;
qspi->DATA = data | SPI_CMD_WRITE;
}
static inline uint8_t spi_read(volatile qspi_t *qspi) {
while(spi_cmd_avail(qspi) == 0);
while (spi_cmd_avail(qspi) == 0)
;
qspi->DATA = SPI_CMD_READ;
while(spi_rsp_occupied(qspi) == 0);
while((qspi->DATA & 0x80000000)==0);
while (spi_rsp_occupied(qspi) == 0)
;
while ((qspi->DATA & 0x80000000) == 0)
;
return qspi->DATA;
}
static inline void spi_select(volatile qspi_t *qspi, uint32_t slaveId) {
while(spi_cmd_avail(qspi) == 0);
qspi->DATA = slaveId | 0x80 | SPI_CMD_SS;
while (spi_cmd_avail(qspi) == 0)
;
qspi->DATA = (slaveId & 0x3) | 0x80 | SPI_CMD_SS;
}
static inline void spi_deselect(volatile qspi_t *qspi, uint32_t slaveId) {
while(spi_cmd_avail(qspi) == 0);
qspi->DATA = slaveId | SPI_CMD_SS;
while (spi_cmd_avail(qspi) == 0)
;
qspi->DATA = (slaveId & 0x3) | SPI_CMD_SS;
}
static inline void spi_wait_tx_idle(volatile qspi_t *qspi) {
while(spi_cmd_avail(qspi) < 0x20);
while (spi_cmd_avail(qspi) < 0x20)
;
}
#endif /* _DEVICES_QSPI_H */

13
include/ehrenberg/devices/timer.h
View File

@ -2,18 +2,13 @@
#define _DEVICES_TIMER_H
#include <stdint.h>
#include "gen/timercounter.h"
inline void prescaler_init(timercounter_t* reg, uint16_t value){
set_timercounter_prescaler(reg, value);
}
static inline void prescaler_init(timercounter_t *reg, uint16_t value) { set_timercounter_prescaler(reg, value); }
inline void timer_t0__init(timercounter_t *reg){
set_timercounter_t0_overflow(reg, 0xffffffff);
}
static inline void timer_t0__init(timercounter_t *reg) { set_timercounter_t0_overflow(reg, 0xffffffff); }
inline void timer_t1__init(timercounter_t *reg){
set_timercounter_t1_overflow(reg, 0xffffffff);
}
static inline void timer_t1__init(timercounter_t *reg) { set_timercounter_t1_overflow(reg, 0xffffffff); }
#endif /* _DEVICES_TIMER_H */

9
libwrap/stdlib/malloc.c
View File

@ -2,9 +2,10 @@
/* These functions are intended for embedded RV32 systems and are
obviously incorrect in general. */
void *__wrap_malloc(unsigned long sz);
void __wrap_free(void *ptr);
void* __wrap_malloc(unsigned long sz)
{
void *__wrap_malloc(unsigned long sz) {
extern void *sbrk(long);
void *res = sbrk(sz);
if ((long)res == -1)
@ -12,6 +13,4 @@ void* __wrap_malloc(unsigned long sz)
return res;
}
void __wrap_free(void* ptr)
{
}
void __wrap_free(void *ptr) { (void)(ptr); }

13
libwrap/sys/write.c
View File

@ -4,6 +4,7 @@
#include <stdint.h>
#include <sys/types.h>
#include <unistd.h>
#include <stdint.h>
#include "platform.h"
#include "stub.h"
@ -12,6 +13,8 @@
#include "semihosting.h"
#endif
extern uint32_t tohost;
ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
const uint8_t *current = (const uint8_t *)ptr;
#if defined(SEMIHOSTING)
@ -25,6 +28,14 @@ ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
return len;
}
// return len;
#elif defined(BOARD_iss)
volatile uint64_t payload[4];
payload[0]= 64;
payload[1]= 0;
payload[2]= (uintptr_t)ptr;
payload[3]= len;
tohost = (uint32_t)payload;
return len;
#endif
if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) {
@ -38,7 +49,7 @@ ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
uart_write(uart, '\r');
}
#elif defined(BOARD_iss)
*((uint32_t *)0xFFFF0000) = current[jj];
// *((uint32_t *)0xFFFF0000) = current[jj];
#elif defined(BOARD_TGCP)
// TODO: implement
#else