adds ehrenberg platform

include/ehrenberg/const.h

@@ -0,0 +1,18 @@
+// See LICENSE for license details.
+/* Derived from <linux/const.h> */
+
+#ifndef _SIFIVE_CONST_H
+#define _SIFIVE_CONST_H
+
+#ifdef __ASSEMBLER__
+#define _AC(X,Y)        X
+#define _AT(T,X)        X
+#else
+#define _AC(X,Y)        (X##Y)
+#define _AT(T,X)        ((T)(X))
+#endif /* !__ASSEMBLER__*/
+
+#define _BITUL(x)       (_AC(1,UL) << (x))
+#define _BITULL(x)      (_AC(1,ULL) << (x))
+
+#endif /* _SIFIVE_CONST_H */

include/ehrenberg/devices.h

@@ -0,0 +1,37 @@
+/*
+ * devices.c
+ *
+ *  Created on: Aug 15, 2020
+ *      Author: eyck
+ */
+
+#ifndef _BSP_EHRENBERG_DEVICES_C_
+#define _BSP_EHRENBERG_DEVICES_C_
+
+#define APB_BUS
+
+#include "devices/gpio.h"
+#include "devices/interrupt.h"
+#include "devices/timer.h"
+#include "devices/uart.h"
+#include "devices/qspi.h"
+
+#define PERIPH(TYPE, ADDR) ((volatile TYPE*) (ADDR))
+
+#define APB_BASE 0xF0000000
+#define TIMER_BASE                 (APB_BASE+0x30000)
+
+#define gpio_a    PERIPH(gpio_t,   APB_BASE+0x00000)
+//#define gpio_b     PERIPH(gpio_t, APB_BASE+0x10000)
+#define uart      PERIPH(uart_t,   APB_BASE+0x10000)
+#define prescaler PERIPH(uart_t,   TIMER_BASE+0x0)
+#define timer_a   PERIPH(uart_t,   TIMER_BASE+0x10)
+#define timer_b   PERIPH(uart_t,   TIMER_BASE+0x20)
+#define mtimer    PERIPH(mtimer_t, APB_BASE+0x30000)
+#define irq       PERIPH(irq_t,    APB_BASE+0x40000)
+#define qspi      PERIPH(qspi_t,   APB_BASE+0x50000)
+//volatile qspi_t*   const qspi       = (qspi_t*)(APB_BASE+0x50000);
+
+#define XIP_START_LOC 0xE0040000
+
+#endif /* _BSP_EHRENBERG_DEVICES_C_ */

include/ehrenberg/devices/gpio.h

@@ -0,0 +1,17 @@
+#ifndef _BSP_GPIO_H
+#define _BSP_GPIO_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t pin_in;
+    volatile uint32_t pin_out;
+    volatile uint32_t out_en;
+} gpio_t;
+
+inline void gpio_init(gpio_t* reg) {
+    reg->out_en=0;
+    reg->pin_out=0;
+}
+
+#endif /* _BSP_GPIO_H */

include/ehrenberg/devices/interrupt.h

@@ -0,0 +1,16 @@
+#ifndef _BSP_INTERRUPT_H
+#define _BSP_INTERRUPT_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t ip;
+    volatile uint32_t ie;
+} irq_t;
+
+inline void irq_init(irq_t* reg){
+    reg->ie = 0;
+    reg->ip = 0xFFFFFFFF;
+}
+
+#endif /* _BSP_INTERRUPT_H */

include/ehrenberg/devices/qspi.h

@@ -0,0 +1,112 @@
+#ifndef _BSP_QSPI_H
+#define _BSP_QSPI_H
+
+#include <stdint.h>
+
+#define __IO volatile
+
+typedef struct {
+    __IO uint32_t data;             // 0x0/0: data, 8bits, 8:write, 9:read, 11:data/ctrl, 31:rxdata valid
+    __IO uint32_t status;           // 0x4/0: txavail, 16: rxused
+    __IO uint32_t config;           // 0x8/0:1 cpol/cpha, 4: transfer mode (0-FullDuplex)
+    __IO uint32_t intr;             // 0xc/0: txien, 1: rxien, 8: txip, 9: rxip, 16: valid?
+    __IO uint32_t __fill0[4];
+    __IO uint32_t clk_divider;      // 0x20/0: sclkToogle
+    // ssGen config
+    __IO uint32_t ss_setup;         // 0x24/0: setup
+    __IO uint32_t ss_hold;          // 0x28/0: hold
+    __IO uint32_t ss_disable;       // 0x2c/0: disable
+    __IO uint32_t ss_activeHigh;    // 0x30/0: disable
+    __IO uint32_t __fill1[3];
+    __IO uint32_t xip_enable;       // 0x40/0: enable
+    __IO uint32_t xip_instr;        // 0x44/0:7 data, 8: enable, 16:23 dummy data, 24:27 dummy count
+    __IO uint32_t xip_mode;         // 0x48/0: instr transfer mode, 8: addr transfer mode, 16: dummy transfer mode, 24: data transfer mode
+    __IO uint32_t __fill2[2];
+    __IO uint32_t xip_write32;      // 0x50
+    __IO uint32_t xip_readwrite32;  // 0x54
+    __IO uint32_t xip_read32;       // 0x58
+}  __attribute((__packed__)) qspi_t;
+
+typedef struct {
+    uint32_t cpol;
+    uint32_t cpha;
+    uint32_t mode;
+    uint32_t clkDivider;
+    uint32_t ssSetup;
+    uint32_t ssHold;
+    uint32_t ssDisable;
+} spi_cfg;
+
+#define SPI_CMD_WRITE (1 << 8)
+#define SPI_CMD_READ (1 << 9)
+#define SPI_CMD_SS (1 << 11)
+
+#define SPI_RSP_VALID (1 << 31)
+
+#define SPI_STATUS_CMD_INT_ENABLE = (1 << 0)
+#define SPI_STATUS_RSP_INT_ENABLE = (1 << 1)
+#define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
+#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
+
+static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
+    reg->config     = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
+    reg->clk_divider = config->clkDivider;
+    reg->ss_setup   = config->ssSetup;
+    reg->ss_hold    = config->ssHold;
+    reg->ss_disable =config->ssDisable;
+}
+
+static inline void spi_init(volatile qspi_t* spi){
+    spi_cfg spiCfg;
+    spiCfg.cpol = 0;
+    spiCfg.cpha = 0;
+    spiCfg.mode = 0;
+    spiCfg.clkDivider = 2;
+    spiCfg.ssSetup = 2;
+    spiCfg.ssHold = 2;
+    spiCfg.ssDisable = 2;
+    spi_configure(spi, &spiCfg);
+}
+
+static inline uint32_t spi_cmd_avail(volatile qspi_t* reg){
+    return reg->status & 0xFFFF;
+}
+static inline uint32_t spi_rsp_occupied(volatile qspi_t* reg){
+    return reg->status >> 16;
+}
+
+static inline void spi_write(volatile qspi_t* reg, uint8_t data){
+    while(spi_cmd_avail(reg) == 0);
+    reg->data = data | SPI_CMD_WRITE;
+}
+
+static inline uint8_t spi_write_read(volatile qspi_t* reg, uint8_t data){
+    while(spi_cmd_avail(reg) == 0);
+    reg->data = data | SPI_CMD_READ | SPI_CMD_WRITE;
+    while(spi_rsp_occupied(reg) == 0);
+    return reg->data;
+}
+
+
+static inline uint8_t spi_read(volatile qspi_t* reg){
+    while(spi_cmd_avail(reg) == 0);
+    reg->data = SPI_CMD_READ;
+    while(spi_rsp_occupied(reg) == 0);
+    while((reg->data & 0x80000000)==0);
+    return reg->data;
+}
+
+static inline void spi_select(volatile qspi_t* reg, uint32_t slaveId){
+    while(spi_cmd_avail(reg) == 0);
+    reg->data = slaveId | 0x80 | SPI_CMD_SS;
+}
+
+static inline void spi_deselect(volatile qspi_t* reg, uint32_t slaveId){
+    while(spi_cmd_avail(reg) == 0);
+    reg->data = slaveId | SPI_CMD_SS;
+}
+
+static inline void spi_wait_tx_idle(volatile qspi_t* reg){
+    while(spi_cmd_avail(reg) < 0x20);
+}
+#endif /* _BSP_QSPI_H */

include/ehrenberg/devices/timer.h

@@ -0,0 +1,52 @@
+#ifndef _BSP_TIMER_H
+#define _BSP_TIMER_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t mtime;     // 0x0:0
+    volatile uint32_t mtimeh;    // 0x4:0
+    volatile uint32_t mtimecmp;  // 0x8:0
+    volatile uint32_t mtimecmph; // 0xc:0
+} mtimer_t;
+
+#ifndef APB_BUS
+typedef struct __attribute((__packed__)) {
+    volatile uint16_t count;
+} prescaler_t;
+
+typedef struct __attribute((__packed__)) {
+    volatile uint16_t clk_en;      // 0x0:0, 0->always, 1->prescaler
+    volatile uint16_t clr_en;      // 0x2:0, 0->on overflow
+    volatile uint32_t limit;       // 0x4:0, upper limit of counter
+    volatile uint32_t timer_value; // 0x8:0 current timer value
+} timer_a_t;
+
+#else
+
+typedef struct __attribute((__packed__)) {
+  volatile uint32_t LIMIT;
+} prescaler_t;
+
+typedef struct __attribute((__packed__)) {
+  volatile uint32_t CLEARS_TICKS;   // 0x0/0:0->always, 1->prescaler; 16:0->on overflow
+  volatile uint32_t LIMIT;          // 0x4/0 upper limit of counter
+  volatile uint32_t VALUE;          // 0x8/0 current timer value
+} timer_a_t;
+
+inline void prescaler_init(prescaler_t* reg){
+    (void)reg;
+}
+
+inline void timer_init(timer_a_t *reg){
+    reg->CLEARS_TICKS  = 0;
+    reg->VALUE = 0;
+}
+
+inline void mtimer_init(mtimer_t *reg){
+    reg->mtimecmph  = UINT32_MAX;
+    reg->mtimecmp = UINT32_MAX;
+}
+
+#endif
+#endif /* _BSP_TIMER_H */

include/ehrenberg/devices/uart.h

@@ -0,0 +1,67 @@
+#ifndef _BSP_UART_H
+#define _BSP_UART_H
+
+#include <stdint.h>
+
+enum uart_parity_e {NONE = 0, EVEN = 1, ODD = 2};
+enum uart_stop_e   {ONE = 0, TWO = 1};
+
+#ifndef APB_BUS
+typedef struct __attribute((__packed__)){
+    // 0x0
+    volatile uint16_t rx_tx_reg; // 8bit, 0x0
+    volatile uint16_t rx_avail;  // 1bit, 0x0:16
+    // 0x4
+    volatile uint16_t irq_ctrl; // 0->tx_ie, 1->rx_ie, 8->tx_ip, 9->rx_ip
+    volatile uint8_t num_tx_avail; // 8bit, 0x4:16
+    volatile uint8_t num_rx_avail; // 8bit, 0x4:24
+    volatile uint32_t dummy;
+    // 0xc
+    volatile uint8_t clock_div;  // 3bit, 0xc:0
+    volatile uint8_t frame;     // 2bit, 0xc:8
+    volatile uint8_t stop_bits; // 1bit, 0xc:16
+    // 0x10
+    volatile uint8_t status; // readError->0, readOverflowError->1,
+    volatile uint8_t active; // rx_active->0, tx_active-1, set_tx_active->2, clear_tx_active->3
+} uart_t;
+#else
+typedef struct __attribute((__packed__)) {
+  volatile uint32_t DATA;
+  volatile uint32_t STATUS;
+  volatile uint32_t CLOCK_DIVIDER;
+  volatile uint32_t FRAME_CONFIG;
+} uart_t;
+
+
+typedef struct __attribute((__packed__)) {
+    uint32_t data_length;
+    enum uart_parity_e parity;
+    enum uart_stop_e stop;
+    uint32_t clock_divider;
+} uart_config_t;
+
+static inline uint32_t uart_get_tx_free(volatile uart_t *reg){
+    return (reg->STATUS >> 16) & 0xFF;
+}
+
+static inline uint32_t uart_get_rx_avail(volatile uart_t *reg){
+    return reg->STATUS >> 24;
+}
+
+static void uart_write(volatile uart_t *reg, uint8_t data){
+    while(uart_get_tx_free(reg) == 0);
+    reg->DATA = data;
+}
+
+static inline uint8_t uart_read(volatile uart_t *reg){
+    uint32_t res = reg->DATA;
+    while((res&0x10000) == 0) res = reg->DATA;
+    return res;
+}
+
+static inline void uart_set_config(volatile uart_t *reg, uart_config_t *config){
+    reg->CLOCK_DIVIDER = config->clock_divider;
+    reg->FRAME_CONFIG = ((config->data_length-1) << 0) | (config->parity << 8) | (config->stop << 16);
+}
+#endif
+#endif /* _BSP_UART_H */