Merge remote-tracking branch 'origin/develop'

https://git.minres.com/DBT-RISE/DBT-RISE-TGC.git

gen_input/templates/CORENAME_sysc.cpp.gtl

@@ -45,17 +45,17 @@ namespace interp {
 using namespace sysc;
 volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         }),
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|interp", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%}%>
@@ -66,17 +66,17 @@ namespace llvm {
 using namespace sysc;
 volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         }),
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%}%>
@@ -88,17 +88,17 @@ namespace tcc {
 using namespace sysc;
 volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         }),
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|tcc", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%}%>
@@ -110,17 +110,17 @@ namespace asmjit {
 using namespace sysc;
 volatile std::array<bool, ${array_count}> ${coreDef.name.toLowerCase()}_init = {
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         }),
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%if(coreDef.name.toLowerCase()=="tgc5d" || coreDef.name.toLowerCase()=="tgc5e") {%>,
         iss_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p_clic_pmp|asmjit", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-            auto* cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+            auto* cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
             auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::${coreDef.name.toLowerCase()}, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_EXT_N | iss::arch::FEAT_CLIC)>>(cc);
             return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::${coreDef.name.toLowerCase()}*>(cpu), gdb_port)}};
         })<%}%>

gen_input/templates/asmjit/CORENAME.cpp.gtl

@@ -263,6 +263,7 @@ void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
     cmp(cc, current_trap_state, 0);
     cc.jne(jh.trap_entry);
     cc.inc(get_ptr_for(jh, traits::ICOUNT));
+    cc.inc(get_ptr_for(jh, traits::CYCLE));
 }
 template <typename ARCH>
 void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){

src/elfio.cpp

@@ -3,34 +3,33 @@
 #define ELFIO_NO_INTTYPES
 #endif
 
-#include <iostream>
 #include <elfio/elfio_dump.hpp>
+#include <iostream>
 
 using namespace ELFIO;
 
-int main( int argc, char** argv )
+int main(int argc, char** argv) {
-{
+    if(argc != 2) {
-    if ( argc != 2 ) {
+        printf("Usage: elfdump <file_name>\n");
-        printf( "Usage: elfdump <file_name>\n" );
         return 1;
     }
 
     elfio reader;
 
-    if ( !reader.load( argv[1] ) ) {
+    if(!reader.load(argv[1])) {
-        printf( "File %s is not found or it is not an ELF file\n", argv[1] );
+        printf("File %s is not found or it is not an ELF file\n", argv[1]);
         return 1;
     }
 
-    dump::header( std::cout, reader );
+    dump::header(std::cout, reader);
-    dump::section_headers( std::cout, reader );
+    dump::section_headers(std::cout, reader);
-    dump::segment_headers( std::cout, reader );
+    dump::segment_headers(std::cout, reader);
-    dump::symbol_tables( std::cout, reader );
+    dump::symbol_tables(std::cout, reader);
-    dump::notes( std::cout, reader );
+    dump::notes(std::cout, reader);
-    dump::modinfo( std::cout, reader );
+    dump::modinfo(std::cout, reader);
-    dump::dynamic_tags( std::cout, reader );
+    dump::dynamic_tags(std::cout, reader);
-    dump::section_datas( std::cout, reader );
+    dump::section_datas(std::cout, reader);
-    dump::segment_datas( std::cout, reader );
+    dump::segment_datas(std::cout, reader);
 
     return 0;
 }

src/iss/arch/riscv_hart_common.h

@@ -36,14 +36,11 @@
 #define _RISCV_HART_COMMON
 
 #include "iss/vm_types.h"
-#include <array>
 #include <cstdint>
 #include <elfio/elfio.hpp>
 #include <fmt/format.h>
 #include <iss/arch_if.h>
 #include <iss/log_categories.h>
-#include <limits>
-#include <sstream>
 #include <string>
 #include <unordered_map>
 #include <util/logging.h>
@@ -59,6 +56,8 @@
 namespace iss {
 namespace arch {
 
+enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
+
 enum features_e { FEAT_NONE, FEAT_PMP = 1, FEAT_EXT_N = 2, FEAT_CLIC = 4, FEAT_DEBUG = 8, FEAT_TCM = 16 };
 
 enum riscv_csr {
@@ -317,8 +316,8 @@ struct riscv_hart_common {
     ~riscv_hart_common(){};
     std::unordered_map<std::string, uint64_t> symbol_table;
     uint64_t entry_address{0};
-    uint64_t tohost = std::numeric_limits<uint64_t>::max();
+    uint64_t tohost = tohost_dflt;
-    uint64_t fromhost = std::numeric_limits<uint64_t>::max();
+    uint64_t fromhost = fromhost_dflt;
 
     bool read_elf_file(std::string name, uint8_t expected_elf_class,
                        std::function<iss::status(uint64_t, uint64_t, const uint8_t* const)> cb) {
@@ -366,10 +365,11 @@ struct riscv_hart_common {
                 }
                 try {
                     tohost = symbol_table.at("tohost");
-                } catch(std::out_of_range& e) {
+                    try {
-                }
+                        fromhost = symbol_table.at("fromhost");
-                try {
+                    } catch(std::out_of_range& e) {
-                    fromhost = symbol_table.at("fromhost");
+                        fromhost = tohost + 0x40;
+                    }
                 } catch(std::out_of_range& e) {
                 }
             }
@@ -377,36 +377,6 @@ struct riscv_hart_common {
         }
         return false;
     };
-    iss::status execute_sys_write(arch_if* aif, const std::array<uint64_t, 8>& loaded_payload, unsigned mem_type) {
-        std::stringstream io_buf;
-        uint64_t fd = loaded_payload[1];
-        uint64_t buf_ptr = loaded_payload[2];
-        uint64_t len = loaded_payload[3];
-        std::vector<char> buf(len);
-        if(aif->read(address_type::PHYSICAL, access_type::DEBUG_READ, mem_type, buf_ptr, len, reinterpret_cast<uint8_t*>(buf.data()))) {
-            CPPLOG(ERR) << "SYS_WRITE buffer read went wrong";
-            return iss::Err;
-        }
-        // we disregard the fd and just log to stdout
-        for(size_t i = 0; i < len; i++) {
-            if(buf[i] == '\n') {
-                CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
-                io_buf.str("");
-            } else
-                io_buf << buf[i];
-        }
-        if(io_buf.str().length()) {
-            CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
-        }
-        // Not sure what the correct return value should be
-        uint8_t ret_val = 1;
-        if(fromhost != std::numeric_limits<uint64_t>::max())
-            if(aif->write(address_type::PHYSICAL, access_type::DEBUG_WRITE, mem_type, fromhost, 1, &ret_val)) {
-                CPPLOG(ERR) << "Fromhost write went wrong";
-                return iss::Err;
-            }
-        return iss::Ok;
-    }
 };
 
 } // namespace arch

src/iss/arch/riscv_hart_m_p.h

@@ -41,11 +41,7 @@
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
 #include "riscv_hart_common.h"
-#include "util/logging.h"
-#include <algorithm>
-#include <cstdint>
 #include <elfio/elf_types.hpp>
-#include <limits>
 #include <stdexcept>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -348,6 +344,7 @@ protected:
     int64_t instret_offset{0};
     uint64_t minstret_csr{0};
     reg_t fault_data;
+    bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
     semihosting_cb_t<reg_t> semihosting_cb;
@@ -357,6 +354,7 @@ protected:
     using csr_page_type = typename csr_type::page_type;
     mem_type mem;
     csr_type csr;
+    std::stringstream uart_buf;
     std::unordered_map<reg_t, uint64_t> ptw;
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
@@ -448,6 +446,7 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
     csr[marchid] = traits<BASE>::MARCHID_VAL;
     csr[mimpid] = 1;
 
+    uart_buf.str("");
     if(traits<BASE>::FLEN > 0) {
         csr_rd_cb[fcsr] = &this_class::read_fcsr;
         csr_wr_cb[fcsr] = &this_class::write_fcsr;
@@ -611,7 +610,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read(const address_type type, co
     try {
         switch(space) {
         case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
+            auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : length;
             if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
                 fault_data = addr;
                 if(is_debug(access))
@@ -721,8 +720,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
                 return iss::Err;
             }
             try {
-                auto alignment = std::min<unsigned>(length, sizeof(reg_t));
+                if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) {
-                if(length > 1 && (addr & (alignment - 1)) && !is_debug(access)) {
                     this->reg.trap_state = (1UL << 31) | 6 << 16;
                     fault_data = addr;
                     return iss::Err;
@@ -742,7 +740,7 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
                 } else {
                     res = write_mem(phys_addr, length, data);
                 }
-                if(unlikely(res != iss::Ok && !is_debug(access))) {
+                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
                     this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data = addr;
                 }
@@ -752,6 +750,38 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
                 fault_data = ta.addr;
                 return iss::Err;
             }
+
+            if((addr + length) > mem.size())
+                return iss::Err;
+            switch(addr) {
+            case 0x10013000: // UART0 base, TXFIFO reg
+            case 0x10023000: // UART1 base, TXFIFO reg
+                uart_buf << (char)data[0];
+                if(((char)data[0]) == '\n' || data[0] == 0) {
+                    std::cout << uart_buf.str();
+                    uart_buf.str("");
+                }
+                return iss::Ok;
+            case 0x10008000: { // HFROSC base, hfrosccfg reg
+                auto& p = mem(addr / mem.page_size);
+                auto offs = addr & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                if(x & 0x40)
+                    x |= 0x80; // hfroscrdy = 1 if hfroscen==1
+                return iss::Ok;
+            }
+            case 0x10008008: { // HFROSC base, pllcfg reg
+                auto& p = mem(addr / mem.page_size);
+                auto offs = addr & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                x |= 0x80; // set pll lock upon writing
+                return iss::Ok;
+            } break;
+            default: {
+            }
+            }
         } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
@@ -1064,51 +1094,59 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_mem(phys_addr_t paddr, unsi
 
 template <typename BASE, features_e FEAT, typename LOGCAT>
 iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
-    mem_type::page_type& p = mem(paddr.val / mem.page_size);
+    switch(paddr.val) {
-    std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
+    // TODO remove UART, Peripherals should not be part of the ISS
-    // tohost handling in case of riscv-test
+    case 0xFFFF0000: // UART0 base, TXFIFO reg
-    // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
+        if(((char)data[0]) == '\n' || data[0] == 0) {
-    if(paddr.access && iss::access_type::FUNC) {
+            CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
-        if(paddr.val == tohost) {
+            uart_buf.str("");
-            reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
+        } else if(((char)data[0]) != '\r')
-            // Extract Device (bits 63:56)
+            uart_buf << (char)data[0];
-            uint8_t device = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF;
+        break;
-            // Extract Command (bits 55:48)
+    default: {
-            uint8_t command = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF;
+        mem_type::page_type& p = mem(paddr.val / mem.page_size);
-            // Extract payload (bits 47:0)
+        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
-            uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL;
+        // tohost handling in case of riscv-test
-            if(payload_addr & 1) {
+        if(paddr.access && iss::access_type::FUNC) {
-                CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
+            auto tohost_upper =
-                              << "), stopping simulation";
+                (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+            auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-                this->interrupt_sim = payload_addr;
+            if(tohost_lower || tohost_upper) {
-                return iss::Ok;
+                uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
-            } else if(device == 0 && command == 0) {
+                // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
-                std::array<uint64_t, 8> loaded_payload;
+                if(tohost_upper && (tohost_lower || tohost_lower_written)) {
-                if(read(address_type::PHYSICAL, access_type::DEBUG_READ, traits<BASE>::MEM, payload_addr, 8 * sizeof(uint64_t),
+                    switch(hostvar >> 48) {
-                        reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
+                    case 0:
-                    CPPLOG(ERR) << "Syscall read went wrong";
+                        if(hostvar != 0x1) {
-                uint64_t syscall_num = loaded_payload.at(0);
+                            CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                if(syscall_num == 64) { // SYS_WRITE
+                                          << "), stopping simulation";
-                    return execute_sys_write(this, loaded_payload, traits<BASE>::MEM);
+                        } else {
-                } else {
+                            CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                    CPPLOG(ERR) << "tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num
+                                         << "), stopping simulation";
-                                << ") not implemented";
+                        }
-                    this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+                        this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                    this->interrupt_sim = payload_addr;
+                        this->interrupt_sim = hostvar;
-                    return iss::Ok;
+                        break;
-                }
+                    case 0x0101: {
-            } else {
+                        char c = static_cast<char>(hostvar & 0xff);
-                CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
+                        if(c == '\n' || c == 0) {
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+                            CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
-                this->interrupt_sim = payload_addr;
+                            uart_buf.str("");
-                return iss::Ok;
+                        } else
+                            uart_buf << c;
+                    } break;
+                    default:
+                        break;
+                    }
+                    tohost_lower_written = false;
+                } else if(tohost_lower)
+                    tohost_lower_written = true;
+            } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+                uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
+                *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
         }
-        if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+    }
-            uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
-            *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
-        }
     }
     return iss::Ok;
 }

src/iss/arch/riscv_hart_msu_vp.h

@@ -41,11 +41,6 @@
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
 #include "riscv_hart_common.h"
-#include "util/logging.h"
-#include <algorithm>
-#include <cstdint>
-#include <elfio/elf_types.hpp>
-#include <limits>
 #include <stdexcept>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -398,6 +393,7 @@ protected:
     uint64_t minstret_csr{0};
     reg_t fault_data;
     std::array<vm_info, 2> vm;
+    bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
     std::function<void(arch_if*, reg_t, reg_t)> semihosting_cb;
@@ -408,6 +404,7 @@ protected:
     mem_type mem;
     csr_type csr;
     void update_vm_info();
+    std::stringstream uart_buf;
     std::unordered_map<reg_t, uint64_t> ptw;
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
@@ -462,6 +459,7 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
     csr[marchid] = traits<BASE>::MARCHID_VAL;
     csr[mimpid] = 1;
 
+    uart_buf.str("");
     for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) {
         csr_rd_cb[addr] = &this_class::read_null;
         csr_wr_cb[addr] = &this_class::write_csr_reg;
@@ -582,7 +580,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
     try {
         switch(space) {
         case traits<BASE>::MEM: {
-            auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
+            auto alignment = is_fetch(access) ? (traits<BASE>::MISA_VAL & 0x100 ? 2 : 4) : length;
             if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
                 fault_data = addr;
                 if(access && iss::access_type::DEBUG)
@@ -701,7 +699,6 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
             }
             phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
             try {
-                // TODO: There is no check for alignment
                 if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
                     vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp);
                     if(vm.levels != 0) { // VM is active
@@ -724,6 +721,40 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
                 fault_data = ta.addr;
                 return iss::Err;
             }
+
+            if((paddr.val + length) > mem.size())
+                return iss::Err;
+            switch(paddr.val) {
+            case 0x10013000: // UART0 base, TXFIFO reg
+            case 0x10023000: // UART1 base, TXFIFO reg
+                uart_buf << (char)data[0];
+                if(((char)data[0]) == '\n' || data[0] == 0) {
+                    // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
+                    // '"<<uart_buf.str()<<"'";
+                    std::cout << uart_buf.str();
+                    uart_buf.str("");
+                }
+                return iss::Ok;
+            case 0x10008000: { // HFROSC base, hfrosccfg reg
+                auto& p = mem(paddr.val / mem.page_size);
+                auto offs = paddr.val & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                if(x & 0x40)
+                    x |= 0x80; // hfroscrdy = 1 if hfroscen==1
+                return iss::Ok;
+            }
+            case 0x10008008: { // HFROSC base, pllcfg reg
+                auto& p = mem(paddr.val / mem.page_size);
+                auto offs = paddr.val & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                x |= 0x80; // set pll lock upon writing
+                return iss::Ok;
+            } break;
+            default: {
+            }
+            }
         } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
@@ -993,51 +1024,61 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
-    mem_type::page_type& p = mem(paddr.val / mem.page_size);
+    switch(paddr.val) {
-    std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
+    case 0xFFFF0000: // UART0 base, TXFIFO reg
-    // tohost handling in case of riscv-test
+        if(((char)data[0]) == '\n' || data[0] == 0) {
-    // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
+            CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
-    if(paddr.access && iss::access_type::FUNC) {
+            uart_buf.str("");
-        if(paddr.val == tohost) {
+        } else if(((char)data[0]) != '\r')
-            reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
+            uart_buf << (char)data[0];
-            // Extract Device (bits 63:56)
+        break;
-            uint8_t device = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF;
+    default: {
-            // Extract Command (bits 55:48)
+        mem_type::page_type& p = mem(paddr.val / mem.page_size);
-            uint8_t command = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF;
+        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
-            // Extract payload (bits 47:0)
+        // tohost handling in case of riscv-test
-            uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL;
+        if(paddr.access && iss::access_type::FUNC) {
-            if(payload_addr & 1) {
+            auto tohost_upper =
-                CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
+                (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-                              << "), stopping simulation";
+            auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+            if(tohost_lower || tohost_upper) {
-                this->interrupt_sim = payload_addr;
+                uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
-                return iss::Ok;
+                // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
-            } else if(device == 0 && command == 0) {
+                if(tohost_upper && (tohost_lower || tohost_lower_written)) {
-                std::array<uint64_t, 8> loaded_payload;
+                    switch(hostvar >> 48) {
-                if(read(address_type::PHYSICAL, access_type::DEBUG_READ, traits<BASE>::MEM, payload_addr, 8 * sizeof(uint64_t),
+                    case 0:
-                        reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
+                        if(hostvar != 0x1) {
-                    CPPLOG(ERR) << "Syscall read went wrong";
+                            CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                uint64_t syscall_num = loaded_payload.at(0);
+                                          << "), stopping simulation";
-                if(syscall_num == 64) { // SYS_WRITE
+                        } else {
-                    return execute_sys_write(this, loaded_payload, traits<BASE>::MEM);
+                            CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                } else {
+                                         << "), stopping simulation";
-                    CPPLOG(ERR) << "tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num
+                        }
-                                << ") not implemented";
+                        this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                    this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+                        this->interrupt_sim = hostvar;
-                    this->interrupt_sim = payload_addr;
+#ifndef WITH_TCC
-                    return iss::Ok;
+                        throw(iss::simulation_stopped(hostvar));
-                }
+#endif
-            } else {
+                        break;
-                CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
+                    case 0x0101: {
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+                        char c = static_cast<char>(hostvar & 0xff);
-                this->interrupt_sim = payload_addr;
+                        if(c == '\n' || c == 0) {
-                return iss::Ok;
+                            CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
+                            uart_buf.str("");
+                        } else
+                            uart_buf << c;
+                    } break;
+                    default:
+                        break;
+                    }
+                    tohost_lower_written = false;
+                } else if(tohost_lower)
+                    tohost_lower_written = true;
+            } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+                uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
+                *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
         }
-        if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+    }
-            uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
-            *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
-        }
     }
     return iss::Ok;
 }

src/iss/arch/riscv_hart_mu_p.h

@@ -41,11 +41,6 @@
 #include "iss/vm_if.h"
 #include "iss/vm_types.h"
 #include "riscv_hart_common.h"
-#include "util/logging.h"
-#include <algorithm>
-#include <cstdint>
-#include <elfio/elf_types.hpp>
-#include <limits>
 #include <stdexcept>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -375,6 +370,7 @@ protected:
     int64_t instret_offset{0};
     uint64_t minstret_csr{0};
     reg_t fault_data;
+    bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
     semihosting_cb_t<reg_t> semihosting_cb;
@@ -384,6 +380,7 @@ protected:
     using csr_page_type = typename csr_type::page_type;
     mem_type mem;
     csr_type csr;
+    std::stringstream uart_buf;
     std::unordered_map<reg_t, uint64_t> ptw;
     std::unordered_map<uint64_t, uint8_t> atomic_reservation;
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
@@ -478,6 +475,7 @@ riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
     csr[marchid] = traits<BASE>::MARCHID_VAL;
     csr[mimpid] = 1;
 
+    uart_buf.str("");
     if(traits<BASE>::FLEN > 0) {
         csr_rd_cb[fcsr] = &this_class::read_fcsr;
         csr_wr_cb[fcsr] = &this_class::write_fcsr;
@@ -785,7 +783,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read(const address_type type, c
                     return iss::Err;
                 }
             }
-            auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : std::min<unsigned>(length, sizeof(reg_t));
+            auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : length;
             if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) {
                 fault_data = addr;
                 if(is_debug(access))
@@ -904,8 +902,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
                 return iss::Err;
             }
             try {
-                auto alignment = std::min<unsigned>(length, sizeof(reg_t));
+                if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) {
-                if(length > 1 && (addr & (alignment - 1)) && !is_debug(access)) {
                     this->reg.trap_state = (1UL << 31) | 6 << 16;
                     fault_data = addr;
                     return iss::Err;
@@ -935,6 +932,38 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write(const address_type type,
                 fault_data = ta.addr;
                 return iss::Err;
             }
+
+            if((addr + length) > mem.size())
+                return iss::Err;
+            switch(addr) {
+            case 0x10013000: // UART0 base, TXFIFO reg
+            case 0x10023000: // UART1 base, TXFIFO reg
+                uart_buf << (char)data[0];
+                if(((char)data[0]) == '\n' || data[0] == 0) {
+                    std::cout << uart_buf.str();
+                    uart_buf.str("");
+                }
+                return iss::Ok;
+            case 0x10008000: { // HFROSC base, hfrosccfg reg
+                auto& p = mem(addr / mem.page_size);
+                auto offs = addr & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                if(x & 0x40)
+                    x |= 0x80; // hfroscrdy = 1 if hfroscen==1
+                return iss::Ok;
+            }
+            case 0x10008008: { // HFROSC base, pllcfg reg
+                auto& p = mem(addr / mem.page_size);
+                auto offs = addr & mem.page_addr_mask;
+                std::copy(data, data + length, p.data() + offs);
+                auto& x = *(p.data() + offs + 3);
+                x |= 0x80; // set pll lock upon writing
+                return iss::Ok;
+            } break;
+            default: {
+            }
+            }
         } break;
         case traits<BASE>::CSR: {
             if(length != sizeof(reg_t))
@@ -1283,53 +1312,65 @@ iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::read_mem(phys_addr_t paddr, uns
     }
     return iss::Ok;
 }
+
 template <typename BASE, features_e FEAT, typename LOGCAT>
 iss::status riscv_hart_mu_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
-    mem_type::page_type& p = mem(paddr.val / mem.page_size);
+    switch(paddr.val) {
-    std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
+    // TODO remove UART, Peripherals should not be part of the ISS
-    // tohost handling in case of riscv-test
+    case 0xFFFF0000: // UART0 base, TXFIFO reg
-    // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
+        if(((char)data[0]) == '\n' || data[0] == 0) {
-    if(paddr.access && iss::access_type::FUNC) {
+            CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
-        if(paddr.val == tohost) {
+            uart_buf.str("");
-            reg_t cur_data = *reinterpret_cast<const reg_t*>(data);
+        } else if(((char)data[0]) != '\r')
-            // Extract Device (bits 63:56)
+            uart_buf << (char)data[0];
-            uint8_t device = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF;
+        break;
-            // Extract Command (bits 55:48)
+    default: {
-            uint8_t command = traits<BASE>::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF;
+        mem_type::page_type& p = mem(paddr.val / mem.page_size);
-            // Extract payload (bits 47:0)
+        std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
-            uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL;
+        // tohost handling in case of riscv-test
-            if(payload_addr & 1) {
+        if(paddr.access && iss::access_type::FUNC) {
-                CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
+            auto tohost_upper =
-                              << "), stopping simulation";
+                (traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+            auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
-                this->interrupt_sim = payload_addr;
+            if(tohost_lower || tohost_upper) {
-                return iss::Ok;
+                uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
-            } else if(device == 0 && command == 0) {
+                // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
-                std::array<uint64_t, 8> loaded_payload;
+                if(tohost_upper && (tohost_lower || tohost_lower_written)) {
-                if(read(address_type::PHYSICAL, access_type::DEBUG_READ, traits<BASE>::MEM, payload_addr, 8 * sizeof(uint64_t),
+                    switch(hostvar >> 48) {
-                        reinterpret_cast<uint8_t*>(loaded_payload.data())) == iss::Err)
+                    case 0:
-                    CPPLOG(ERR) << "Syscall read went wrong";
+                        if(hostvar != 0x1) {
-                uint64_t syscall_num = loaded_payload.at(0);
+                            CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                if(syscall_num == 64) { // SYS_WRITE
+                                          << "), stopping simulation";
-                    return execute_sys_write(this, loaded_payload, traits<BASE>::MEM);
+                        } else {
-                } else {
+                            CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                    CPPLOG(ERR) << "tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num
+                                         << "), stopping simulation";
-                                << ") not implemented";
+                        }
-                    this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+                        this->reg.trap_state = std::numeric_limits<uint32_t>::max();
-                    this->interrupt_sim = payload_addr;
+                        this->interrupt_sim = hostvar;
-                    return iss::Ok;
+#ifndef WITH_TCC
-                }
+                        throw(iss::simulation_stopped(hostvar));
-            } else {
+#endif
-                CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
+                        break;
-                this->reg.trap_state = std::numeric_limits<uint32_t>::max();
+                    case 0x0101: {
-                this->interrupt_sim = payload_addr;
+                        char c = static_cast<char>(hostvar & 0xff);
-                return iss::Ok;
+                        if(c == '\n' || c == 0) {
+                            CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
+                            uart_buf.str("");
+                        } else
+                            uart_buf << c;
+                    } break;
+                    default:
+                        break;
+                    }
+                    tohost_lower_written = false;
+                } else if(tohost_lower)
+                    tohost_lower_written = true;
+            } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+                uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
+                *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
             }
         }
-        if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
+    }
-            uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
-            *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
-        }
     }
     return iss::Ok;
 }

src/main.cpp

@@ -206,13 +206,21 @@ int main(int argc, char* argv[]) {
         if(clim.count("elf"))
             for(std::string input : clim["elf"].as<std::vector<std::string>>()) {
                 auto start_addr = vm->get_arch()->load_file(input);
-                if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
+                if(start_addr.second)
                     start_address = start_addr.first;
+                else {
+                    LOG(ERR) << "Error occured while loading file " << input << std::endl;
+                    return 1;
+                }
             }
         for(std::string input : args) {
             auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
-            if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
+            if(start_addr.second)
                 start_address = start_addr.first;
+            else {
+                LOG(ERR) << "Error occured while loading file " << input << std::endl;
+                return 1;
+            }
         }
         if(clim.count("reset")) {
             auto str = clim["reset"].as<std::string>();

src/sysc/register_tgc_c.cpp

@@ -62,12 +62,12 @@ using namespace sysc;
 volatile std::array<bool, 2> tgc_init = {
     iss_factory::instance().register_creator("tgc5c|m_p|llvm",
                                              [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+                                                 auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
                                                  auto* cpu = new sc_core_adapter<arch::riscv_hart_m_p<arch::tgc5c>>(cc);
                                                  return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
                                              }),
     iss_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned gdb_port, void* data) -> iss_factory::base_t {
-        auto cc = reinterpret_cast<sysc::tgfs::core_complex*>(data);
+        auto cc = reinterpret_cast<sysc::tgfs::core_complex_if*>(data);
         auto* cpu = new sc_core_adapter<arch::riscv_hart_mu_p<arch::tgc5c>>(cc);
         return {sysc::sc_cpu_ptr{cpu}, vm_ptr{create(static_cast<arch::tgc5c*>(cpu), gdb_port)}};
     })};

src/vm/asmjit/vm_tgc5c.cpp

@@ -4822,6 +4822,7 @@ void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
     cmp(cc, current_trap_state, 0);
     cc.jne(jh.trap_entry);
     cc.inc(get_ptr_for(jh, traits::ICOUNT));
+    cc.inc(get_ptr_for(jh, traits::CYCLE));
 }
 template <typename ARCH>
 void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){