fix MISA val

gen_input/TGC_D_XRB_NN.core_desc

@@ -127,7 +127,7 @@ Core TGC_D_XRB_NN provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_NN {
         XLEN=32;
         // definitions for the architecture wrapper
         //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
-        unsigned MISA_VAL = 0b01000000000000000001000100000100;
+        unsigned MISA_VAL = 0b01000000100100000011000100000100;
         unsigned MARCHID_VAL = 0x80000004;
     }
 }