1 Commits

Author SHA1 Message Date
d31b4ef5a8 fix MISA val 2021-11-11 12:58:57 +01:00

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@ -127,7 +127,7 @@ Core TGC_D_XRB_NN provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_NN {
XLEN=32;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned MISA_VAL = 0b01000000100100000011000100000100;
unsigned MARCHID_VAL = 0x80000004;
}
}