DBT-RISE/DBT-RISE-TGC
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base: DBT-RISE:3fd51cc68c4547cb1e89d56a2010ff3af0ff5e97
Branches Tags
DBT-RISE:main DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter
...
compare: DBT-RISE:346b177a87b8bfa9f3e895e63910f9c7cf7a1561
Branches Tags
DBT-RISE:develop DBT-RISE:featture/interp_instr_cache DBT-RISE:feature/privilege_refactor DBT-RISE:feature/htif DBT-RISE:feature/eve_checkin DBT-RISE:main DBT-RISE:feature/iss_factory DBT-RISE:feature/core_factory DBT-RISE:Trace_enhancement DBT-RISE:feature/reduced_output DBT-RISE:msvc_compat DBT-RISE:hotfix/latest_scc DBT-RISE:feature/interpreter

7 Commits
3fd51cc68c ... 346b177a87

Author SHA1 Message Date
Eyck Jentzsch
346b177a87 extends finishing conditions 2024-07-05 05:52:29 +02:00
stas
d4ec131fa7 change COUNT_LIMIT to ICOUNT_LIMIT 2024-07-04 10:46:24 +02:00
Eyck-Alexander Jentzsch
48370a4555 asmjit passes backend with new CoreDSL 2024-06-22 09:28:26 +02:00
Eyck-Alexander Jentzsch
36b076774e Merge branch 'develop' of https://git.minres.com/DBT-RISE/DBT-RISE-TGC into develop 2024-06-21 13:35:30 +02:00
Eyck-Alexander Jentzsch
482a4ec253 fixes semihosting callbacks in templates 2024-06-21 13:35:25 +02:00
Eyck Jentzsch
2fb28364c5 fixes remaining templates 2024-06-21 10:49:36 +02:00
Eyck Jentzsch
8460f4ab7f updates templates to re-enable interactive debugging of generator 2024-06-21 10:46:11 +02:00
9 changed files with 207 additions and 200 deletions
Expand all files Collapse all files

8
gen_input/templates/CORENAME.cpp.gtl
View File

@ -47,10 +47,10 @@ def getRegisterSizes(){
using namespace iss::arch;
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
constexpr std::array<const char*, ${registers.size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
constexpr std::array<const char*, ${registers.size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() = default;

8
gen_input/templates/CORENAME.h.gtl
View File

@ -75,10 +75,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static char const* const core_type = "${coreDef.name}";
static constexpr std::array<const char*, ${registers.size}> reg_names{
static constexpr std::array<const char*, ${registers.size()}> reg_names{
{"${registers.collect{it.name.toLowerCase()}.join('", "')}"}};
static constexpr std::array<const char*, ${registers.size}> reg_aliases{
static constexpr std::array<const char*, ${registers.size()}> reg_aliases{
{"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}};
enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}};
@ -99,10 +99,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, ${getRegisterSizes().size}> reg_bit_widths{
static constexpr std::array<const uint32_t, ${getRegisterSizes().size()}> reg_bit_widths{
{${getRegisterSizes().join(',')}}};
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size}> reg_byte_offsets{
static constexpr std::array<const uint32_t, ${getRegisterOffsets().size()}> reg_byte_offsets{
{${getRegisterOffsets().join(',')}}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);

8
gen_input/templates/asmjit/CORENAME.cpp.gtl
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2023 MINRES Technologies GmbH
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -129,7 +129,7 @@ private:
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
@ -363,7 +363,7 @@ volatile std::array<bool, 2> dummy = {
auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
@ -373,7 +373,7 @@ volatile std::array<bool, 2> dummy = {
auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};

21
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2021 MINRES Technologies GmbH
* Copyright (C) 20217-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -117,6 +117,8 @@ protected:
this->core.wait_until(type);
}
uint64_t fetch_count{0};
using yield_t = boost::coroutines2::coroutine<void>::push_type;
using coro_t = boost::coroutines2::coroutine<void>::pull_type;
std::vector<coro_t> spawn_blocks;
@ -160,7 +162,7 @@ private:
};
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
{${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
}};
@ -219,6 +221,7 @@ private:
});
}
}
typename arch::traits<ARCH>::opcode_e decode_instr(decoding_tree_node* node, code_word_t word){
if(!node->children.size()){
if(node->instrs.size() == 1) return node->instrs[0].op;
@ -268,8 +271,12 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
populate_decoding_tree(root);
}
inline bool is_count_limit_enabled(finish_cond_e cond){
return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
inline bool is_icount_limit_enabled(finish_cond_e cond){
return (cond & finish_cond_e::ICOUNT_LIMIT) == finish_cond_e::ICOUNT_LIMIT;
}
inline bool is_fcount_limit_enabled(finish_cond_e cond){
return (cond & finish_cond_e::FCOUNT_LIMIT) == finish_cond_e::FCOUNT_LIMIT;
}
inline bool is_jump_to_self_enabled(finish_cond_e cond){
@ -277,7 +284,7 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
}
template <typename ARCH>
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t count_limit){
auto pc=start;
auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
@ -290,7 +297,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
auto *const data = reinterpret_cast<uint8_t*>(&instr);
while(!this->core.should_stop() &&
!(is_count_limit_enabled(cond) && icount >= icount_limit)){
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
fetch_count++;
if(fetch_ins(pc, data)!=iss::Ok){
this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);

4
gen_input/templates/llvm/CORENAME.cpp.gtl
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -148,7 +148,7 @@ private:
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>

8
gen_input/templates/tcc/CORENAME.cpp.gtl
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2020 MINRES Technologies GmbH
* Copyright (C) 2020-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -148,7 +148,7 @@ private:
decoding_tree_node* root {nullptr};
const std::array<instruction_descriptor, ${instructions.size}> instr_descr = {{
const std::array<instruction_descriptor, ${instructions.size()}> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
/* instruction ${instr.instruction.name}, encoding '${instr.encoding}' */
{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
@ -334,7 +334,7 @@ volatile std::array<bool, 2> dummy = {
auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};
@ -344,7 +344,7 @@ volatile std::array<bool, 2> dummy = {
auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb);
}
return {cpu_ptr{cpu}, vm_ptr{vm}};

2
src/iss/arch/tgc5c.h
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File diff suppressed because one or more lines are too long

189
src/vm/asmjit/vm_tgc5c.cpp
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017, 2023 MINRES Technologies GmbH
* Copyright (C) 2017-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -339,7 +339,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -385,7 +385,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -431,7 +431,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){
@ -486,7 +486,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto addr_mask = (uint32_t)- 2;
@ -554,7 +554,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto label_merge = cc.newLabel();
@ -612,7 +612,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto label_merge = cc.newLabel();
@ -670,7 +670,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto label_merge = cc.newLabel();
@ -730,7 +730,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto label_merge = cc.newLabel();
@ -790,7 +790,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto label_merge = cc.newLabel();
@ -848,7 +848,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto label_merge = cc.newLabel();
@ -906,7 +906,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto load_address = gen_ext(jh,
@ -959,7 +959,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto load_address = gen_ext(jh,
@ -1012,7 +1012,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto load_address = gen_ext(jh,
@ -1065,7 +1065,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto load_address = gen_ext(jh,
@ -1117,7 +1117,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto load_address = gen_ext(jh,
@ -1169,7 +1169,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto store_address = gen_ext(jh,
@ -1217,7 +1217,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto store_address = gen_ext(jh,
@ -1265,7 +1265,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto store_address = gen_ext(jh,
@ -1313,7 +1313,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1362,7 +1362,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1424,7 +1424,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1485,7 +1485,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1533,7 +1533,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1581,7 +1581,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1629,7 +1629,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1677,7 +1677,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1725,7 +1725,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1733,7 +1733,7 @@ private:
gen_ext(jh,
(gen_operation(jh, sar, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), shamt)
), 32, true));
), 32, false));
}
}
auto returnValue = CONT;
@ -1775,7 +1775,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1824,7 +1824,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1873,7 +1873,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1922,7 +1922,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -1985,7 +1985,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -2046,7 +2046,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -2094,7 +2094,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -2143,7 +2143,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -2194,7 +2194,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -2242,7 +2242,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -2471,7 +2471,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1);
@ -2524,7 +2524,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
@ -2577,7 +2577,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
@ -2630,7 +2630,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
@ -2679,7 +2679,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
@ -2731,7 +2731,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
@ -2822,16 +2822,13 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto res = gen_ext(jh,
(gen_operation(jh, imul, gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true))
), 64, true);
auto res = gen_operation(jh, imul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true))
;
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
@ -2877,16 +2874,13 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto res = gen_ext(jh,
(gen_operation(jh, imul, gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true))
), 64, true);
auto res = gen_operation(jh, imul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true))
;
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
@ -2933,15 +2927,12 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto res = gen_ext(jh,
(gen_operation(jh, imul, gen_ext(jh,
gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 64, false))
), 64, true);
auto res = gen_operation(jh, imul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), load_reg_from_mem(jh, traits::X0 + rs2))
;
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
@ -2988,14 +2979,12 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto res = gen_ext(jh,
(gen_operation(jh, mul, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 64, false))
), 64, false);
auto res = gen_operation(jh, mul,
load_reg_from_mem(jh, traits::X0 + rs1),
load_reg_from_mem(jh, traits::X0 + rs2));
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
@ -3042,13 +3031,13 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto dividend = gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, false);
load_reg_from_mem(jh, traits::X0 + rs1), 32, true);
auto divisor = gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, false);
load_reg_from_mem(jh, traits::X0 + rs2), 32, true);
if(rd!=0){
auto label_merge = cc.newLabel();
cc.cmp(gen_operation(jh, ne, divisor, 0)
@ -3126,7 +3115,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto label_merge = cc.newLabel();
@ -3137,9 +3126,8 @@ private:
{
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
(gen_operation(jh, div, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
), 32, false));
gen_operation(jh, div, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
);
}
}
cc.jmp(label_merge);
@ -3191,7 +3179,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto label_merge = cc.newLabel();
@ -3223,9 +3211,9 @@ private:
cc.mov(get_ptr_for(jh, traits::X0+ rd),
gen_ext(jh,
(gen_operation(jh, srem, gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, false))
), 32, true));
load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh,
load_reg_from_mem(jh, traits::X0 + rs2), 32, true))
), 32, false));
}
}
cc.bind(label_merge);
@ -3279,7 +3267,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto label_merge = cc.newLabel();
@ -3348,7 +3336,7 @@ private:
), 32, false));
}
else{
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
auto returnValue = CONT;
@ -3476,7 +3464,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rs1!=0){
@ -3600,7 +3588,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -3646,7 +3634,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(imm==0||rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd),
@ -3695,7 +3683,7 @@ private:
), 32, true));
}
else{
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
auto returnValue = CONT;
@ -3732,7 +3720,7 @@ private:
gen_instr_prologue(jh);
cc.comment("//behavior:");
/*generate behavior*/
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
auto returnValue = CONT;
gen_instr_epilogue(jh);
@ -4199,7 +4187,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rs1!=0){
@ -4246,7 +4234,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)||rd==0){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto offs = gen_ext(jh,
@ -4295,7 +4283,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -4421,7 +4409,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rd>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
if(rd!=0){
@ -4468,7 +4456,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs1>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto new_pc = load_reg_from_mem(jh, traits::X0 + rs1);
@ -4552,7 +4540,7 @@ private:
cc.comment("//behavior:");
/*generate behavior*/
if(rs2>=static_cast<uint32_t>(traits::RFS)){
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
}
else{
auto offs = gen_ext(jh,
@ -4595,7 +4583,7 @@ private:
gen_instr_prologue(jh);
cc.comment("//behavior:");
/*generate behavior*/
gen_raise(jh, 0, 2);
gen_raise(jh, 0, static_cast<int32_t>(traits::RV_CAUSE_ILLEGAL_INSTRUCTION));
auto returnValue = CONT;
gen_instr_epilogue(jh);
@ -4616,7 +4604,8 @@ private:
gen_instr_epilogue(jh);
this->gen_sync(jh, POST_SYNC, instr_descr.size());
return BRANCH;
}
}
//decoding functionality
void populate_decoding_tree(decoding_tree_node* root){

159
src/vm/interp/vm_tgc5c.cpp
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2021 MINRES Technologies GmbH
* Copyright (C) 20217-2024 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -113,6 +113,8 @@ protected:
this->core.wait_until(type);
}
uint64_t fetch_count{0};
using yield_t = boost::coroutines2::coroutine<void>::push_type;
using coro_t = boost::coroutines2::coroutine<void>::pull_type;
std::vector<coro_t> spawn_blocks;
@ -299,6 +301,7 @@ private:
});
}
}
typename arch::traits<ARCH>::opcode_e decode_instr(decoding_tree_node* node, code_word_t word){
if(!node->children.size()){
if(node->instrs.size() == 1) return node->instrs[0].op;
@ -348,8 +351,12 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
populate_decoding_tree(root);
}
inline bool is_count_limit_enabled(finish_cond_e cond){
return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT;
inline bool is_icount_limit_enabled(finish_cond_e cond){
return (cond & finish_cond_e::ICOUNT_LIMIT) == finish_cond_e::ICOUNT_LIMIT;
}
inline bool is_fcount_limit_enabled(finish_cond_e cond){
return (cond & finish_cond_e::FCOUNT_LIMIT) == finish_cond_e::FCOUNT_LIMIT;
}
inline bool is_jump_to_self_enabled(finish_cond_e cond){
@ -357,7 +364,7 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
}
template <typename ARCH>
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t count_limit){
auto pc=start;
auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
@ -370,7 +377,9 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
auto *const data = reinterpret_cast<uint8_t*>(&instr);
while(!this->core.should_stop() &&
!(is_count_limit_enabled(cond) && icount >= icount_limit)){
!(is_icount_limit_enabled(cond) && icount >= count_limit) &&
!(is_fcount_limit_enabled(cond) && fetch_count >= count_limit)){
fetch_count++;
if(fetch_ins(pc, data)!=iss::Ok){
this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
@ -399,7 +408,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -425,7 +434,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -451,7 +460,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(imm % traits::INSTR_ALIGNMENT) {
@ -485,7 +494,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t addr_mask = (uint32_t)- 2;
@ -521,7 +530,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) == *(X+rs2)) {
@ -554,7 +563,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) != *(X+rs2)) {
@ -587,7 +596,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) {
@ -620,7 +629,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) {
@ -653,7 +662,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) < *(X+rs2)) {
@ -686,7 +695,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs1) >= *(X+rs2)) {
@ -719,7 +728,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -750,7 +759,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -781,7 +790,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -812,7 +821,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -843,7 +852,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -874,7 +883,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -901,7 +910,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -928,7 +937,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
@ -955,7 +964,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -982,7 +991,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1009,7 +1018,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1036,7 +1045,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1063,7 +1072,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1090,7 +1099,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1117,7 +1126,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1144,7 +1153,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1171,11 +1180,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt);
*(X+rd) = ((uint32_t)((int32_t)*(X+rs1) >> shamt));
}
}
}
@ -1198,7 +1207,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1225,7 +1234,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1252,7 +1261,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1279,7 +1288,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1306,7 +1315,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1333,7 +1342,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1360,7 +1369,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1387,7 +1396,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1414,7 +1423,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1441,7 +1450,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -1542,7 +1551,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t xrs1 = *(X+rs1);
@ -1579,7 +1588,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_33 = super::template read_mem<uint32_t>(traits::CSR, csr);
@ -1614,7 +1623,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_34 = super::template read_mem<uint32_t>(traits::CSR, csr);
@ -1649,7 +1658,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_35 = super::template read_mem<uint32_t>(traits::CSR, csr);
@ -1681,7 +1690,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_36 = super::template read_mem<uint32_t>(traits::CSR, csr);
@ -1715,7 +1724,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t res_37 = super::template read_mem<uint32_t>(traits::CSR, csr);
@ -1739,7 +1748,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence.i"),
fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
@ -1769,7 +1778,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) );
@ -1797,7 +1806,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) );
@ -1825,7 +1834,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)(*(X+rs2) );
@ -1853,7 +1862,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint64_t res = (uint64_t)(*(X+rs1) ) * (uint64_t)(*(X+rs2) );
@ -1881,7 +1890,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
int32_t dividend = (int32_t)*(X+rs1);
@ -1921,7 +1930,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs2) != 0) {
@ -1955,7 +1964,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs2) != 0) {
@ -1997,7 +2006,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(*(X+rs2) != 0) {
@ -2033,7 +2042,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(imm ));
}
else {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
}
break;
@ -2099,7 +2108,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rs1 != 0) {
@ -2113,7 +2122,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "c__nop");
this->core.disass_output(pc.val, "c.nop");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@ -2158,7 +2167,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -2184,7 +2193,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(imm == 0 || rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
if(rd != 0) {
*(X+rd) = (uint32_t)((int32_t)sext<18>(imm));
@ -2210,7 +2219,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*(X+2) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)((int16_t)sext<10>(nzimm) ));
}
else {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
}
break;
@ -2219,13 +2228,13 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "__reserved_clui");
this->core.disass_output(pc.val, ".reserved_clui");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
// execute instruction
{
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
break;
}// @suppress("No break at end of case")
@ -2447,7 +2456,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rs1 != 0) {
@ -2473,7 +2482,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS || rd == 0) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
@ -2500,7 +2509,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -2537,7 +2546,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::__reserved_cmv: {
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "__reserved_cmv");
this->core.disass_output(pc.val, ".reserved_cmv");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@ -2563,7 +2572,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rd >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
if(rd != 0) {
@ -2588,7 +2597,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs1 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t new_pc = *(X+rs1);
@ -2602,7 +2611,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
case arch::traits<ARCH>::opcode_e::C__EBREAK: {
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "c__ebreak");
this->core.disass_output(pc.val, "c.ebreak");
}
// used registers// calculate next pc value
*NEXT_PC = *PC + 2;
@ -2628,7 +2637,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction
{
if(rs2 >= traits::RFS) {
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
else {
uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
@ -2647,7 +2656,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2;
// execute instruction
{
raise(0, 2);
raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
}
break;
}// @suppress("No break at end of case")