simplify spawn block handling

CMakeLists.txt

@@ -36,6 +36,8 @@ set(LIB_SOURCES
     src/vm/fp_functions.cpp
     src/plugin/instruction_count.cpp
     src/plugin/cycle_estimate.cpp
+    src/plugin/cov.cpp
+    
     ${TGC_SOURCES}
     ${TGC_VM_SOURCES}
 )

gen_input/templates/interp/CORENAME.cpp.gtl

@@ -181,6 +181,15 @@ protected:
         auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     }
+    
+    inline void process_spawn_blocks() {
+        for(auto it = std::begin(spawn_blocks); it!=std::end(spawn_blocks);)
+             if(*it){
+                 (*it)();
+                 ++it;
+             } else
+                 spawn_blocks.erase(it);
+    }
 <%functions.each{ it.eachLine { %>
     ${it}<%}%>
 <%}%>
@@ -226,7 +235,7 @@ private:
         <%instr.behavior.eachLine{%>${it}
         <%}%>} catch(...){}
         // post execution stuff
-        for(auto& spawn_block:spawn_blocks) spawn_block();
+        process_spawn_blocks();
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
         // trap check
         if(*trap_state!=0){

incl/iss/arch/riscv_hart_m_p.h

@@ -233,11 +233,11 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        virtual uint64_t get_pc() { return arch.get_pc(); };
+        uint64_t get_pc() override { return arch.get_pc(); };
 
-        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
+        uint64_t get_next_pc() override { return arch.get_next_pc(); };
 
-        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
+        void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
 
         riscv_hart_m_p<BASE, FEAT> &arch;
     };

incl/iss/arch/riscv_hart_msu_vp.h

@@ -293,16 +293,16 @@ public:
 
     std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
 
-    virtual phys_addr_t virt2phys(const iss::addr_t &addr) override;
+    phys_addr_t virt2phys(const iss::addr_t &addr) override;
 
     iss::status read(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, uint8_t *const data) override;
     iss::status write(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
+    uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
+    uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    virtual uint64_t leave_trap(uint64_t flags) override;
+    uint64_t leave_trap(uint64_t flags) override;
     void wait_until(uint64_t flags) override;
 
     void disass_output(uint64_t pc, const std::string instr) override {

incl/iss/arch/riscv_hart_mu_p.h

@@ -207,9 +207,9 @@ public:
     iss::status write(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, fault_data, fault_data); }
+    uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, fault_data, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
+    uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    virtual uint64_t leave_trap(uint64_t flags) override;
+    uint64_t leave_trap(uint64_t flags) override;
 
     const reg_t& get_mhartid() const { return mhartid_reg;	}
 	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };

incl/iss/arch/tgc_c.h

@@ -217,7 +217,7 @@ struct tgc_c: public arch_if {
 
     inline uint32_t get_last_branch() { return reg.last_branch; }
 
-protected:
+
 #pragma pack(push, 1)
     struct TGC_C_regs { 
         uint32_t X0 = 0; 

incl/iss/plugin/cov.h

@@ -0,0 +1,84 @@
+/*******************************************************************************
+ * Copyright (C) 2017, 2018, MINRES Technologies GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Contributors:
+ *       eyck@minres.com - initial API and implementation
+ ******************************************************************************/
+
+#ifndef _ISS_PLUGIN_COV_H_
+#define _ISS_PLUGIN_COV_H_
+
+#include <iss/vm_plugin.h>
+#include "iss/instrumentation_if.h"
+#include <json/json.h>
+#include <string>
+#include <fstream>
+
+
+namespace iss {
+namespace plugin {
+
+class cov : public iss::vm_plugin {
+    struct instr_delay {
+        std::string instr_name;
+        size_t size;
+        size_t not_taken_delay;
+        size_t taken_delay;
+    };
+
+public:
+
+    cov(const cov &) = delete;
+
+    cov(const cov &&) = delete;
+
+    cov();
+
+    virtual ~cov();
+
+    cov &operator=(const cov &) = delete;
+
+    cov &operator=(const cov &&) = delete;
+
+    bool registration(const char *const version, vm_if &arch) override;
+
+    sync_type get_sync() override { return POST_SYNC; };
+
+    void callback(instr_info_t, exec_info const&) override;
+
+private:
+    iss::instrumentation_if *instr_if  {nullptr};
+    int counter {0};
+    std::ofstream output;
+};
+}
+}
+
+#endif /* _ISS_PLUGIN_COV_H_ */

src/plugin/cov.cpp

@@ -0,0 +1,32 @@
+#include <iss/plugin/cov.h>
+#include <iss/arch_if.h>
+#include <iostream>
+
+
+iss::plugin::cov::cov() {
+    std::cout << "Entering Constructor"<<std::endl;
+    output.open("output.txt");
+
+}
+
+iss::plugin::cov::~cov() {
+    std::cout << "Entering Destructor"<<std::endl;
+    output.close();
+
+
+}
+
+bool iss::plugin::cov::registration(const char *const version, vm_if& vm) {
+    instr_if = vm.get_arch()->get_instrumentation_if();
+    return true;
+}
+void iss::plugin::cov::callback(instr_info_t iinfo, const exec_info&) {
+//    if((instr_if->get_next_pc() - instr_if->get_pc() != 4) ||( instr_if->get_next_pc() - instr_if->get_pc() != 2)){
+//        std::cout << "jump from " << std::hex << instr_if->get_pc() << " to " << instr_if->get_next_pc()<< " after " << std::dec << counter <<" linear instructions" <<std::endl;
+//        counter = 0;
+//    }else {
+//        counter++;
+//    }
+
+    output<<std::hex << instr_if->get_pc() << std::endl;
+}

src/sysc/core_complex.cpp

@@ -69,6 +69,8 @@ using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_n
 #include <array>
 #include <iss/plugin/cycle_estimate.h>
 #include <iss/plugin/instruction_count.h>
+#include <iss/plugin/cov.h>
+
 // clang-format on
 
 #define STR(X) #X
@@ -423,6 +425,10 @@ void core_complex::before_end_of_elaboration() {
                 auto *plugin = new iss::plugin::cycle_estimate(filename);
                 cpu->vm->register_plugin(*plugin);
                 plugin_list.push_back(plugin);
+            } else if (plugin_name == "cov") {
+                auto *plugin = new iss::plugin::cov();
+                cpu->vm->register_plugin(*plugin);
+                plugin_list.push_back(plugin);
             } else {
                 std::array<char const*, 1> a{{filename.c_str()}};
                 iss::plugin::loader l(plugin_name, {{"initPlugin"}});