remove unneeded constants

CMakeLists.txt

@@ -60,7 +60,7 @@ endif()
 
 target_compile_options(${PROJECT_NAME} PRIVATE -Wno-shift-count-overflow)
 target_include_directories(${PROJECT_NAME} PUBLIC incl)
-target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util)
+target_link_libraries(${PROJECT_NAME} PUBLIC softfloat scc-util jsoncpp)
 target_link_libraries(${PROJECT_NAME} PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
 target_link_libraries(${PROJECT_NAME} PUBLIC ${Boost_LIBRARIES} )
 set_target_properties(${PROJECT_NAME} PROPERTIES

incl/iss/arch/riscv_hart_m_p.h

@@ -309,8 +309,6 @@ public:
 
         T satp;
 
-        static constexpr T get_misa() { return (1UL << 30) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
-
         static constexpr uint32_t get_mask() {
             return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011  // only machine mode is supported
         }
@@ -434,10 +432,8 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
 : state()
 , cycle_offset(0)
 , instr_if(*this) {
-    csr[misa] = hart_state<reg_t>::get_misa();
+    csr[misa] = traits<BASE>::MISA_VAL;
     uart_buf.str("");
-    // read-only registers
-    csr_wr_cb[misa] = nullptr;
     for (unsigned addr = mcycle; addr <= hpmcounter31; ++addr) csr_wr_cb[addr] = nullptr;
     for (unsigned addr = mcycleh; addr <= hpmcounter31h; ++addr) csr_wr_cb[addr] = nullptr;
     // special handling
@@ -462,6 +458,9 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
         csr_rd_cb[addr] = &riscv_hart_m_p<BASE>::read_reg;
         csr_wr_cb[addr] = &riscv_hart_m_p<BASE>::write_reg;
     }
+    // read-only registers
+    csr_rd_cb[misa] = &riscv_hart_m_p<BASE>::read_reg;
+    csr_wr_cb[misa] = nullptr;
 }
 
 template <typename BASE> std::pair<uint64_t, bool> riscv_hart_m_p<BASE>::load_file(std::string name, int type) {
@@ -894,7 +893,10 @@ template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
 
     if (enabled_interrupts != 0) {
         int res = 0;
-        while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
+        while ((enabled_interrupts & 1) == 0) {
+        	enabled_interrupts >>= 1;
+        	res++;
+        }
         this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
     }
 }
@@ -946,20 +948,7 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
 }
 
 template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flags) {
-    /* TODO: configurable support of User mode
-    auto cur_priv = this->reg.PRIV;
-    auto inst_priv = flags & 0x3;
-    auto status = state.mstatus;
-
-    // pop the relevant lower-privilege interrupt enable and privilege mode stack
-    // clear respective yIE
-    if (inst_priv == PRIV_M) {
-        this->reg.PRIV = state.mstatus.MPP;
-        state.mstatus.MPP = 0; // clear mpp to U mode
     state.mstatus.MIE = state.mstatus.MPIE;
-    } else {
-    	CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
-    }*/
     // sets the pc to the value stored in the x epc register.
     this->reg.NEXT_PC = csr[mepc];
     CLOG(INFO, disass) << "Executing xRET";

incl/iss/arch/tgf_c.h

@@ -53,7 +53,7 @@ template <> struct traits<tgf_c> {
     static constexpr std::array<const char*, 35> reg_aliases{
         {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}};
 
-    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, eei_aligned_addresses=1, MUL_LEN=64};
+    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b01000000000000000001000100000100, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, eei_aligned_addresses=1, MUL_LEN=64};
 
     constexpr static unsigned FP_REGS_SIZE = 0;
 

incl/iss/debugger/riscv_target_adapter.h

@@ -183,7 +183,8 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
     data.clear();
     avail.clear();
     const uint8_t *reg_base = core->get_regs_base_ptr();
-    for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
+    auto start_reg=arch::traits<ARCH>::X0;
+    for (size_t reg_no = start_reg; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
         auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
         unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
         for (size_t j = 0; j < reg_width; ++j) {
@@ -210,11 +211,11 @@ status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, st
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
-    auto reg_count = arch::traits<ARCH>::NUM_REGS;
+    auto start_reg=arch::traits<ARCH>::X0;
     auto *reg_base = core->get_regs_base_ptr();
     auto iter = data.data();
-    for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) {
-        auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
+    for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits<ARCH>::NUM_REGS*/; ++reg_no) {
+        auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
         auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
         std::copy(iter, iter + reg_width, reg_base);
         iter += 4;

incl/sysc/core_complex.h

@@ -33,10 +33,10 @@
 #ifndef _SYSC_SIFIVE_FE310_H_
 #define _SYSC_SIFIVE_FE310_H_
 
-#include "scc/initiator_mixin.h"
+#include "tlm/scc/initiator_mixin.h"
 #include "scc/traceable.h"
 #include "scc/utilities.h"
-#include "scv4tlm/tlm_rec_initiator_socket.h"
+#include "tlm/scc/scv/tlm_rec_initiator_socket.h"
 #include <cci_configuration>
 #include <tlm>
 #include <tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h>
@@ -75,7 +75,7 @@ class core_wrapper;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator{"intor"};
+    tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
 
     sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 

src/sysc/core_complex.cpp

@@ -191,6 +191,8 @@ public:
         } else
             this->csr[arch::mip] &= ~mask;
         this->check_interrupt();
+        if(value)
+            SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap;
     }
 
 private:
@@ -391,7 +393,7 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
             if (is_fetch && tr_handle.is_active()) {
                 tr_handle.end_transaction();
             }
-            auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(tr_handle, this);
             gp.set_extension(preExt);
         }
 #endif
@@ -437,7 +439,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
         sc_time delay{quantum_keeper.get_local_time()};
 #ifdef WITH_SCV
         if (m_db != nullptr && tr_handle.is_valid()) {
-            auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
+            auto preExt = new tlm::scc::scv::tlm_recording_extension(tr_handle, this);
             gp.set_extension(preExt);
         }
 #endif