fix stand-alone ISS compilation to include all generated cores

CMakeLists.txt

@@ -28,15 +28,15 @@ endif()
 add_subdirectory(softfloat)
 
 # library files
-FILE(GLOB TGC_SOURCES
+FILE(GLOB TGC_SOURCES    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp) 
-    ${CMAKE_CURRENT_SOURCE_DIR}/src/iss/*.cpp 
+FILE(GLOB TGC_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp)
-    ${CMAKE_CURRENT_SOURCE_DIR}/src/vm/interp/vm_*.cpp
+
-)
 set(LIB_SOURCES 
     src/vm/fp_functions.cpp
     src/plugin/instruction_count.cpp
     src/plugin/cycle_estimate.cpp
     ${TGC_SOURCES}
+    ${TGC_VM_SOURCES}
 )
 
 if(WITH_LLVM)
@@ -105,8 +105,12 @@ project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)
 
 add_executable(${PROJECT_NAME} src/main.cpp)
-# This sets the include directory for the reference project. This is the -I flag in gcc.
+foreach(F IN LISTS TGC_SOURCES)
-target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+    string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+    string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
+    target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+endforeach()
+
 if(WITH_LLVM)
     target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
     target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
@@ -142,15 +146,11 @@ if(SystemC_FOUND)
     add_library(${PROJECT_NAME} src/sysc/core_complex.cpp)
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
     target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_b.h)
+    foreach(F IN LISTS TGC_SOURCES)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_B)
+        string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
-    endif()
+        string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_c.h)
+        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_C)
+    endforeach()
-    endif()
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss/arch/tgc_d.h)
-        target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_TGC_D)
-    endif()
     target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc)
     if(WITH_LLVM)
         target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})

gen_input/templates/CORENAME_cyles.txt.gtl

@@ -1,9 +1,9 @@
-{ 
+{
 	"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
 		{
 			"name"  : "${instr.name}",
 			"size"  : ${instr.length},
-			"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
+			"delay" : ${instr.isConditional?"[1,1]":"1"}
 		}<%}%>
 	]
 }

incl/iss/arch/riscv_hart_mu_p.h

@@ -330,6 +330,7 @@ protected:
     iss::status write_dcsr_reg(unsigned addr, reg_t val);
     iss::status read_dpc_reg(unsigned addr, reg_t &val);
     iss::status write_dpc_reg(unsigned addr, reg_t val);
+    iss::status write_pmpcfg_reg(unsigned addr, reg_t val);
 
     reg_t mhartid_reg{0x0};
     std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
@@ -425,7 +426,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
         }
         for(size_t i=pmpcfg0; i<=pmpcfg3; ++i){
             csr_rd_cb[i] = &this_class::read_csr_reg;
-            csr_wr_cb[i] = &this_class::write_csr_reg;
+            csr_wr_cb[i] = &this_class::write_pmpcfg_reg;
         }
     }
     if(FEAT & FEAT_EXT_N){
@@ -544,6 +545,12 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
     throw std::runtime_error("memory load file not found");
 }
 
+template<typename BASE, features_e FEAT>
+inline iss::status riscv_hart_mu_p<BASE, FEAT>::write_pmpcfg_reg(unsigned addr, reg_t val) {
+    csr[addr] = val & 0x9f9f9f9f;
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_check(const access_type type, const uint64_t addr, const unsigned len) {
     constexpr auto PMP_SHIFT=2U;
     constexpr auto PMP_R = 0x1U;
@@ -574,7 +581,7 @@ template <typename BASE, features_e FEAT> bool riscv_hart_mu_p<BASE, FEAT>::pmp_
             for (reg_t offset = 0; offset < len; offset += 1 << PMP_SHIFT) {
                 reg_t cur_addr = addr + offset;
                 auto napot_match = ((cur_addr ^ tor) & mask) == 0;
-                auto tor_match = base <= cur_addr && cur_addr < tor;
+                auto tor_match = base <= (cur_addr+len-1) && cur_addr < tor;
                 auto match = is_tor ? tor_match : napot_match;
                 any_match |= match;
                 all_match &= match;

src/main.cpp

@@ -54,6 +54,16 @@ using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, (iss::arch:
 #include "iss/arch/tgc_d_xrb_mac.h"
 using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
 #endif
+#ifdef CORE_TGC_D_XRB_NN
+#include "iss/arch/riscv_hart_mu_p.h"
+#include "iss/arch/tgc_d_xrb_nn.h"
+using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
+#ifdef CORE_TGC_E
+#include "iss/arch/riscv_hart_mu_p.h"
+#include "iss/arch/tgc_e.h"
+using tgc_e_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_e, (iss::arch::features_e)(iss::arch::FEAT_PMP | iss::arch::FEAT_CLIC | iss::arch::FEAT_EXT_N)>;
+#endif
 #ifdef WITH_LLVM
 #include <iss/llvm/jit_helper.h>
 #endif
@@ -153,9 +163,21 @@ int main(int argc, char *argv[]) {
             std::tie(cpu, vm) =
                 iss::create_cpu<tgc_d_xrb_mac_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
         } else
+#endif
+#ifdef CORE_TGC_D_XRB_NN
+        if (isa_opt == "tgc_d_xrb_nn") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_d_xrb_nn_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
+#endif
+#ifdef CORE_TGC_E
+        if (isa_opt == "tgc_e") {
+            std::tie(cpu, vm) =
+                iss::create_cpu<tgc_e_plat_type>(clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+        } else
 #endif
         {
-            LOG(ERR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
+            LOG(ERR) << "Illegal argument value for '--isa': " << isa_opt << std::endl;
             return 127;
         }
         if (clim.count("plugin")) {

src/sysc/core_complex.cpp

@@ -57,6 +57,11 @@ using tgc_d_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d, iss::arch::
 #include "iss/arch/tgc_d_xrb_mac.h"
 using tgc_d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_mac, iss::arch::FEAT_PMP>;
 #endif
+#ifdef CORE_TGC_D_XRB_NN
+#include "iss/arch/riscv_hart_mu_p.h"
+#include "iss/arch/tgc_d_xrb_nn.h"
+using tgc_d_xrb_nn_plat_type = iss::arch::riscv_hart_mu_p<iss::arch::tgc_d_xrb_nn, iss::arch::FEAT_PMP>;
+#endif
 #include <scc/report.h>
 #include <util/ities.h>
 #include <iostream>
@@ -303,8 +308,11 @@ public:
 #ifdef CORE_TGC_D
         CREATE_CORE(tgc_d)
 #endif
-#ifdef CORE_TGC_D_XRB_MACD
+#ifdef CORE_TGC_D_XRB_MAC
         CREATE_CORE(tgc_d_xrb_mac)
+#endif
+#ifdef CORE_TGC_D_XRB_NN
+        CREATE_CORE(tgc_d_xrb_nn)
 #endif
         {
             LOG(ERR) << "Illegal argument value for core type: " << type << std::endl;