 Eyck Jentzsch
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d78fcc48e5
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use marchid in platform
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2021-09-30 19:27:03 +02:00 |
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Eyck Jentzsch
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ba9339a50d
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fix MPP reset value, PMP inactive in U-mode handling and MRET in U-mode
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2021-09-21 16:52:40 +02:00 |
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Eyck Jentzsch
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9c8b72693e
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correct trap ids of access faults
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2021-08-20 09:02:56 +02:00 |
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Eyck Jentzsch
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2f05083cf0
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fix elf loader and pmp check for debug accesses
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2021-08-19 10:50:25 +02:00 |
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Eyck Jentzsch
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836ba269e3
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fix clic reset values
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2021-08-16 15:05:05 +02:00 |
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Eyck Jentzsch
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adeffe47ad
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fix behavior of riscv_hart_mu_p to match TGC_D
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2021-08-12 20:34:10 +02:00 |
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Eyck Jentzsch
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d95846a849
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fix trap handling if illegal fetch (PMP) and U-mode CSRs
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2021-08-01 17:23:22 +02:00 |
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Eyck Jentzsch
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af887c286f
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fix for #2
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2021-07-28 09:09:08 +02:00 |
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Eyck Jentzsch
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d7bddd825c
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add clic CSRs
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2021-07-27 10:47:48 +02:00 |
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Eyck Jentzsch
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d0f3a120fd
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fix naming in MU wrapper
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2021-07-19 16:26:23 +02:00 |
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Eyck Jentzsch
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473f8a5a17
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fix privilege behavior
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2021-07-07 11:30:00 +02:00 |
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Eyck Jentzsch
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2f4b5bd9b2
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fix detailed behavior of TGC_C
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2021-07-06 21:19:36 +02:00 |
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Eyck Jentzsch
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23b9741adf
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refine and fix TGC_C iss to becoem compliant
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2021-06-29 11:51:30 +02:00 |
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Eyck Jentzsch
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5d8da08ce5
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fix linker issue
the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
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2021-06-26 14:30:36 +02:00 |
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Eyck Jentzsch
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aaceecd5dc
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fix mu_p platform features and CSRs
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2021-05-17 09:20:09 +02:00 |
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Eyck Jentzsch
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a35974c9f5
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make cpu type in core_complex configurable
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2021-05-16 15:06:42 +02:00 |
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Eyck Jentzsch
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9c456ba8f2
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initial version of MU hart
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2021-05-14 13:29:39 +02:00 |