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aa70d8a54a
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fixes CLIC to match clicinfo description in CLIC spec 11.04.2023
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2023-05-02 17:22:13 +02:00 |
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d990f1cf5d
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fixes reading of 64bit CSR register
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2023-05-01 22:23:35 +02:00 |
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1672b01e62
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adds WT cache functionality as mixin
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2023-04-28 20:38:07 +02:00 |
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00b0f101ac
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adapts to changes of instrumentation interface in dbt-rise-core
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2023-04-28 20:38:07 +02:00 |
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f626ee2684
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fixes privilege wrapper for M/U to cope with 64bit
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2023-04-05 15:38:25 +02:00 |
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98dd329833
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fixes CSR access rights
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2023-04-04 09:23:08 +02:00 |
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6213445bc4
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fixes 64bit behavior of CSR regs
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2023-03-27 12:04:43 +02:00 |
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7efa924510
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fixes m/uintstatus read
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2023-03-17 10:51:39 +01:00 |
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febbc4fff0
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fixes m/uintstatus read
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2023-03-17 10:23:05 +01:00 |
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39b2788b7e
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implements and fixes CLIC CSR behavior
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2023-03-17 09:09:09 +01:00 |
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a943dd3bdf
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fixes wrong array size which led to unintended CSR definitions
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2023-03-15 14:16:08 +01:00 |
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fedbff5971
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fixes xcause and u-mode clic CSRs
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2023-03-15 12:27:39 +01:00 |
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c2758e8321
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removes mscratchcsw from CLIC feature
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2023-03-15 09:07:00 +01:00 |
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3f7ce41b9d
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fixes CLIC mtvt register behavior
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2023-03-11 14:03:03 +01:00 |
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ad1cbedf00
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adds back missing max irq functions
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2023-03-11 12:47:10 +01:00 |
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83f54b5074
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fixes CLICCFG settings
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2023-03-11 08:48:03 +01:00 |
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a83928fd8c
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fixes CSR/CLIC implementation
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2023-03-10 20:40:21 +01:00 |
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62c118e501
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fixes CSR to match latest fast interrupts spec
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2023-01-20 16:21:04 +01:00 |
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a977200284
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cleans up priv wrappers
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2022-10-05 08:58:57 +02:00 |
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ad7bb28b4c
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fixes write mask of clic memory mapped registers
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2022-09-17 12:15:19 +02:00 |
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57347ae4d9
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fixes cppcheck flagged issues
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2022-07-23 13:49:10 +02:00 |
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966d1616c5
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change source code to unified layout
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2022-05-21 11:55:24 +02:00 |
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