DBT-RISE/DBT-RISE-TGC
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replaces virtual functions with memory pointers (kind of)

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This commit is contained in:
Eyck Jentzsch 2025-03-11 08:31:25 +01:00
parent 57d5ea92be
commit fb0f6255e9
5 changed files with 26 additions and 11 deletions
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15
src/iss/arch/riscv_hart_common.h
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@ -348,6 +348,9 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
using reg_t = typename core::reg_t;
using addr_t = typename core::addr_t;
using rd_csr_f = std::function<iss::status(unsigned addr, reg_t&)>;
using wr_csr_f = std::function<iss::status(unsigned addr, reg_t)>;
#define MK_CSR_RD_CB(FCT) [this](unsigned a, reg_t& r) -> iss::status { return this->FCT(a, r); };
#define MK_CSR_WR_CB(FCT) [this](unsigned a, reg_t r) -> iss::status { return this->FCT(a, r); };
@ -530,8 +533,14 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
this->reg.cycle + cycle_offset);
};
void register_custom_csr_rd(unsigned addr) { csr_rd_cb[addr] = &this_class::read_custom_csr; }
void register_custom_csr_wr(unsigned addr) { csr_wr_cb[addr] = &this_class::write_custom_csr; }
void register_csr(unsigned addr, rd_csr_f f) { csr_rd_cb[addr] = f; }
void register_csr(unsigned addr, wr_csr_f f) { csr_wr_cb[addr] = f; }
void register_csr(unsigned addr, rd_csr_f rdf, wr_csr_f wrf) {
csr_rd_cb[addr] = rdf;
csr_wr_cb[addr] = wrf;
}
void unregister_csr_rd(unsigned addr) { csr_rd_cb.erase(addr); }
void unregister_csr_wr(unsigned addr) { csr_wr_cb.erase(addr); }
bool debug_mode_active() { return this->reg.PRIV & 0x4; }
@ -777,8 +786,6 @@ protected:
using csr_page_type = typename csr_type::page_type;
csr_type csr;
using rd_csr_f = std::function<iss::status(unsigned addr, reg_t&)>;
using wr_csr_f = std::function<iss::status(unsigned addr, reg_t)>;
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;

7
src/iss/arch/riscv_hart_m_p.h
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@ -232,9 +232,9 @@ public:
void reset(uint64_t address) override;
iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
uint8_t* const data) override;
uint8_t* const data);
iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
const uint8_t* const data) override;
const uint8_t* const data);
uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, this->fault_data, this->fault_data); }
uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
@ -316,6 +316,9 @@ template <typename BASE, features_e FEAT, typename LOGCAT>
riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
: state()
, cfg(cfg) {
this->rd_func = util::delegate<arch_if::rd_func_sig>::from<this_class, &this_class::read>(this);
this->wr_func = util::delegate<arch_if::wr_func_sig>::from<this_class, &this_class::write>(this);
const std::array<unsigned, 4> rwaddrs{{mepc, mtvec, mscratch, mtval}};
for(auto addr : rwaddrs) {
this->csr_rd_cb[addr] = MK_CSR_RD_CB(read_plain);

6
src/iss/arch/riscv_hart_msu_vp.h
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@ -288,9 +288,9 @@ public:
phys_addr_t virt2phys(const iss::addr_t& addr) override;
iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
uint8_t* const data) override;
uint8_t* const data);
iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
const uint8_t* const data) override;
const uint8_t* const data);
uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, this->fault_data, this->fault_data); }
uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
@ -341,6 +341,8 @@ template <typename BASE>
riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
: state() {
this->mmu = true;
this->rd_func = util::delegate<arch_if::rd_func_sig>::from<this_class, &this_class::read>(this);
this->rd_func = util::delegate<arch_if::wr_func_sig>::from<this_class, &this_class::write>(this);
// common regs
const std::array<unsigned, 17> rwaddrs{{mepc, mtvec, mscratch, mtval, mscratch, sepc, stvec, sscratch, scause, stval, sscratch, uepc,
utvec, uscratch, ucause, utval, uscratch}};

7
src/iss/arch/riscv_hart_mu_p.h
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@ -258,9 +258,9 @@ public:
void reset(uint64_t address) override;
iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
uint8_t* const data) override;
uint8_t* const data);
iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length,
const uint8_t* const data) override;
const uint8_t* const data);
uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, this->fault_data, this->fault_data); }
uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
@ -346,6 +346,9 @@ template <typename BASE, features_e FEAT, typename LOGCAT>
riscv_hart_mu_p<BASE, FEAT, LOGCAT>::riscv_hart_mu_p(feature_config cfg)
: state()
, cfg(cfg) {
this->rd_func = util::delegate<arch_if::rd_func_sig>::from<this_class, &this_class::read>(this);
this->rd_func = util::delegate<arch_if::wr_func_sig>::from<this_class, &this_class::write>(this);
const std::array<unsigned, 8> rwaddrs{{
mepc,
mtvec,

2
src/vm/interp/vm_tgc5c.cpp
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@ -263,7 +263,7 @@ private:
return iss::Err;
// }
} else {
if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok)
return iss::Err;
}