From fb0f6255e9aa858c948910ca0bdfd305c8137039 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 11 Mar 2025 08:31:25 +0100 Subject: [PATCH] replaces virtual functions with memory pointers (kind of) --- src/iss/arch/riscv_hart_common.h | 15 +++++++++++---- src/iss/arch/riscv_hart_m_p.h | 7 +++++-- src/iss/arch/riscv_hart_msu_vp.h | 6 ++++-- src/iss/arch/riscv_hart_mu_p.h | 7 +++++-- src/vm/interp/vm_tgc5c.cpp | 2 +- 5 files changed, 26 insertions(+), 11 deletions(-) diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h index ef325bc..b640b0f 100644 --- a/src/iss/arch/riscv_hart_common.h +++ b/src/iss/arch/riscv_hart_common.h @@ -348,6 +348,9 @@ template struct riscv_hart_co using reg_t = typename core::reg_t; using addr_t = typename core::addr_t; + using rd_csr_f = std::function; + using wr_csr_f = std::function; + #define MK_CSR_RD_CB(FCT) [this](unsigned a, reg_t& r) -> iss::status { return this->FCT(a, r); }; #define MK_CSR_WR_CB(FCT) [this](unsigned a, reg_t r) -> iss::status { return this->FCT(a, r); }; @@ -530,8 +533,14 @@ template struct riscv_hart_co this->reg.cycle + cycle_offset); }; - void register_custom_csr_rd(unsigned addr) { csr_rd_cb[addr] = &this_class::read_custom_csr; } - void register_custom_csr_wr(unsigned addr) { csr_wr_cb[addr] = &this_class::write_custom_csr; } + void register_csr(unsigned addr, rd_csr_f f) { csr_rd_cb[addr] = f; } + void register_csr(unsigned addr, wr_csr_f f) { csr_wr_cb[addr] = f; } + void register_csr(unsigned addr, rd_csr_f rdf, wr_csr_f wrf) { + csr_rd_cb[addr] = rdf; + csr_wr_cb[addr] = wrf; + } + void unregister_csr_rd(unsigned addr) { csr_rd_cb.erase(addr); } + void unregister_csr_wr(unsigned addr) { csr_wr_cb.erase(addr); } bool debug_mode_active() { return this->reg.PRIV & 0x4; } @@ -777,8 +786,6 @@ protected: using csr_page_type = typename csr_type::page_type; csr_type csr; - using rd_csr_f = std::function; - using wr_csr_f = std::function; std::unordered_map csr_rd_cb; std::unordered_map csr_wr_cb; diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 1a985b1..cbdf752 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -232,9 +232,9 @@ public: void reset(uint64_t address) override; iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, - uint8_t* const data) override; + uint8_t* const data); iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, - const uint8_t* const data) override; + const uint8_t* const data); uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, this->fault_data, this->fault_data); } uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override; @@ -316,6 +316,9 @@ template riscv_hart_m_p::riscv_hart_m_p(feature_config cfg) : state() , cfg(cfg) { + this->rd_func = util::delegate::from(this); + this->wr_func = util::delegate::from(this); + const std::array rwaddrs{{mepc, mtvec, mscratch, mtval}}; for(auto addr : rwaddrs) { this->csr_rd_cb[addr] = MK_CSR_RD_CB(read_plain); diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index 1ffeafd..a6b9437 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -288,9 +288,9 @@ public: phys_addr_t virt2phys(const iss::addr_t& addr) override; iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, - uint8_t* const data) override; + uint8_t* const data); iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, - const uint8_t* const data) override; + const uint8_t* const data); uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, this->fault_data, this->fault_data); } uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override; @@ -341,6 +341,8 @@ template riscv_hart_msu_vp::riscv_hart_msu_vp() : state() { this->mmu = true; + this->rd_func = util::delegate::from(this); + this->rd_func = util::delegate::from(this); // common regs const std::array rwaddrs{{mepc, mtvec, mscratch, mtval, mscratch, sepc, stvec, sscratch, scause, stval, sscratch, uepc, utvec, uscratch, ucause, utval, uscratch}}; diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 151bfdc..6d35d7a 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -258,9 +258,9 @@ public: void reset(uint64_t address) override; iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, - uint8_t* const data) override; + uint8_t* const data); iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, - const uint8_t* const data) override; + const uint8_t* const data); uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, this->fault_data, this->fault_data); } uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override; @@ -346,6 +346,9 @@ template riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg) : state() , cfg(cfg) { + this->rd_func = util::delegate::from(this); + this->rd_func = util::delegate::from(this); + const std::array rwaddrs{{ mepc, mtvec, diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index e23b520..8f2b515 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -263,7 +263,7 @@ private: return iss::Err; // } } else { - if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok) + if (this->core.read(iss::address_type::PHYSICAL, pc.access, pc.space, pc.val, 4, data) != iss::Ok) return iss::Err; }