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DBT-RISE-TGC
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fix MISA val

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Eyck Jentzsch 2021-11-11 12:58:57 +01:00
parent 7452c5df43
commit d31b4ef5a8
1 changed files with 1 additions and 1 deletions
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2
gen_input/TGC_D_XRB_NN.core_desc
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@ -127,7 +127,7 @@ Core TGC_D_XRB_NN provides RV32I, Zicsr, Zifencei, RV32M, RV32IC, X_RB_NN {
XLEN=32; XLEN=32;
// definitions for the architecture wrapper // definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA // XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100; unsigned MISA_VAL = 0b01000000100100000011000100000100;
unsigned MARCHID_VAL = 0x80000004; unsigned MARCHID_VAL = 0x80000004;
} }
} }