improved testbench import; added prebuild FW for testing
This commit is contained in:
Rocco Jonack
parent
0304aac9e5
commit
54f75f92ea
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@ -42,6 +42,7 @@ set block SYSTEM_LIBRARY:${top_design_name}
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::pct::set_encap_build_script $block/sysc::tgfs::${top_design_name} $scriptDir/build.tcl
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::pct::set_encap_build_script $block/sysc::tgfs::${top_design_name} $scriptDir/build.tcl
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::pct::set_background_color_rgb $block 255 255 255 255
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::pct::set_background_color_rgb $block 255 255 255 255
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::pct::create_instance SYSTEM_LIBRARY:${top_design_name} ${hardware} ${model_prefix}${top_design_name}${model_postfix} sysc::tgfs::${top_design_name} sysc::tgfs::${top_design_name}()
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::pct::create_instance SYSTEM_LIBRARY:${top_design_name} ${hardware} ${model_prefix}${top_design_name}${model_postfix} sysc::tgfs::${top_design_name} sysc::tgfs::${top_design_name}()
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::pct::set_bounds i_${top_design_name} 200 300 100 400
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# export the result as component
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# export the result as component
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::pct::export_system_library ${top_design_name} ${top_design_name}.xml
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::pct::export_system_library ${top_design_name} ${top_design_name}.xml
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@ -1,29 +0,0 @@
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source tgc_import.tcl
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::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
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::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
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::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \
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{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
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::pct::create_connection C i_core_complex/initiator i_Bus/i_core_complex_initiator
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::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10
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::pct::create_connection C_1 i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
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#::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
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#::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
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::pct::create_simulation_build_config Debug
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::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
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# add build settings and save design for next steps
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#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs ${currentDir}/model/i_${Ncore_top_name}/Vgen_wrapper__ALL.a $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
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#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
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#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
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#::simulation::run_simulation Simulation
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#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
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#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
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#::pct::export_system "export"
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#::cd "export"
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#::scsh::open-project
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#::scsh::build
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#::scsh::elab sim
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::pct::save_system testbench.xml
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@ -0,0 +1,61 @@
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source tgc_import.tcl
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set hardware /HARDWARE/HW/HW
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set FW_name ${scriptDir}/hello.elf
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puts "instantiate testbench elements"
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::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
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::pct::set_bounds i_Memory_Generic 1000 300 100 100
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::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
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::BLWizard::generateFramework i_Bus SBLTLM2FT * {} \
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{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
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::pct::set_bounds i_Bus 700 300 100 400
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::pct::create_connection C_init i_core_complex/initiator i_Bus/i_core_complex_initiator
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::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10
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::pct::create_connection C_targ i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
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puts "instantiating clock manager"
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set clock "Clk"
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::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
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::pct::set_bounds ${clock}_clock 100 100 100 100
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::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
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::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
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puts "instantiating reset manager"
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set reset "Rst"
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::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
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::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 1000
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::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
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::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
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::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
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# ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
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::pct::set_bounds ${reset}_reset 300 100 100 100
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puts "connecting reset/clock"
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::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
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::pct::add_ports_to_connection C_clk i_Bus/Clk
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::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
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::pct::add_ports_to_connection C_rst i_Bus/Rst
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puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
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::pct::set_param_value $hardware/i_core_complex {Scml Properties} elf_file ${FW_name}
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::pct::set_address i_core_complex/initiator:i_Memory_Generic/MEM 0x0
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#::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
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#::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
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#::pct::create_simulation_build_config Debug
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#::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
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# add build settings and save design for next steps
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#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
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#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
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#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
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#::simulation::run_simulation Simulation
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#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
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#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
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#::pct::export_system "export"
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#::cd "export"
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#::scsh::open-project
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#::scsh::build
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#::scsh::elab sim
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::pct::save_system testbench.xml
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