diff --git a/contrib/hello.elf b/contrib/hello.elf
new file mode 100755
index 0000000..9b63df7
Binary files /dev/null and b/contrib/hello.elf differ
diff --git a/contrib/tgc_import.tcl b/contrib/tgc_import.tcl
index 04e0262..549f1b6 100644
--- a/contrib/tgc_import.tcl
+++ b/contrib/tgc_import.tcl
@@ -42,6 +42,7 @@ set block SYSTEM_LIBRARY:${top_design_name}
 ::pct::set_encap_build_script $block/sysc::tgfs::${top_design_name} $scriptDir/build.tcl
 ::pct::set_background_color_rgb $block 255 255 255 255
 ::pct::create_instance SYSTEM_LIBRARY:${top_design_name}  ${hardware} ${model_prefix}${top_design_name}${model_postfix} sysc::tgfs::${top_design_name} sysc::tgfs::${top_design_name}() 
+::pct::set_bounds i_${top_design_name} 200 300 100 400
 
 # export the result as component
 ::pct::export_system_library ${top_design_name}  ${top_design_name}.xml
diff --git a/contrib/tgc_import_tb.pct b/contrib/tgc_import_tb.pct
deleted file mode 100644
index f1b3fb8..0000000
--- a/contrib/tgc_import_tb.pct
+++ /dev/null
@@ -1,29 +0,0 @@
-source tgc_import.tcl
-
-::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
-::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
-::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
-						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
-::pct::create_connection C i_core_complex/initiator i_Bus/i_core_complex_initiator
-::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10
-::pct::create_connection C_1 i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
-
-#::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
-#::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
-::pct::create_simulation_build_config Debug
-::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
-# add build settings and save design for next steps
-#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs ${currentDir}/model/i_${Ncore_top_name}/Vgen_wrapper__ALL.a $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
-#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
-
-#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
-#::simulation::run_simulation Simulation
-
-#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
-#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
-#::pct::export_system "export"
-#::cd "export"
-#::scsh::open-project
-#::scsh::build
-#::scsh::elab sim
-::pct::save_system testbench.xml
diff --git a/contrib/tgc_import_tb.tcl b/contrib/tgc_import_tb.tcl
new file mode 100644
index 0000000..9df24aa
--- /dev/null
+++ b/contrib/tgc_import_tb.tcl
@@ -0,0 +1,61 @@
+source tgc_import.tcl
+set hardware /HARDWARE/HW/HW
+set FW_name ${scriptDir}/hello.elf
+
+puts "instantiate testbench elements"
+::paultra::add_hw_instance GenericIPlib:Memory_Generic -inst_name i_Memory_Generic
+::pct::set_bounds i_Memory_Generic 1000 300 100 100
+::paultra::add_hw_instance Bus:Bus -inst_name i_Bus
+::BLWizard::generateFramework i_Bus SBLTLM2FT  * {} \
+						{ common_configuration:BackBone:/advanced/num_resources_per_target:1 }
+::pct::set_bounds i_Bus 700 300 100 400
+::pct::create_connection C_init i_core_complex/initiator i_Bus/i_core_complex_initiator
+::pct::set_location_on_owner i_Bus/i_core_complex_initiator 10
+::pct::create_connection C_targ i_Bus/i_Memory_Generic_MEM i_Memory_Generic/MEM
+
+puts "instantiating clock manager"
+set clock "Clk"
+::hw::create_hw_instance "" GenericIPlib:ClockGenerator ${clock}_clock
+::pct::set_bounds ${clock}_clock 100 100 100 100
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period 1000
+::pct::set_param_value $hardware/${clock}_clock {Constructor Arguments} period_unit sc_core::SC_PS
+
+puts "instantiating reset manager"
+set reset "Rst"
+ ::hw::create_hw_instance "" GenericIPlib:ResetGenerator ${reset}_reset
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time 1000
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} start_time_unit sc_core::SC_PS
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration 10000
+ ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} duration_unit sc_core::SC_PS
+# ::pct::set_param_value $hardware/${reset}_reset {Constructor Arguments} active_level true
+::pct::set_bounds ${reset}_reset 300 100 100 100
+
+puts "connecting reset/clock"
+::pct::create_connection C_clk . Clk_clock/CLK i_core_complex/clk_i
+::pct::add_ports_to_connection C_clk i_Bus/Clk
+::pct::create_connection C_rst . Rst_reset/RST i_core_complex/rst_i
+::pct::add_ports_to_connection C_rst i_Bus/Rst
+
+puts "setting parameters for DBT-RISE-TGC/Bus and memory components"
+::pct::set_param_value $hardware/i_core_complex {Scml Properties} elf_file ${FW_name}
+::pct::set_address i_core_complex/initiator:i_Memory_Generic/MEM 0x0
+
+#::pct::set_main_configuration Default {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::INFO).coloredOutput(false).logAsync(false));} {} {} {}}
+#::pct::set_main_configuration Debug {{#include <scc/report.h>} {::scc::init_logging(::scc::LogConfig().logLevel(::scc::log::DEBUG).coloredOutput(false).logAsync(false));} {} {} {}}
+#::pct::create_simulation_build_config Debug
+#::pct::set_simulation_build_project_setting Debug "Main Configuration" Default
+# add build settings and save design for next steps
+#::pct::set_simulation_build_project_setting "Debug" "Linker Flags" "-Wl,-z,muldefs $::env(VERILATOR_ROOT)/include/verilated.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_sc.cpp $::env(VERILATOR_ROOT)/include/verilated_vcd_c.cpp"
+#::pct::set_simulation_build_project_setting "Debug" "Include Paths" $::env(VERILATOR_ROOT)/include/
+
+#::simulation::set_simulation_property Simulation [list run_for_duration:200ns results_dir:results/test_0 "TLM Port Trace:true"]
+#::simulation::run_simulation Simulation
+
+#::pct::set_simulation_build_project_setting Debug {Export Type} {STATIC NETLIST}
+#::pct::set_simulation_build_project_setting Debug {Encapsulated Netlist} false
+#::pct::export_system "export"
+#::cd "export"
+#::scsh::open-project
+#::scsh::build
+#::scsh::elab sim
+::pct::save_system testbench.xml