DBT-RISE/DBT-RISE-TGC
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Added use of CCI and support of LLVM 5.0

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changed load_file to adhere to API change in DBT-RISE
This commit is contained in:
Eyck Jentzsch
2018-03-27 19:49:11 +02:00
parent 36be8b87f1
commit 3ea9651665
16 changed files with 61 additions and 36 deletions
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4
riscv.sc/src/sysc/uart.cpp
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@ -57,7 +57,7 @@ uart::uart(sc_core::sc_module_name nm)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(uart_regs, regs)
, NAMED(write_to_ws, false, this) {
, NAMED(write_to_ws, false) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive << clk_i;
@ -76,7 +76,7 @@ uart::uart(sc_core::sc_module_name nm)
uart::~uart() {}
void uart::before_end_of_elaboration() {
if(write_to_ws.value) {
if(write_to_ws.get_value()) {
LOG(TRACE)<<"Adding WS handler for "<<(std::string{"/ws/"}+name());
handler=std::make_shared<WsHandler>();
sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"}+name()).c_str(), handler);