Added simple example plugin creating instruction histogram
This commit is contained in:
parent
c5a7adcef5
commit
36be8b87f1
2
dbt-core
2
dbt-core
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@ -1 +1 @@
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Subproject commit e70839fbf599302c976919afc590492b80bb2995
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Subproject commit 5a31988a9d389db6e3862fc611125e11fe75362c
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@ -1,8 +1,9 @@
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{
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'${coreDef.name}' : [<%instructions.each{instr -> %>
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"${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","}
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{
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'name' : '${instr.name}',
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'delay' : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1
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},<%}%>
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"name" : "${instr.name}",
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"size" : ${instr.length},
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"delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1}
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}<%}%>
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]
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}
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@ -52,6 +52,8 @@ struct ${coreDef.name.toLowerCase()};
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template<>
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struct traits<${coreDef.name.toLowerCase()}> {
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constexpr static char const* const core_type = "${coreDef.name}";
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enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
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enum reg_e {<%
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@ -110,6 +112,8 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
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${coreDef.name.toLowerCase()}();
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~${coreDef.name.toLowerCase()}();
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const std::string core_type_name() const override {return traits<${coreDef.name.toLowerCase()}>::core_type;}
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void reset(uint64_t address=0) override;
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uint8_t* get_regs_base_ptr() override;
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@ -46,6 +46,8 @@ struct rv32imac;
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template<>
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struct traits<rv32imac> {
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constexpr static char const* const core_type = "RV32IMAC";
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enum constants {XLEN=32, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095};
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enum reg_e {
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@ -128,6 +130,8 @@ struct rv32imac: public arch_if {
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rv32imac();
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~rv32imac();
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const std::string core_type_name() const override {return traits<rv32imac>::core_type;}
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void reset(uint64_t address=0) override;
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uint8_t* get_regs_base_ptr() override;
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@ -46,6 +46,8 @@ struct rv64ia;
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template<>
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struct traits<rv64ia> {
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constexpr static char const* const core_type = "RV64IA";
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enum constants {XLEN=64, XLEN2=128, XLEN_BIT_MASK=63, PCLEN=64, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
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enum reg_e {
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@ -128,6 +130,8 @@ struct rv64ia: public arch_if {
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rv64ia();
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~rv64ia();
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const std::string core_type_name() const override {return traits<rv64ia>::core_type;}
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void reset(uint64_t address=0) override;
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uint8_t* get_regs_base_ptr() override;
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@ -0,0 +1,73 @@
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/*******************************************************************************
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* Copyright (C) 2017, MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Contributors:
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* eyck@minres.com - initial API and implementation
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******************************************************************************/
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#ifndef _ISS_PLUGIN_CYCLE_COUNTER_H_
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#define _ISS_PLUGIN_CYCLE_COUNTER_H_
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#include <iss/vm_plugin.h>
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#include <json/json.h>
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#include <string>
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namespace iss {
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namespace plugin {
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class instruction_count: public iss::vm_plugin {
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struct instr_delay {
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std::string instr_name;
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size_t size;
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size_t not_taken_delay;
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size_t taken_delay;
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};
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public:
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instruction_count() = delete;
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instruction_count(std::string config_file_name);
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virtual ~instruction_count();
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bool registration(const char* const version, vm_if& arch) override;
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sync_type get_sync() override {return POST_SYNC;};
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void callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) override;
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private:
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Json::Value root;
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std::vector<instr_delay> delays;
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std::vector<uint64_t> rep_counts;
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};
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}
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}
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#endif /* _ISS_PLUGIN_CYCLE_COUNTER_H_ */
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@ -6,6 +6,7 @@ set(LIB_SOURCES
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iss/rv64ia.cpp
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internal/vm_rv32imac.cpp
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internal/vm_rv64ia.cpp
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plugin/instruction_count.cpp
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)
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set(APP_HEADERS )
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@ -42,6 +42,7 @@
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#include <iss/arch/rv64ia.h>
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#include <iss/jit/MCJIThelper.h>
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#include <iss/log_categories.h>
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#include <iss/plugin/instruction_count.h>
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namespace po = boost::program_options;
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@ -101,12 +102,14 @@ int main(int argc, char *argv[]) {
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// instantiate the simulator
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std::unique_ptr<iss::vm_if> vm{nullptr};
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std::string isa_opt(clim["isa"].as<std::string>());
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iss::plugin::instruction_count cc_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
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if (isa_opt.substr(0, 4)=="rv64") {
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iss::arch::rv64ia* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64ia>();
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vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
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} else if (isa_opt.substr(0, 4)=="rv32") {
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iss::arch::rv32imac* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
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vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
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vm->register_plugin(cc_plugin);
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} else {
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LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
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return 127;
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@ -0,0 +1,90 @@
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/*******************************************************************************
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* Copyright (C) 2017, MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Contributors:
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* eyck@minres.com - initial API and implementation
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******************************************************************************/
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#include "../../incl/iss/plugin/instruction_count.h"
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#include <iss/arch_if.h>
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#include <util/logging.h>
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#include <fstream>
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iss::plugin::instruction_count::instruction_count(std::string config_file_name) {
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if (config_file_name.length() > 0) {
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std::ifstream is(config_file_name);
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if (is.is_open()) {
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try {
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is >> root;
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} catch (Json::RuntimeError &e) {
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LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
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}
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} else {
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LOG(ERROR) << "Could not open input file " << config_file_name;
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}
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}
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}
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iss::plugin::instruction_count::~instruction_count() {
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size_t idx=0;
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for(auto it:delays){
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if(rep_counts[idx]>0)
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LOG(INFO)<<it.instr_name<<";"<<rep_counts[idx];
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idx++;
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}
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}
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bool iss::plugin::instruction_count::registration(const char* const version, vm_if& vm) {
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const std::string core_name = vm.get_arch()->core_type_name();
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Json::Value &val = root[core_name];
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if(val.isArray()){
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delays.reserve(val.size());
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for(auto it:val){
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auto name = it["name"];
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auto size = it["size"];
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auto delay = it["delay"];
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if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error");
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if(delay.isUInt()){
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const instr_delay entry{name.asCString(), size.asUInt(), delay.asUInt(), 0};
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delays.push_back(entry);
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} else {
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const instr_delay entry{name.asCString(), size.asUInt(), delay[0].asUInt(), delay[1].asUInt()};
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delays.push_back(entry);
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}
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}
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rep_counts.resize(delays.size());
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}
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return true;
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}
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void iss::plugin::instruction_count::callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) {
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rep_counts[instr_id]++;
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}
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@ -1 +1 @@
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Subproject commit 92802d543014324ad599723ae32d0a84c5162ca8
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Subproject commit 19406add3e723f032058c01ecae7c2c84bbe67e9
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