From 36be8b87f14bc992e80749a256566caa1f0fec15 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sun, 11 Feb 2018 21:23:26 +0000 Subject: [PATCH] Added simple example plugin creating instruction histogram --- dbt-core | 2 +- .../templates/CORENAME_cyles.txt.gtl | 9 +- riscv/gen_input/templates/incl-CORENAME.h.gtl | 4 + riscv/incl/iss/arch/rv32imac.h | 4 + riscv/incl/iss/arch/rv64ia.h | 4 + riscv/incl/iss/plugin/instruction_count.h | 73 +++++++++++++++ riscv/src/CMakeLists.txt | 1 + riscv/src/main.cpp | 3 + riscv/src/plugin/instruction_count.cpp | 90 +++++++++++++++++++ sc-components | 2 +- 10 files changed, 186 insertions(+), 6 deletions(-) create mode 100644 riscv/incl/iss/plugin/instruction_count.h create mode 100644 riscv/src/plugin/instruction_count.cpp diff --git a/dbt-core b/dbt-core index e70839f..5a31988 160000 --- a/dbt-core +++ b/dbt-core @@ -1 +1 @@ -Subproject commit e70839fbf599302c976919afc590492b80bb2995 +Subproject commit 5a31988a9d389db6e3862fc611125e11fe75362c diff --git a/riscv/gen_input/templates/CORENAME_cyles.txt.gtl b/riscv/gen_input/templates/CORENAME_cyles.txt.gtl index 4f5eac7..3a1ad8e 100644 --- a/riscv/gen_input/templates/CORENAME_cyles.txt.gtl +++ b/riscv/gen_input/templates/CORENAME_cyles.txt.gtl @@ -1,8 +1,9 @@ { - '${coreDef.name}' : [<%instructions.each{instr -> %> + "${coreDef.name}" : [<%instructions.eachWithIndex{instr,index -> %>${index==0?"":","} { - 'name' : '${instr.name}', - 'delay' : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1 - },<%}%> + "name" : "${instr.name}", + "size" : ${instr.length}, + "delay" : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1} + }<%}%> ] } \ No newline at end of file diff --git a/riscv/gen_input/templates/incl-CORENAME.h.gtl b/riscv/gen_input/templates/incl-CORENAME.h.gtl index 9af6850..2b5686a 100644 --- a/riscv/gen_input/templates/incl-CORENAME.h.gtl +++ b/riscv/gen_input/templates/incl-CORENAME.h.gtl @@ -52,6 +52,8 @@ struct ${coreDef.name.toLowerCase()}; template<> struct traits<${coreDef.name.toLowerCase()}> { + constexpr static char const* const core_type = "${coreDef.name}"; + enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}}; enum reg_e {<% @@ -110,6 +112,8 @@ struct ${coreDef.name.toLowerCase()}: public arch_if { ${coreDef.name.toLowerCase()}(); ~${coreDef.name.toLowerCase()}(); + const std::string core_type_name() const override {return traits<${coreDef.name.toLowerCase()}>::core_type;} + void reset(uint64_t address=0) override; uint8_t* get_regs_base_ptr() override; diff --git a/riscv/incl/iss/arch/rv32imac.h b/riscv/incl/iss/arch/rv32imac.h index 0814d96..0364679 100644 --- a/riscv/incl/iss/arch/rv32imac.h +++ b/riscv/incl/iss/arch/rv32imac.h @@ -46,6 +46,8 @@ struct rv32imac; template<> struct traits { + constexpr static char const* const core_type = "RV32IMAC"; + enum constants {XLEN=32, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095}; enum reg_e { @@ -128,6 +130,8 @@ struct rv32imac: public arch_if { rv32imac(); ~rv32imac(); + const std::string core_type_name() const override {return traits::core_type;} + void reset(uint64_t address=0) override; uint8_t* get_regs_base_ptr() override; diff --git a/riscv/incl/iss/arch/rv64ia.h b/riscv/incl/iss/arch/rv64ia.h index 3566e49..ea000f4 100644 --- a/riscv/incl/iss/arch/rv64ia.h +++ b/riscv/incl/iss/arch/rv64ia.h @@ -46,6 +46,8 @@ struct rv64ia; template<> struct traits { + constexpr static char const* const core_type = "RV64IA"; + enum constants {XLEN=64, XLEN2=128, XLEN_BIT_MASK=63, PCLEN=64, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095}; enum reg_e { @@ -128,6 +130,8 @@ struct rv64ia: public arch_if { rv64ia(); ~rv64ia(); + const std::string core_type_name() const override {return traits::core_type;} + void reset(uint64_t address=0) override; uint8_t* get_regs_base_ptr() override; diff --git a/riscv/incl/iss/plugin/instruction_count.h b/riscv/incl/iss/plugin/instruction_count.h new file mode 100644 index 0000000..9c78829 --- /dev/null +++ b/riscv/incl/iss/plugin/instruction_count.h @@ -0,0 +1,73 @@ +/******************************************************************************* + * Copyright (C) 2017, MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Contributors: + * eyck@minres.com - initial API and implementation + ******************************************************************************/ + +#ifndef _ISS_PLUGIN_CYCLE_COUNTER_H_ +#define _ISS_PLUGIN_CYCLE_COUNTER_H_ + +#include +#include +#include + +namespace iss { +namespace plugin { + +class instruction_count: public iss::vm_plugin { + struct instr_delay { + std::string instr_name; + size_t size; + size_t not_taken_delay; + size_t taken_delay; + }; +public: + instruction_count() = delete; + + instruction_count(std::string config_file_name); + + virtual ~instruction_count(); + + bool registration(const char* const version, vm_if& arch) override; + + sync_type get_sync() override {return POST_SYNC;}; + + void callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) override; +private: + Json::Value root; + std::vector delays; + std::vector rep_counts; +}; + +} +} + +#endif /* _ISS_PLUGIN_CYCLE_COUNTER_H_ */ diff --git a/riscv/src/CMakeLists.txt b/riscv/src/CMakeLists.txt index ccdc31f..9c3f1bb 100644 --- a/riscv/src/CMakeLists.txt +++ b/riscv/src/CMakeLists.txt @@ -6,6 +6,7 @@ set(LIB_SOURCES iss/rv64ia.cpp internal/vm_rv32imac.cpp internal/vm_rv64ia.cpp + plugin/instruction_count.cpp ) set(APP_HEADERS ) diff --git a/riscv/src/main.cpp b/riscv/src/main.cpp index 8eb001a..1cc659e 100644 --- a/riscv/src/main.cpp +++ b/riscv/src/main.cpp @@ -42,6 +42,7 @@ #include #include #include +#include namespace po = boost::program_options; @@ -101,12 +102,14 @@ int main(int argc, char *argv[]) { // instantiate the simulator std::unique_ptr vm{nullptr}; std::string isa_opt(clim["isa"].as()); + iss::plugin::instruction_count cc_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt"); if (isa_opt.substr(0, 4)=="rv64") { iss::arch::rv64ia* cpu = new iss::arch::riscv_hart_msu_vp(); vm = iss::create(cpu, clim["gdb-port"].as()); } else if (isa_opt.substr(0, 4)=="rv32") { iss::arch::rv32imac* cpu = new iss::arch::riscv_hart_msu_vp(); vm = iss::create(cpu, clim["gdb-port"].as()); + vm->register_plugin(cc_plugin); } else { LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as() << std::endl; return 127; diff --git a/riscv/src/plugin/instruction_count.cpp b/riscv/src/plugin/instruction_count.cpp new file mode 100644 index 0000000..4a3ad54 --- /dev/null +++ b/riscv/src/plugin/instruction_count.cpp @@ -0,0 +1,90 @@ +/******************************************************************************* + * Copyright (C) 2017, MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Contributors: + * eyck@minres.com - initial API and implementation + ******************************************************************************/ + +#include "../../incl/iss/plugin/instruction_count.h" + +#include +#include +#include + +iss::plugin::instruction_count::instruction_count(std::string config_file_name) { + if (config_file_name.length() > 0) { + std::ifstream is(config_file_name); + if (is.is_open()) { + try { + is >> root; + } catch (Json::RuntimeError &e) { + LOG(ERROR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); + } + } else { + LOG(ERROR) << "Could not open input file " << config_file_name; + } + } +} + +iss::plugin::instruction_count::~instruction_count() { + size_t idx=0; + for(auto it:delays){ + if(rep_counts[idx]>0) + LOG(INFO)<core_type_name(); + Json::Value &val = root[core_name]; + if(val.isArray()){ + delays.reserve(val.size()); + for(auto it:val){ + auto name = it["name"]; + auto size = it["size"]; + auto delay = it["delay"]; + if(!name.isString() || !size.isUInt() || !(delay.isUInt() || delay.isArray())) throw std::runtime_error("JSON parse error"); + if(delay.isUInt()){ + const instr_delay entry{name.asCString(), size.asUInt(), delay.asUInt(), 0}; + delays.push_back(entry); + } else { + const instr_delay entry{name.asCString(), size.asUInt(), delay[0].asUInt(), delay[1].asUInt()}; + delays.push_back(entry); + } + } + rep_counts.resize(delays.size()); + } + return true; +} + +void iss::plugin::instruction_count::callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) { + rep_counts[instr_id]++; +} diff --git a/sc-components b/sc-components index 92802d5..19406ad 160000 --- a/sc-components +++ b/sc-components @@ -1 +1 @@ -Subproject commit 92802d543014324ad599723ae32d0a84c5162ca8 +Subproject commit 19406add3e723f032058c01ecae7c2c84bbe67e9