DBT-RISE-TGC/incl/sysc/core_complex.h

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/*******************************************************************************
* Copyright (C) 2017-2021 MINRES Technologies GmbH
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* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#ifndef _SYSC_CORE_COMPLEX_H_
#define _SYSC_CORE_COMPLEX_H_
#include <tlm/scc/initiator_mixin.h>
#include <scc/traceable.h>
#include <scc/tick2time.h>
#include <scc/utilities.h>
#include <tlm/scc/scv/tlm_rec_initiator_socket.h>
#ifdef CWR_SYSTEMC
#include <scmlinc/scml_property.h>
#else
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#include <cci_configuration>
#endif
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#include <tlm>
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#include <tlm_utils/tlm_quantumkeeper.h>
#include <util/range_lut.h>
#include <memory>
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namespace sysc {
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class tlm_dmi_ext : public tlm::tlm_dmi {
public:
bool operator==(const tlm_dmi_ext &o) const {
return this->get_granted_access() == o.get_granted_access() &&
this->get_start_address() == o.get_start_address() && this->get_end_address() == o.get_end_address();
}
bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
};
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namespace tgfs {
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class core_wrapper;
struct core_trace;
class core_complex : public sc_core::sc_module, public scc::traceable {
public:
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tlm::scc::initiator_mixin<tlm::scc::scv::tlm_rec_initiator_socket<32>> initiator{"intor"};
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sc_core::sc_in<bool> rst_i{"rst_i"};
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sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
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sc_core::sc_in<bool> timer_irq_i{"timer_irq_i"};
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sc_core::sc_in<bool> sw_irq_i{"sw_irq_i"};
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sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i{"local_irq_i", 16};
#ifndef CWR_SYSTEMC
sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
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sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
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cci::cci_param<std::string> elf_file{"elf_file", ""};
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cci::cci_param<bool> enable_disass{"enable_disass", false};
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cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
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cci::cci_param<std::string> core_type{"core_type", "tgc_c"};
cci::cci_param<std::string> backend{"backend", "interp"};
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cci::cci_param<unsigned short> gdb_server_port{"gdb_server_port", 0};
cci::cci_param<bool> dump_ir{"dump_ir", false};
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cci::cci_param<uint32_t> mhartid{"mhartid", 0};
core_complex(sc_core::sc_module_name const& name);
#else
sc_core::sc_in<bool> clk_i{"clk_i"};
sc_core::sc_in<uint64_t> mtime_i{"mtime_i"};
scml_property<std::string> elf_file{"elf_file", ""};
scml_property<bool> enable_disass{"enable_disass", false};
scml_property<unsigned long long> reset_address{"reset_address", 0ULL};
scml_property<std::string> core_type{"core_type", "tgc_c"};
scml_property<std::string> backend{"backend", "interp"};
scml_property<unsigned> gdb_server_port{"gdb_server_port", 0};
scml_property<bool> dump_ir{"dump_ir", false};
scml_property<uint32_t> mhartid{"mhartid", 0};
core_complex(sc_core::sc_module_name const& name)
: sc_module(name)
, local_irq_i{"local_irq_i", 16}
, elf_file{"elf_file", ""}
, enable_disass{"enable_disass", false}
, reset_address{"reset_address", 0ULL}
, core_type{"core_type", "tgc_c"}
, backend{"backend", "interp"}
, gdb_server_port{"gdb_server_port", 0}
, dump_ir{"dump_ir", false}
, mhartid{"mhartid", 0}
, read_lut(tlm_dmi_ext())
, write_lut(tlm_dmi_ext())
{
init();
}
#endif
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~core_complex();
inline void sync(uint64_t cycle) {
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auto time = curr_clk * (cycle - last_sync_cycle);
quantum_keeper.inc(time);
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if (quantum_keeper.need_sync()) {
wait(quantum_keeper.get_local_time());
quantum_keeper.reset();
}
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last_sync_cycle = cycle;
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}
bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
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bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data);
bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data);
bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data);
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void trace(sc_core::sc_trace_file *trf) const override;
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bool disass_output(uint64_t pc, const std::string instr);
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void set_clock_period(sc_core::sc_time period);
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protected:
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void before_end_of_elaboration() override;
void start_of_simulation() override;
void forward();
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void run();
void rst_cb();
void sw_irq_cb();
void timer_irq_cb();
void global_irq_cb();
uint64_t last_sync_cycle = 0;
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util::range_lut<tlm_dmi_ext> read_lut, write_lut;
tlm_utils::tlm_quantumkeeper quantum_keeper;
std::vector<uint8_t> write_buf;
core_wrapper* cpu{nullptr};
sc_core::sc_signal<sc_core::sc_time> curr_clk;
core_trace* trc{nullptr};
std::unique_ptr<scc::tick2time> t2t;
private:
void init();
};
} /* namespace SiFive */
} /* namespace sysc */
#endif /* _SYSC_CORE_COMPLEX_H_ */