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103 Commits 3 Branches 0 Tags 2.7 MiB
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103 Commits

Author SHA1 Message Date
Eyck Jentzsch 70ee11ad3d fixes coremark linker setting 2024-03-21 07:32:20 +01:00
Eyck Jentzsch a04e6d3c5b fixes TGCP settings in coremark port 2024-03-20 12:53:35 +01:00
Eyck Jentzsch 06add2e20d reduces dhrystone iterations to 20000 for reasonable RTL sim times 2024-03-20 12:24:57 +01:00
Eyck Jentzsch 2fb5920348 updates coremark portable part to match BSP 2024-03-20 11:55:48 +01:00
Eyck Jentzsch 6d33d0b066 fixes wrone use of bsp in coremark 2024-03-20 07:46:42 +01:00
Eyck Jentzsch d5c672c288 updates coremark build system to use BSP definitions 2024-03-20 07:40:21 +01:00
Eyck Jentzsch fabf7cc588 fixes env name for TGCP 2024-03-19 14:25:58 +01:00
Eyck Jentzsch 34764d3149 updates BSP 2024-03-14 08:13:10 +01:00
Eyck Jentzsch 6498091bfb removes unused file 2024-03-14 07:58:48 +01:00
Eyck Jentzsch aeef0f314a updates bare-metal-bsp 2024-03-02 16:11:24 +01:00
Eyck-Alexander Jentzsch 542e448f17 adds new bsp, updates stubs for mrns vp 2024-02-22 17:11:58 +01:00
gabriel 6a6c2007d9 add Jenkinsfile 2024-01-30 10:08:15 +01:00
Eyck Jentzsch 3381b01ec1 replaces bare-metal-bsp with submodule 2024-01-13 15:37:10 +01:00
Eyck Jentzsch 51c8a93336 fixes march definitions for dhrystone and coremark 2023-12-09 16:38:45 +01:00
Eyck Jentzsch 6ff0161882 adds some consistency fixes for variable ISA settings 2023-12-02 17:41:14 +01:00
Eyck Jentzsch 8c1c2766e8 Merge branch 'develop' into main 2023-12-02 16:27:30 +01:00
Eyck Jentzsch 1b8f78fe78 makes build more configurable by CLI 2023-11-27 10:13:22 +01:00
Stanislaw Kaushanski d20582d7aa fix prci build 2023-11-24 13:06:31 +01:00
Eyck Jentzsch 0188d404de fixes hifive1 build 2023-11-24 11:39:23 +01:00
Stanislaw Kaushanski 77ca8a01b4 add hifive1 2023-11-24 09:36:53 +01:00
Eyck Jentzsch db53376533 Merge branch 'develop' into main 2023-11-23 18:30:43 +01:00
Eyck Jentzsch 41f204e304 adds wrapping to all clib symbols 2023-11-23 18:29:26 +01:00
Eyck Jentzsch acf20a4818 adds missing files 2023-11-23 18:14:41 +01:00
Eyck Jentzsch aab4d1f2a0 adds missing symbols and sources for libwrap 2023-11-23 18:14:41 +01:00
Eyck Jentzsch e91ce0148b adds build targets 2023-10-30 07:51:59 +01:00
Eyck Jentzsch 7093e47c08 adds a CMakeLists.txt message to indicate board selection 2023-10-27 22:16:21 +02:00
Eyck Jentzsch 63f57b9ba1 extends eclipse build configs 2023-10-26 06:11:12 +02:00
Eyck Jentzsch af3a154882 adds tgc-vp environment 2023-10-25 20:35:44 +02:00
Eyck Jentzsch b082091db2 adds missing files 2023-09-30 20:31:58 +02:00
Eyck Jentzsch eeb17437ee adds missing symbols and sources for libwrap 2023-09-28 11:51:20 +02:00
Eyck Jentzsch 9c0047b3ea updates linker script for rtl env 2023-08-30 15:07:56 +02:00
Eyck Jentzsch ca1adccb2b fixes TGC5L settings 2023-08-28 10:01:06 +02:00
Eyck Jentzsch 3217871752 extends build system to propagate more settings 2023-08-20 16:45:54 +02:00
Eyck Jentzsch 9dd7dcb4ce adds TGC5L environment 2023-08-20 16:39:20 +02:00
Eyck Jentzsch 3403edcde9 adds CMakeLists.txt 2023-08-20 15:50:00 +02:00
Eyck Jentzsch 3a3cbf38c3 re-adds coremark as submodule 2023-08-20 15:23:05 +02:00
Eyck Jentzsch 822696ae0d cleanup 2023-08-20 15:20:39 +02:00
Eyck Jentzsch 314ceeb072 rework structure 2023-08-20 15:00:51 +02:00
Eyck Jentzsch 4c2208c1ac fix wrong exit call 2022-11-06 17:33:39 +01:00
Stanislaw Kaushanski 36a6de6dc0 remove raven dirs 2022-05-02 13:21:12 +02:00
Stanislaw Kaushanski d2cb78724a move RAVEN FW into Validation-VP repo 2022-05-02 13:19:36 +02:00
Stanislaw Kaushanski 0de438dc52 avoid interrupts while printing 2022-05-02 09:51:05 +02:00
Stanislaw Kaushanski 5f44f8df98 Improve wait for interrupt routines 2022-04-28 19:20:32 +02:00
Stanislaw Kaushanski 02ce96eed8 improve interrupt handling 2022-04-26 15:29:49 +02:00
Johannes Wirth 46f197c287 Add additional registers for input to FW 
(number of XSPNs, batch size, iterations)
 2022-03-11 14:21:25 +01:00
Johannes Wirth 43e2a299db fpga_spn: add check if input-/ref-data fits into memory 2022-03-10 14:17:52 +01:00
Johannes Wirth 8450f85c93 raven_spn: add check if input-/ref-data fits into memory 2022-03-10 13:11:10 +01:00
Johannes Wirth a14ff554b0 Move XSPN input and ref data to Validation-VP 2022-03-10 13:09:11 +01:00
Stanislaw Kaushanski 588ca3c7ba Merge pull request 'Add allocate+free functionality for fpga' (#1) from feature/fpga-alloc-free into master 
Reviewed-on: VP/Firmwares#1
 2022-02-11 16:12:21 +01:00
Johannes Wirth 91f28e9f2b Add allocate+free functionality for fpga 2022-01-20 18:22:21 +01:00