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70ee11ad3d
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fixes coremark linker setting
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2024-03-21 07:32:20 +01:00 |
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a04e6d3c5b
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fixes TGCP settings in coremark port
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2024-03-20 12:53:35 +01:00 |
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06add2e20d
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reduces dhrystone iterations to 20000 for reasonable RTL sim times
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2024-03-20 12:24:57 +01:00 |
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2fb5920348
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updates coremark portable part to match BSP
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2024-03-20 11:55:48 +01:00 |
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6d33d0b066
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fixes wrone use of bsp in coremark
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2024-03-20 07:46:42 +01:00 |
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d5c672c288
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updates coremark build system to use BSP definitions
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2024-03-20 07:40:21 +01:00 |
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fabf7cc588
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fixes env name for TGCP
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2024-03-19 14:25:58 +01:00 |
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34764d3149
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updates BSP
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2024-03-14 08:13:10 +01:00 |
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6498091bfb
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removes unused file
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2024-03-14 07:58:48 +01:00 |
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aeef0f314a
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updates bare-metal-bsp
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2024-03-02 16:11:24 +01:00 |
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542e448f17
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adds new bsp, updates stubs for mrns vp
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2024-02-22 17:11:58 +01:00 |
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gabriel
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6a6c2007d9
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add Jenkinsfile
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2024-01-30 10:08:15 +01:00 |
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3381b01ec1
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replaces bare-metal-bsp with submodule
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2024-01-13 15:37:10 +01:00 |
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51c8a93336
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fixes march definitions for dhrystone and coremark
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2023-12-09 16:38:45 +01:00 |
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6ff0161882
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adds some consistency fixes for variable ISA settings
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2023-12-02 17:41:14 +01:00 |
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8c1c2766e8
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Merge branch 'develop' into main
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2023-12-02 16:27:30 +01:00 |
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1b8f78fe78
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makes build more configurable by CLI
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2023-11-27 10:13:22 +01:00 |
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d20582d7aa
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fix prci build
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2023-11-24 13:06:31 +01:00 |
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0188d404de
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fixes hifive1 build
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2023-11-24 11:39:23 +01:00 |
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77ca8a01b4
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add hifive1
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2023-11-24 09:36:53 +01:00 |
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db53376533
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Merge branch 'develop' into main
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2023-11-23 18:30:43 +01:00 |
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41f204e304
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adds wrapping to all clib symbols
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2023-11-23 18:29:26 +01:00 |
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acf20a4818
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adds missing files
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2023-11-23 18:14:41 +01:00 |
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aab4d1f2a0
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adds missing symbols and sources for libwrap
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2023-11-23 18:14:41 +01:00 |
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e91ce0148b
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adds build targets
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2023-10-30 07:51:59 +01:00 |
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7093e47c08
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adds a CMakeLists.txt message to indicate board selection
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2023-10-27 22:16:21 +02:00 |
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63f57b9ba1
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extends eclipse build configs
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2023-10-26 06:11:12 +02:00 |
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af3a154882
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adds tgc-vp environment
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2023-10-25 20:35:44 +02:00 |
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b082091db2
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adds missing files
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2023-09-30 20:31:58 +02:00 |
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eeb17437ee
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adds missing symbols and sources for libwrap
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2023-09-28 11:51:20 +02:00 |
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9c0047b3ea
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updates linker script for rtl env
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2023-08-30 15:07:56 +02:00 |
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ca1adccb2b
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fixes TGC5L settings
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2023-08-28 10:01:06 +02:00 |
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3217871752
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extends build system to propagate more settings
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2023-08-20 16:45:54 +02:00 |
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9dd7dcb4ce
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adds TGC5L environment
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2023-08-20 16:39:20 +02:00 |
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3403edcde9
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adds CMakeLists.txt
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2023-08-20 15:50:00 +02:00 |
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3a3cbf38c3
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re-adds coremark as submodule
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2023-08-20 15:23:05 +02:00 |
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822696ae0d
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cleanup
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2023-08-20 15:20:39 +02:00 |
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314ceeb072
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rework structure
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2023-08-20 15:00:51 +02:00 |
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4c2208c1ac
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fix wrong exit call
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2022-11-06 17:33:39 +01:00 |
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36a6de6dc0
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remove raven dirs
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2022-05-02 13:21:12 +02:00 |
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d2cb78724a
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move RAVEN FW into Validation-VP repo
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2022-05-02 13:19:36 +02:00 |
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0de438dc52
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avoid interrupts while printing
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2022-05-02 09:51:05 +02:00 |
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5f44f8df98
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Improve wait for interrupt routines
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2022-04-28 19:20:32 +02:00 |
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02ce96eed8
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improve interrupt handling
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2022-04-26 15:29:49 +02:00 |
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46f197c287
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Add additional registers for input to FW
(number of XSPNs, batch size, iterations)
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2022-03-11 14:21:25 +01:00 |
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43e2a299db
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fpga_spn: add check if input-/ref-data fits into memory
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2022-03-10 14:17:52 +01:00 |
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8450f85c93
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raven_spn: add check if input-/ref-data fits into memory
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2022-03-10 13:11:10 +01:00 |
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a14ff554b0
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Move XSPN input and ref data to Validation-VP
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2022-03-10 13:09:11 +01:00 |
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588ca3c7ba
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Merge pull request 'Add allocate+free functionality for fpga' (#1) from feature/fpga-alloc-free into master
Reviewed-on: VP/Firmwares#1
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2022-02-11 16:12:21 +01:00 |
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91f28e9f2b
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Add allocate+free functionality for fpga
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2022-01-20 18:22:21 +01:00 |
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