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Back-ported DVCon turorial changes

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This commit is contained in:
Eyck Jentzsch
2018-11-08 13:31:28 +01:00
parent 124a308ffa
commit 20b3665003
86 changed files with 429488 additions and 4424 deletions
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130
platform/src/sysc/BLDC.cpp
View File

@ -1,9 +1,34 @@
/*
* BLDC.cpp
/*******************************************************************************
* Copyright (C) 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Created on: 26.06.2018
* Author: eyck
*/
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/top/BLDC.h"
@ -14,50 +39,48 @@ BLDC::BLDC(const Config config)
, stateVector({{0.0, 0.0, 0.0, 0.0, 0.0}})
, state(stateVector)
, vin({{0.0, 0.0, 0.0}})
, voltages({{0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0}})
{
, voltages({{0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0}}) {
state.init();
}
BLDC::~BLDC() {
BLDC::~BLDC() = default;
}
double BLDC::calc_bemf_factor(const State& x, double theta){
if(theta>=0 && theta < 2./3.*M_PI){
double BLDC::calc_bemf_factor(const State &x, double theta) {
if (theta >= 0 && theta < 2. / 3. * M_PI) {
return 1;
} else if(theta>=2./3.*M_PI && theta < M_PI){
return 1-6/M_PI*(theta-2./3.*M_PI);
} else if(theta>=M_PI && theta < 5./3. * M_PI){
} else if (theta >= 2. / 3. * M_PI && theta < M_PI) {
return 1 - 6 / M_PI * (theta - 2. / 3. * M_PI);
} else if (theta >= M_PI && theta < 5. / 3. * M_PI) {
return -1;
} else if(theta>=5./3. * M_PI && theta < 2. * M_PI){
return -1+6/M_PI*(theta-5./3.*M_PI);
} else if (theta >= 5. / 3. * M_PI && theta <= 2. * M_PI) {
return -1 + 6 / M_PI * (theta - 5. / 3. * M_PI);
} else {
fprintf(stderr, "ERROR: angle out of bounds can not calculate bemf %f\n", theta);
throw std::runtime_error("angle out of bounds can not calculate bemf");
}
}
void BLDC::calc_back_emf(const State& state, double theta_e) {
void BLDC::calc_back_emf(const State &state, double theta_e) {
double max_bemf = config.Ke * state.omega;
voltages[EA] = max_bemf*calc_bemf_factor(state, norm_angle(theta_e));
voltages[EB] = max_bemf*calc_bemf_factor(state, norm_angle(theta_e + M_PI * (2. / 3.)));
voltages[EC] = max_bemf*calc_bemf_factor(state, norm_angle(theta_e + M_PI * (4. / 3.)));
theta_e-=M_PI * (1. / 3.);
voltages[EA] = max_bemf * calc_bemf_factor(state, norm_angle(theta_e));
voltages[EB] = max_bemf * calc_bemf_factor(state, norm_angle(theta_e + M_PI * (2. / 3.)));
voltages[EC] = max_bemf * calc_bemf_factor(state, norm_angle(theta_e + M_PI * (4. / 3.)));
}
void BLDC::calc_voltages(){
void BLDC::calc_voltages() {
const double NaN = nan("");
/* Check which phases are excited. */
bool pa = isnan(vin[0])?false:true;
bool pb = isnan(vin[1])?false:true;
bool pc = isnan(vin[2])?false:true;
bool pa = isnan(vin[0]) ? false : true;
bool pb = isnan(vin[1]) ? false : true;
bool pc = isnan(vin[2]) ? false : true;
if (pa && pb && pc) {
voltages[VA] = vin[0];
voltages[VB] = vin[1];
voltages[VC] = vin[2];
voltages[VCENTER] = (voltages[VA] + voltages[VB] + voltages[VC] - voltages[EA] - voltages[EB] - voltages[EC]) / 3.;
voltages[VCENTER] =
(voltages[VA] + voltages[VB] + voltages[VC] - voltages[EA] - voltages[EB] - voltages[EC]) / 3.;
} else if (pa && pb) {
voltages[VA] = vin[0];
voltages[VB] = vin[1];
@ -93,19 +116,21 @@ void BLDC::calc_voltages(){
voltages[VB] = voltages[EB];
voltages[VC] = voltages[EC];
voltages[VCENTER] = 0;
// return;
}
auto vmax = std::max({pa ? vin[0] : 0, pb ? vin[1] : 0, pc ? vin[2] : 0});
voltages[VCENTER] = vmax / 2;
}
void BLDC::printToStream(std::ostream& os) const {
os<<state.omega<<";"<<state.theta<<";"
<<state.ia<<";"<<state.ib<<";"<<state.ic<<";"
<<voltages[VA]<<";"<<voltages[VB]<<";"<<voltages[VC]<<";"
<<voltages[EA]<<";"<<voltages[EB]<<";"<<voltages[EC]<<";"<<voltages[VCENTER]<<";"
<<vin[0]<<";"<<vin[1]<<";"<<vin[2]<<";"<<etorque;
void BLDC::printToStream(std::ostream &os) const {
os << state.omega << ";" << state.theta << ";" << state.ia << ";" << state.ib << ";" << state.ic << ";"
<< voltages[VA] << ";" << voltages[VB] << ";" << voltages[VC] << ";" << voltages[EA] << ";" << voltages[EB]
<< ";" << voltages[EC] << ";" << voltages[VCENTER] << ";" << vin[0] << ";" << vin[1] << ";" << vin[2] << ";"
<< etorque;
}
void BLDC::rotor_dyn(const StateVector& x_, StateVector& dxdt_, const double t) {
const State x(const_cast<StateVector&>(x_));
void BLDC::rotor_dyn(const StateVector &x_, StateVector &dxdt_, const double t) {
const State x(const_cast<StateVector &>(x_));
State dxdt(dxdt_);
double theta_e = state.theta * (config.NbPoles / 2.);
/* Calculate backemf voltages. */
@ -113,18 +138,16 @@ void BLDC::rotor_dyn(const StateVector& x_, StateVector& dxdt_, const double t)
/* Calculate voltages. */
calc_voltages();
/* Electromagnetic torque. */
// if (x.omega == 0) {
// printf("ERROR: input state vector omega equals 0!!!\n");
// throw std::runtime_error("input state vector omega equals 0");
// }
// if (x.omega == 0) {
// printf("ERROR: input state vector omega equals 0!!!\n");
// throw std::runtime_error("input state vector omega equals 0");
// }
/* electrical torque */
//etorque = ((voltages[EA] * x.ia) + (voltages[EB] * x.ib) + (voltages[EC] * x.ic)) / x.omega;
// etorque = ((voltages[EA] * x.ia) + (voltages[EB] * x.ib) + (voltages[EC] * x.ic)) / x.omega;
// which is equivalent to:
etorque = config.Ke*(
x.ia * (calc_bemf_factor(state, norm_angle(theta_e))) +
x.ib * (calc_bemf_factor(state, norm_angle(theta_e + M_PI * (2. / 3.)))) +
x.ic * (calc_bemf_factor(state, norm_angle(theta_e + M_PI * (4. / 3.))))
);
etorque = config.Ke * (x.ia * (calc_bemf_factor(state, norm_angle(theta_e))) +
x.ib * (calc_bemf_factor(state, norm_angle(theta_e + M_PI * (2. / 3.)))) +
x.ic * (calc_bemf_factor(state, norm_angle(theta_e + M_PI * (4. / 3.)))));
/* Mechanical torque. */
mtorque = ((etorque * (config.NbPoles / 2)) - (config.damping * x.omega) - torque_load);
@ -149,16 +172,17 @@ void BLDC::rotor_dyn(const StateVector& x_, StateVector& dxdt_, const double t)
}
void BLDC::run(double incr) {
if(dt>incr) throw std::runtime_error("incr needs to be larger than dt");
double next_time = current_time+incr;
odeint::integrate_adaptive(make_controlled( 1.0e-10 , 1.0e-6 , stepper_type() ),
[this]( const StateVector &x , StateVector &dxdt , double t ) {this->rotor_dyn(x, dxdt,t);},
stateVector, current_time, next_time, dt);
current_time=next_time;
state.theta=norm_angle(state.theta);
if (dt > incr) throw std::runtime_error("incr needs to be larger than dt");
double next_time = current_time + incr;
odeint::integrate_adaptive(
make_controlled(1.0e-10, 1.0e-6, stepper_type()),
[this](const StateVector &x, StateVector &dxdt, double t) { this->rotor_dyn(x, dxdt, t); }, stateVector,
current_time, next_time, dt);
current_time = next_time;
state.theta = norm_angle(state.theta);
}
std::ostream& operator <<(std::ostream& os, const BLDC& bldc) {
std::ostream &operator<<(std::ostream &os, const BLDC &bldc) {
bldc.printToStream(os);
return os;
}

93
platform/src/sysc/aon.cpp
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@ -1,38 +1,38 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial implementation
//
//
////////////////////////////////////////////////////////////////////////////////
/*******************************************************************************
* Copyright (C) 2017, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Contributors:
* eyck@minres.com - initial implementation
*
*
*******************************************************************************/
#include "sysc/SiFive/aon.h"
@ -48,7 +48,7 @@ aon::aon(sc_core::sc_module_name nm)
, NAMED(erst_n_i)
, NAMED(lfclkc_o)
, NAMED(rst_o)
, NAMEDD(aon_regs, regs) {
, NAMEDD(regs, aon_regs) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive << clk_i;
@ -56,28 +56,23 @@ aon::aon(sc_core::sc_module_name nm)
sensitive << erst_n_i;
}
void aon::start_of_simulation() {
rst_o=true;
}
void aon::start_of_simulation() { rst_o = true; }
void aon::clock_cb() {
this->clk = clk_i.read();
}
void aon::clock_cb() { this->clk = clk_i.read(); }
aon::~aon() {}
aon::~aon() {} // NOLINT
void aon::reset_cb() {
if (!erst_n_i.read()){
if (!erst_n_i.read()) {
regs->reset_start();
rst_o=true;
rst_o = true;
} else {
regs->reset_stop();
rst_o=false;
rst_o = false;
}
lfclkc_o.write(sc_core::sc_time(1/32768., sc_core::SC_SEC));
lfclkc_o.write(sc_core::sc_time(1 / 32768., sc_core::SC_SEC));
}
void aon::reset_internal_cb() {
}
void aon::reset_internal_cb() {}
} /* namespace sysc */

102
platform/src/sysc/clint.cpp
View File

@ -1,46 +1,43 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial implementation
//
//
////////////////////////////////////////////////////////////////////////////////
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/SiFive/clint.h"
#include "scc/utilities.h"
#include "scc/report.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/clint_regs.h"
namespace sysc {
using namespace sc_core;
const int lfclk_mutiplier = 1 << 12;
@ -52,28 +49,29 @@ clint::clint(sc_core::sc_module_name nm)
, NAMED(rst_i)
, NAMED(mtime_int_o)
, NAMED(msip_int_o)
, NAMEDD(clint_regs, regs)
, NAMEDD(regs, clint_regs)
, cnt_fraction(0) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive << tlclk_i<<lfclk_i;
sensitive << tlclk_i << lfclk_i;
SC_METHOD(reset_cb);
sensitive << rst_i;
dont_initialize();
regs->mtimecmp.set_write_cb([this](scc::sc_register<uint64_t> &reg, uint64_t data) -> bool {
regs->mtimecmp.set_write_cb([this](scc::sc_register<uint64_t> &reg, uint64_t data, sc_core::sc_time d) -> bool {
if (!regs->in_reset()) {
reg.put(data);
this->update_mtime();
}
return true;
});
regs->mtime.set_read_cb([this](const scc::sc_register<uint64_t> &reg, uint64_t &data) -> bool {
regs->mtime.set_read_cb([this](const scc::sc_register<uint64_t> &reg, uint64_t &data, sc_core::sc_time d) -> bool {
this->update_mtime();
data = reg.get();
return true;
});
regs->mtime.set_write_cb([this](scc::sc_register<uint64_t> &reg, uint64_t data) -> bool { return false; });
regs->msip.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->mtime.set_write_cb(
[this](scc::sc_register<uint64_t> &reg, uint64_t data, sc_core::sc_time d) -> bool { return false; });
regs->msip.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
reg.put(data);
msip_int_o.write(regs->r_msip.msip);
return true;
@ -89,7 +87,7 @@ void clint::clock_cb() {
update_mtime();
}
clint::~clint() {}
clint::~clint() = default;
void clint::reset_cb() {
if (rst_i.read()) {
@ -102,16 +100,18 @@ void clint::reset_cb() {
}
void clint::update_mtime() {
if(clk>SC_ZERO_TIME){
uint64_t elapsed_clks = (sc_time_stamp()-last_updt)/clk; // get the number of clock periods since last invocation
last_updt += elapsed_clks*clk; // increment the last_updt timestamp by the number of clocks
if(elapsed_clks){ // update mtime reg if we have more than 0 elapsed clk periods
regs->r_mtime+=elapsed_clks;
if (clk > SC_ZERO_TIME) {
uint64_t elapsed_clks =
(sc_time_stamp() - last_updt) / clk; // get the number of clock periods since last invocation
last_updt += elapsed_clks * clk; // increment the last_updt timestamp by the number of clocks
if (elapsed_clks) { // update mtime reg if we have more than 0 elapsed clk periods
regs->r_mtime += elapsed_clks;
mtime_evt.cancel();
if (regs->r_mtimecmp > 0)
if(regs->r_mtimecmp > regs->r_mtime && clk > sc_core::SC_ZERO_TIME) {
sc_core::sc_time next_trigger = (clk * lfclk_mutiplier) * (regs->r_mtimecmp - regs->mtime) - cnt_fraction * clk;
LOG(DEBUG)<<"Timer fires at "<< sc_time_stamp()+next_trigger;
if (regs->r_mtimecmp > regs->r_mtime && clk > sc_core::SC_ZERO_TIME) {
sc_core::sc_time next_trigger =
(clk * lfclk_mutiplier) * (regs->r_mtimecmp - regs->mtime) - cnt_fraction * clk;
SCTRACE() << "Timer fires at " << sc_time_stamp() + next_trigger;
mtime_evt.notify(next_trigger);
mtime_int_o.write(false);
} else

111
platform/src/sysc/dcmotor.cpp
View File

@ -1,9 +1,34 @@
/*
* dcmotor.cpp
/*******************************************************************************
* Copyright (C) 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Created on: 25.07.2018
* Author: eyck
*/
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/top/dcmotor.h"
#include "scc/utilities.h"
@ -15,54 +40,74 @@ using namespace sc_core;
auto get_config = []() -> BLDC::Config {
BLDC::Config config{};
config.Ke=1./4000. ,//0.01; // V/rad/s, = 1/Kv
config.R=0.5; // Ohm
config.Ke = 1. / 4000., // 0.01; // V/rad/s, = 1/Kv
config.R = 0.5; // Ohm
config.Ke = 0.01;
config.inertia = 0.0005;
config.NbPoles = 2;
config.damping = 0.00001;
return config;
};
dc_motor::dc_motor(const sc_module_name& nm )
dc_motor::dc_motor(const sc_module_name &nm)
: sc_module(nm)
, NAMED(va_i)
, NAMED(vb_i)
, NAMED(vc_i)
, NAMED(va_o)
, NAMED(vb_o)
, NAMED(vc_o)
, NAMED(vcenter_o)
, NAMED(max_integ_step, sc_time(10, SC_US))
, NAMED(load, 0.1)
, bldc_model(get_config())
, bldc_state(bldc_model.getState())
{
, bldc_state(bldc_model.getState()) {
bldc_model.setLoad(0.0001);
SC_THREAD(thread);
}
dc_motor::~dc_motor() {
dc_motor::~dc_motor() = default;
void dc_motor::trace(sc_trace_file *trf) const {
auto &ia = bldc_state.ia;
sc_core::sc_trace(trf, bldc_state.ia, std::string(this->name()) +"." "ia");
sc_core::sc_trace(trf, bldc_state.ib, std::string(this->name()) +"." "ib");
sc_core::sc_trace(trf, bldc_state.ic, std::string(this->name()) +"." "ic");
sc_core::sc_trace(trf, bldc_state.theta, std::string(this->name()) +"." "theta");
sc_core::sc_trace(trf, bldc_state.omega, std::string(this->name()) +"." "omega");
sc_core::sc_trace(trf, vout[0], std::string(this->name()) + "." "va");
sc_core::sc_trace(trf, vout[1], std::string(this->name()) + "." "vb");
sc_core::sc_trace(trf, vout[2], std::string(this->name()) + "." "vc");
sc_core::sc_trace(trf, vout[3], std::string(this->name()) + "." "vcenter");
sc_core::sc_trace(trf, vout[4], std::string(this->name()) + "." "ea");
sc_core::sc_trace(trf, vout[5], std::string(this->name()) + "." "eb");
sc_core::sc_trace(trf, vout[6], std::string(this->name()) + "." "ec");
}
void dc_motor::trace(sc_trace_file* trf) {
auto ia=bldc_state.ia; TRACE_VAR(trf, ia);
auto ib=bldc_state.ib; TRACE_VAR(trf, ib);
auto ic=bldc_state.ic; TRACE_VAR(trf, ic);
auto theta=bldc_state.theta; TRACE_VAR(trf, theta);
auto omega=bldc_state.omega; TRACE_VAR(trf, omega);
}
void dc_motor::thread(void) {
void dc_motor::thread() {
const auto divider = 10.0;
wait(SC_ZERO_TIME);
std::array<double, 3> vin{0., 0., 0.};
const sc_time step(1, SC_US);
auto eval_model = [this](std::array<double, 3> vin, const sc_time step)->std::tuple<double, double, double> {
auto eval_model = [this](std::array<double, 3> vin, const sc_time step) -> std::array<double, 7> {
bldc_model.set_input(vin);
bldc_model.run(step.to_seconds());
return bldc_model.get_voltages();
};
while(true){
vin[0]=va_i.read();
vin[1]=vb_i.read();
vin[2]=vc_i.read();
// auto sim_res=std::async(std::launch::async, eval_model, vin, step);
wait(step);
// auto vout=sim_res.get();
auto vout = eval_model(vin, step);
va_o=std::get<0>(vout);
vb_o=std::get<1>(vout);
vc_o=std::get<2>(vout);
while (true) {
vin[0] = va_i.read();
vin[1] = vb_i.read();
vin[2] = vc_i.read();
// auto sim_res=std::async(std::launch::async, eval_model, vin, step);
auto start = sc_time_stamp();
wait(max_integ_step, va_i.value_changed_event() | vb_i.value_changed_event() | vc_i.value_changed_event());
auto diff = sc_time_stamp() - start;
if (diff.to_seconds() >= bldc_model.dt) {
vout = eval_model(vin, diff); // sim_res.get();
va_o = vout[0] / divider;
vb_o = vout[1] / divider;
vc_o = vout[2] / divider;
vcenter_o = vout[3] / divider;
}
}
}

194
platform/src/sysc/fe310.cpp Normal file
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@ -0,0 +1,194 @@
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/SiFive/fe310.h"
namespace sysc {
using namespace sc_core;
using namespace SiFive;
#ifdef HAS_VERILATOR
inline std::unique_ptr<spi> create_spi(sc_module_name nm, bool use_rtl) {
return use_rtl ? spi::create<spi_impl::rtl>("i_qspi1") : spi::create<spi_impl::beh>("i_qspi1");
}
#else
inline std::unique_ptr<spi> create_spi(sc_module_name nm, bool use_rtl) {
return spi::create<spi_impl::beh>("i_qspi1");
}
#endif
fe310::fe310(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(pins_o, 32)
, NAMED(pins_i, 32)
, NAMED(erst_n)
, NAMED(use_rtl, false)
, NAMEDD(i_core_complex, core_complex)
, NAMEDD(i_router, scc::router<>, e300_plat_t_map.size() + 2, 1)
, NAMEDD(i_uart0, uart)
, NAMEDD(i_uart1, uart)
, NAMEDC(i_qspi0, spi, spi_impl::beh)
, i_qspi1(create_spi("i_qspi1", use_rtl))
, NAMEDC(i_qspi2, spi, spi_impl::beh)
, NAMEDD(i_pwm0, pwm)
, NAMEDD(i_pwm1, pwm)
, NAMEDD(i_pwm2, pwm)
, NAMEDD(i_gpio0, gpio)
, NAMEDD(i_plic, plic)
, NAMEDD(i_aon, aon)
, NAMEDD(i_prci, prci)
, NAMEDD(i_clint, clint)
, NAMEDD(i_mem_qspi, mem_qspi_t)
, NAMEDD(i_mem_ram, mem_ram_t)
, NAMED(s_tlclk)
, NAMED(s_lfclk)
, NAMED(s_rst)
, NAMED(s_mtime_int)
, NAMED(s_msie_int)
, NAMED(s_global_int, 256)
, NAMED(s_local_int, 16)
, NAMED(s_core_int)
, NAMED(s_dummy_sck_i, 16)
, NAMED(s_dummy_sck_o, 16) {
i_core_complex->initiator(i_router->target[0]);
size_t i = 0;
for (const auto &e : e300_plat_t_map) {
i_router->initiator.at(i)(e.target);
i_router->add_target_range(i, e.start, e.size);
i++;
}
i_router->initiator.at(i)(i_mem_qspi->target);
i_router->add_target_range(i, 0x20000000, 512_MB);
i_router->initiator.at(++i)(i_mem_ram->target);
i_router->add_target_range(i, 0x80000000, 128_kB);
i_uart0->clk_i(s_tlclk);
i_uart1->clk_i(s_tlclk);
i_qspi0->clk_i(s_tlclk);
i_qspi1->clk_i(s_tlclk);
i_qspi2->clk_i(s_tlclk);
i_pwm0->clk_i(s_tlclk);
i_pwm1->clk_i(s_tlclk);
i_pwm2->clk_i(s_tlclk);
i_gpio0->clk_i(s_tlclk);
i_plic->clk_i(s_tlclk);
i_aon->clk_i(s_tlclk);
i_aon->lfclkc_o(s_lfclk);
i_prci->hfclk_o(s_tlclk); // clock driver
i_clint->tlclk_i(s_tlclk);
i_clint->lfclk_i(s_lfclk);
i_core_complex->clk_i(s_tlclk);
i_uart0->rst_i(s_rst);
i_uart1->rst_i(s_rst);
i_qspi0->rst_i(s_rst);
i_qspi1->rst_i(s_rst);
i_qspi2->rst_i(s_rst);
i_pwm0->rst_i(s_rst);
i_pwm1->rst_i(s_rst);
i_pwm2->rst_i(s_rst);
i_gpio0->rst_i(s_rst);
i_plic->rst_i(s_rst);
i_aon->rst_o(s_rst);
i_prci->rst_i(s_rst);
i_clint->rst_i(s_rst);
i_core_complex->rst_i(s_rst);
i_aon->erst_n_i(erst_n);
i_clint->mtime_int_o(s_mtime_int);
i_clint->msip_int_o(s_msie_int);
i_plic->global_interrupts_i(s_global_int);
i_plic->core_interrupt_o(s_core_int);
i_core_complex->sw_irq_i(s_msie_int);
i_core_complex->timer_irq_i(s_mtime_int);
i_core_complex->global_irq_i(s_core_int);
i_core_complex->local_irq_i(s_local_int);
pins_i(i_gpio0->pins_i);
i_gpio0->pins_o(pins_o);
i_gpio0->iof0_i[17](i_uart0->tx_o);
i_uart0->rx_i(i_gpio0->iof0_o[16]);
i_uart0->irq_o(s_global_int[3]);
i_gpio0->iof0_i[5](i_qspi1->sck_o);
i_gpio0->iof0_i[3](i_qspi1->mosi_o);
i_qspi1->miso_i(i_gpio0->iof0_o[4]);
i_gpio0->iof0_i[2](i_qspi1->scs_o[0]);
i_gpio0->iof0_i[9](i_qspi1->scs_o[2]);
i_gpio0->iof0_i[10](i_qspi1->scs_o[3]);
i_qspi0->irq_o(s_global_int[5]);
i_qspi1->irq_o(s_global_int[6]);
i_qspi2->irq_o(s_global_int[7]);
s_dummy_sck_i[0](i_uart1->tx_o);
i_uart1->rx_i(s_dummy_sck_o[0]);
i_uart1->irq_o(s_global_int[4]);
i_gpio0->iof1_i[0](i_pwm0->cmpgpio_o[0]);
i_gpio0->iof1_i[1](i_pwm0->cmpgpio_o[1]);
i_gpio0->iof1_i[2](i_pwm0->cmpgpio_o[2]);
i_gpio0->iof1_i[3](i_pwm0->cmpgpio_o[3]);
i_gpio0->iof1_i[10](i_pwm2->cmpgpio_o[0]);
i_gpio0->iof1_i[11](i_pwm2->cmpgpio_o[1]);
i_gpio0->iof1_i[12](i_pwm2->cmpgpio_o[2]);
i_gpio0->iof1_i[13](i_pwm2->cmpgpio_o[3]);
i_gpio0->iof1_i[19](i_pwm1->cmpgpio_o[0]);
i_gpio0->iof1_i[20](i_pwm1->cmpgpio_o[1]);
i_gpio0->iof1_i[21](i_pwm1->cmpgpio_o[2]);
i_gpio0->iof1_i[22](i_pwm1->cmpgpio_o[3]);
i_pwm0->cmpip_o[0](s_global_int[40]);
i_pwm0->cmpip_o[1](s_global_int[41]);
i_pwm0->cmpip_o[2](s_global_int[42]);
i_pwm0->cmpip_o[3](s_global_int[43]);
i_pwm1->cmpip_o[0](s_global_int[44]);
i_pwm1->cmpip_o[1](s_global_int[45]);
i_pwm1->cmpip_o[2](s_global_int[46]);
i_pwm1->cmpip_o[3](s_global_int[47]);
i_pwm2->cmpip_o[0](s_global_int[48]);
i_pwm2->cmpip_o[1](s_global_int[49]);
i_pwm2->cmpip_o[2](s_global_int[50]);
i_pwm2->cmpip_o[3](s_global_int[51]);
for (auto &sock : s_dummy_sck_i) sock.error_if_no_callback = false;
}
} /* namespace sysc */

267
platform/src/sysc/gpio.cpp
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@ -1,46 +1,45 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial implementation
//
//
////////////////////////////////////////////////////////////////////////////////
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/SiFive/gpio.h"
#include "sysc/sc_comm_singleton.h"
#include "scc/report.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/gpio_regs.h"
#include "sysc/sc_comm_singleton.h"
#include <limits>
namespace sysc {
using namespace sc_core;
using namespace sc_dt;
gpio::gpio(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
@ -53,95 +52,85 @@ gpio::gpio(sc_core::sc_module_name nm)
, NAMED(iof1_o, 32)
, NAMED(iof0_i, 32)
, NAMED(iof1_i, 32)
, NAMEDD(gpio_regs, regs)
, NAMED(write_to_ws, false){
, NAMEDD(regs, gpio_regs)
, NAMED(write_to_ws, false) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive << clk_i;
SC_METHOD(reset_cb);
sensitive << rst_i;
dont_initialize();
auto pins_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<sc_logic>& gp,
tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
auto pins_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->pin_input(tag, gp, delay);
return tlm::TLM_COMPLETED;
};
auto i=0U;
for(auto& s:pins_i){
auto i = 0U;
for (auto &s : pins_i) {
s.register_nb_transport(pins_i_cb, i);
++i;
}
auto iof0_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<bool>& gp,
tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
last_iof0[tag]=gp.get_value();
auto iof0_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
last_iof0[tag] = gp.get_value();
this->iof_input(tag, 0, gp, delay);
return tlm::TLM_COMPLETED;
};
i=0;
for(auto& s:iof0_i){
i = 0;
for (auto &s : iof0_i) {
s.register_nb_transport(iof0_i_cb, i);
++i;
}
auto iof1_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<bool>& gp,
tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
last_iof1[tag]=gp.get_value();
auto iof1_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
last_iof1[tag] = gp.get_value();
this->iof_input(tag, 1, gp, delay);
return tlm::TLM_COMPLETED;
};
i=0;
for(auto& s:iof1_i){
i = 0;
for (auto &s : iof1_i) {
s.register_nb_transport(iof1_i_cb, i);
++i;
}
regs->port.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
auto update_pins_cb = [this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
if (!this->regs->in_reset()) {
auto changed_bits = (reg.get() ^ data);
reg.put(data);
// read r_ports and update pins_io
update_pins();
update_pins(changed_bits);
}
return true;
});
regs->iof_en.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
if (!this->regs->in_reset()) {
enable_outputs(data, regs->r_iof_sel);
reg.put(data);
}
return true;
});
regs->iof_sel.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
if (!this->regs->in_reset()) {
enable_outputs(regs->r_iof_en, data);
reg.put(data);
}
return true;
});
};
regs->port.set_write_cb(update_pins_cb);
regs->output_en.set_write_cb(update_pins_cb);
regs->out_xor.set_write_cb(update_pins_cb);
regs->iof_en.set_write_cb(update_pins_cb);
regs->iof_sel.set_write_cb(update_pins_cb);
}
gpio::~gpio() {}
gpio::~gpio() = default;
void gpio::before_end_of_elaboration() {
if(write_to_ws.get_value()) {
LOG(TRACE)<<"Adding WS handler for "<<(std::string{"/ws/"}+name());
handler=std::make_shared<WsHandler>();
sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"}+name()).c_str(), handler);
}
if (write_to_ws.get_value()) {
SCTRACE() << "Adding WS handler for " << (std::string{"/ws/"} + name());
handler = std::make_shared<WsHandler>();
sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"} + name()).c_str(), handler);
}
}
void gpio::reset_cb() {
if (rst_i.read())
if (rst_i.read()) {
regs->reset_start();
else
} else {
regs->reset_stop();
}
update_pins(std::numeric_limits<uint32_t>::max());
}
void gpio::clock_cb() {
this->clk = clk_i.read();
}
void gpio::clock_cb() { this->clk = clk_i.read(); }
tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, size_t i, sc_dt::sc_logic val) {
tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, size_t i, sc_dt::sc_logic val) {
sc_core::sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{ tlm::BEGIN_REQ };
tlm::tlm_phase phase{tlm::BEGIN_REQ};
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_response_status(tlm::TLM_OK_RESPONSE);
gp.set_value(val);
@ -149,92 +138,81 @@ tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, size_
return phase;
}
void gpio::update_pins() {
sc_core::sc_inout_rv<32>::data_type out_val;
tlm::tlm_signal_gp<sc_dt::sc_logic> gp;
for(size_t i=0, mask = 1; i<32; ++i, mask<<=1){
if((regs->iof_en&mask == 0) || (iof0_i[i].size()==0 && iof1_i[i].size()==0)){
auto val = regs->r_output_en&mask?
regs->r_port&mask?
sc_dt::Log_1:
sc_dt::Log_0:
sc_dt::Log_Z;
tlm::tlm_phase phase = write_output(gp, i, val);
}
}
}
void gpio::enable_outputs(uint32_t new_iof_en, uint32_t new_iof_sel) {
auto changed_bits = (regs->r_iof_en^new_iof_en) | (regs->r_iof_sel^new_iof_sel);
void gpio::update_pins(uint32_t changed_bits) {
sc_core::sc_inout_rv<32>::data_type out_val;
tlm::tlm_signal_gp<sc_dt::sc_logic> gp;
for(size_t i=0, mask=1; i<32; ++i, mask<<=1){
if(changed_bits&mask){
if(new_iof_en&mask){
if((regs->r_iof_sel&mask)==0 && iof0_i[i].size()>0){
tlm::tlm_phase phase = write_output(gp, i, last_iof0[i]?sc_dt::Log_1:sc_dt::Log_0);
} else if((regs->r_iof_sel&mask)==1 && iof1_i[i].size()>0)
tlm::tlm_phase phase = write_output(gp, i, last_iof1[i]?sc_dt::Log_1:sc_dt::Log_0);
sc_logic val;
for (size_t i = 0, mask = 1; i < 32; ++i, mask <<= 1) {
if (changed_bits & mask) {
if ((regs->r_iof_en & mask != 0) && (iof0_i[i].size() == 0 || iof1_i[i].size() == 0)) {
if ((regs->r_iof_sel & mask) == 0 && iof0_i[i].size() > 0) {
val = last_iof0[i] ? sc_dt::Log_1 : sc_dt::Log_0;
} else if ((regs->r_iof_sel & mask) == 1 && iof1_i[i].size() > 0)
val = last_iof1[i] ? sc_dt::Log_1 : sc_dt::Log_0;
} else {
auto val = regs->r_output_en&mask?
regs->r_port&mask?sc_dt::Log_1:sc_dt::Log_0:
sc_dt::Log_Z;
tlm::tlm_phase phase = write_output(gp, i, val);
if (regs->r_output_en & mask)
val = regs->r_port & mask ? sc_dt::Log_1 : sc_dt::Log_0;
else
val = sc_dt::Log_Z;
if (regs->r_out_xor & mask) val = ~val;
}
tlm::tlm_phase phase = write_output(gp, i, val);
}
}
}
void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic>& gp, sc_core::sc_time& delay) {
if(delay>SC_ZERO_TIME){
wait(delay);
delay=SC_ZERO_TIME;
}
switch(gp.get_value().value()){
case sc_dt::Log_1:
regs->r_value|=1<<tag;
forward_pin_input(tag, gp);
break;
case sc_dt::Log_0:
regs->r_value&=~(1<<tag);
forward_pin_input(tag, gp);
break;
}
void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp, sc_core::sc_time &delay) {
if (delay > SC_ZERO_TIME) {
wait(delay);
delay = SC_ZERO_TIME;
}
auto mask = 1u << tag;
switch (gp.get_value().value()) {
case sc_dt::Log_1:
if (regs->r_output_en & mask == 0) regs->r_value |= mask;
forward_pin_input(tag, gp);
break;
case sc_dt::Log_0:
if (regs->r_output_en & mask == 0) regs->r_value &= ~mask;
forward_pin_input(tag, gp);
break;
}
}
void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic>& gp) {
const auto mask = 1U<<tag;
if(regs->iof_en&mask){
auto& socket = regs->iof_sel&mask?iof1_o[tag]:iof0_o[tag];
void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp) {
const auto mask = 1U << tag;
if (regs->iof_en & mask) {
auto &socket = regs->iof_sel & mask ? iof1_o[tag] : iof0_o[tag];
tlm::tlm_signal_gp<> new_gp;
for(size_t i=0; i<socket.size(); ++i){
for (size_t i = 0; i < socket.size(); ++i) {
sc_core::sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
new_gp.set_command(tlm::TLM_WRITE_COMMAND);
new_gp.set_response_status(tlm::TLM_OK_RESPONSE);
new_gp.set_value(gp.get_value().value()==sc_dt::Log_1);
new_gp.set_value(gp.get_value().value() == sc_dt::Log_1);
new_gp.update_extensions_from(gp);
socket->nb_transport_fw(new_gp, phase, delay); // we don't care about phase and sync enum
}
}
}
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay) {
if(delay>SC_ZERO_TIME){
wait(delay);
delay=SC_ZERO_TIME;
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
if (delay > SC_ZERO_TIME) {
wait(delay);
delay = SC_ZERO_TIME;
}
const auto mask = 1U<<tag;
if(regs->r_iof_en&mask){
const auto idx = regs->r_iof_sel&mask?1:0;
if(iof_idx == idx){
auto& socket = pins_o[tag];
for(size_t i=0; i<socket.size(); ++i){
const auto mask = 1U << tag;
if (regs->r_iof_en & mask) {
const auto idx = regs->r_iof_sel & mask ? 1 : 0;
if (iof_idx == idx) {
auto &socket = pins_o[tag];
for (size_t i = 0; i < socket.size(); ++i) {
sc_core::sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
tlm::tlm_signal_gp<sc_logic> new_gp;
new_gp.set_command(tlm::TLM_WRITE_COMMAND);
auto val = gp.get_value();
new_gp.set_value(val?sc_dt::Log_1:sc_dt::Log_0);
new_gp.set_value(val ? sc_dt::Log_1 : sc_dt::Log_0);
new_gp.copy_extensions_from(gp);
socket->nb_transport_fw(new_gp, phase, delay); // we don't care about phase and sync enum
gp.update_extensions_from(new_gp);
@ -244,4 +222,3 @@ void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<>& g
}
} /* namespace sysc */

94
platform/src/sysc/h_bridge.cpp
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@ -1,18 +1,45 @@
/*
* h_bridge.cpp
/*******************************************************************************
* Copyright (C) 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Created on: 25.07.2018
* Author: eyck
*/
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/top/h_bridge.h"
#include "scc/utilities.h"
#include <cmath>
namespace sysc {
using namespace sc_core;
using namespace sc_dt;
h_bridge::h_bridge(const sc_module_name& nm)
:sc_module(nm)
h_bridge::h_bridge(const sc_module_name &nm)
: sc_module(nm)
, NAMED(ha_i)
, NAMED(la_i)
, NAMED(hb_i)
@ -22,26 +49,55 @@ h_bridge::h_bridge(const sc_module_name& nm)
, NAMED(va_o)
, NAMED(vb_o)
, NAMED(vc_o)
, NAMED(vcc, 48.0)
{
, NAMED(vcc, 48.0) {
SC_METHOD(ain_cb);
sensitive<<ha_i<<la_i;
sensitive << ha_i << la_i;
SC_METHOD(bin_cb);
sensitive<<hb_i<<lb_i;
sensitive << hb_i << lb_i;
SC_METHOD(cin_cb);
sensitive<<hc_i<<lc_i;
sensitive << hc_i << lc_i;
}
h_bridge::~h_bridge() {
}
h_bridge::~h_bridge() = default;
void h_bridge::ain_cb() {
}
void h_bridge::ain_cb() { write_output(ha_i.read(), la_i.read(), va_o); }
void h_bridge::bin_cb() {
}
void h_bridge::bin_cb() { write_output(hb_i.read(), lb_i.read(), vb_o); }
void h_bridge::cin_cb() {
void h_bridge::cin_cb() { write_output(hc_i.read(), lc_i.read(), vc_o); }
void h_bridge::write_output(sc_logic h_i, sc_logic l_i, sc_out<double> &v_o) {
if (h_i == sc_dt::Log_1 && l_i == sc_dt::Log_0)
v_o.write(vcc);
else if (h_i == sc_dt::Log_0 && l_i == sc_dt::Log_1)
v_o.write(0.0);
else
v_o.write(nan(""));
/*
auto v = v_o.read();
if(h_i==Log_1 && l_i==Log_0){
if(isnan(v)){
v_o.write(0.75*vcc);
next_trigger(2, SC_US);
} else
v_o.write(vcc);
} else if(h_i==Log_0 && l_i==Log_1){
if(isnan(v)){
v_o.write(0.25*vcc);
next_trigger(2, SC_US);
} else
v_o.write(0.0);
} else {
if(v_o.read()>0.8*vcc) {
v_o.write(0.75*vcc);
next_trigger(2, SC_US);
} else if(v_o.read()>0.8*vcc) {
v_o.write(0.25*vcc);
next_trigger(2, SC_US);
} else
v_o.write(nan(""));
}
*/
}
} /* namespace sysc */

236
platform/src/sysc/hifive1.cpp
View File

@ -1,145 +1,111 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial implementation
//
//
////////////////////////////////////////////////////////////////////////////////
/*******************************************************************************
* Copyright (C) 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/SiFive/hifive1.h"
#include <sysc/top/hifive1.h>
namespace sysc {
using namespace sc_core;
using namespace sc_dt;
using namespace sysc;
hifive1::hifive1(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(pins_o, 32)
, NAMED(pins_i, 32)
hifive1::hifive1(sc_module_name nm)
: sc_module(nm)
, NAMED(erst_n)
, NAMED(i_core_complex)
, NAMED(i_router, 12, 1)
, NAMED(i_uart0)
, NAMED(i_uart1)
, NAMED(i_qspi0)
, NAMED(i_qspi1)
, NAMED(i_qspi2)
, NAMED(i_gpio0)
, NAMED(i_plic)
, NAMED(i_aon)
, NAMED(i_prci)
, NAMED(i_clint)
, NAMED(i_mem_qspi)
, NAMED(i_mem_ram)
, NAMED(s_tlclk)
, NAMED(s_rst)
, NAMED(s_global_int, 256)
, NAMED(s_local_int, 16)
, NAMED(s_core_int)
, NAMED(s_dummy, 16)
, NAMED(s_dummy_sck_i, 16)
, NAMED(s_dummy_sck_o, 16)
, NAMED(vref_i)
#define PORT_NAMING(z, n, _) , NAMED(adc_ch##n##_i)
BOOST_PP_REPEAT(8, PORT_NAMING, _)
#undef PORT_NAMING
, NAMED(ha_o)
, NAMED(la_o)
, NAMED(hb_o)
, NAMED(lb_o)
, NAMED(hc_o)
, NAMED(lc_o)
, NAMED(s_gpio, 32)
, NAMED(h_bridge, 6)
, NAMED(i_fe310)
, NAMED(i_terminal)
, NAMED(i_adc)
{
i_core_complex.initiator(i_router.target[0]);
size_t i = 0;
for (const auto &e : e300_plat_map) {
i_router.initiator.at(i)(e.target->socket);
i_router.add_target_range(i, e.start, e.size);
i++;
i_fe310.erst_n(erst_n);
for (auto i = 0U; i < s_gpio.size(); ++i) {
s_gpio[i].in(i_fe310.pins_o[i]);
i_fe310.pins_i[i](s_gpio[i].out);
}
i_router.initiator.at(i)(i_mem_qspi.target);
i_router.add_target_range(i, 0x20000000, 512_MB);
i_router.initiator.at(++i)(i_mem_ram.target);
i_router.add_target_range(i, 0x80000000, 128_kB);
// connect other units
// terminal
i_terminal.tx_o(s_gpio[16].in);
s_gpio[17].out(i_terminal.rx_i);
// adc digital io
s_gpio[2].out(i_adc.cs_i);
s_gpio[3].out(i_adc.mosi_i);
i_adc.miso_o(s_gpio[4].in);
s_gpio[5].out(i_adc.sck_i);
// adc analog inputs
i_adc.vref_i(vref_i);
i_adc.ch_i[0](adc_ch0_i);
i_adc.ch_i[1](adc_ch1_i);
i_adc.ch_i[2](adc_ch2_i);
i_adc.ch_i[3](adc_ch3_i);
i_adc.ch_i[4](adc_ch4_i);
i_adc.ch_i[5](adc_ch5_i);
i_adc.ch_i[6](adc_ch6_i);
i_adc.ch_i[7](adc_ch7_i);
// H-Bridge signal proxies
s_gpio[0].out(h_bridge[0]);
s_gpio[1].out(h_bridge[1]);
s_gpio[10].out(h_bridge[2]);
s_gpio[11].out(h_bridge[3]);
s_gpio[20].out(h_bridge[4]);
s_gpio[19].out(h_bridge[5]);
// proxy callbacks
h_bridge[0].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
ha_o.write(gp.get_value());
});
h_bridge[1].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
la_o.write(gp.get_value());
});
h_bridge[2].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
hb_o.write(gp.get_value());
});
h_bridge[3].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
lb_o.write(gp.get_value());
});
h_bridge[4].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
hc_o.write(gp.get_value());
});
h_bridge[5].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
lc_o.write(gp.get_value());
});
i_uart0.clk_i(s_tlclk);
i_uart1.clk_i(s_tlclk);
i_qspi0.clk_i(s_tlclk);
i_qspi1.clk_i(s_tlclk);
i_qspi2.clk_i(s_tlclk);
i_gpio0.clk_i(s_tlclk);
i_plic.clk_i(s_tlclk);
i_aon.clk_i(s_tlclk);
i_aon.lfclkc_o(s_lfclk);
i_prci.hfclk_o(s_tlclk); // clock driver
i_clint.tlclk_i(s_tlclk);
i_clint.lfclk_i(s_lfclk);
i_core_complex.clk_i(s_tlclk);
i_uart0.rst_i(s_rst);
i_uart1.rst_i(s_rst);
i_qspi0.rst_i(s_rst);
i_qspi1.rst_i(s_rst);
i_qspi2.rst_i(s_rst);
i_gpio0.rst_i(s_rst);
i_plic.rst_i(s_rst);
i_aon.rst_o(s_rst);
i_prci.rst_i(s_rst);
i_clint.rst_i(s_rst);
i_core_complex.rst_i(s_rst);
i_aon.erst_n_i(erst_n);
i_clint.mtime_int_o(s_mtime_int);
i_clint.msip_int_o(s_msie_int);
i_plic.global_interrupts_i(s_global_int);
i_plic.core_interrupt_o(s_core_int);
i_core_complex.sw_irq_i(s_msie_int);
i_core_complex.timer_irq_i(s_mtime_int);
i_core_complex.global_irq_i(s_core_int);
i_core_complex.local_irq_i(s_local_int);
pins_i(i_gpio0.pins_i);
i_gpio0.pins_o(pins_o);
i_gpio0.iof0_i[17](i_uart0.tx_o);
i_uart0.rx_i(i_gpio0.iof0_o[16]);
i_uart0.irq_o(s_global_int[3]);
i_gpio0.iof0_i[2](i_qspi1.scs_o[0]);
i_gpio0.iof0_i[3](i_qspi1.mosi_o);
i_qspi1.miso_i(i_gpio0.iof0_o[4]);
i_gpio0.iof0_i[5](i_qspi1.sck_o);
i_gpio0.iof0_i[9](i_qspi1.scs_o[2]);
i_gpio0.iof0_i[10](i_qspi1.scs_o[3]);
i_qspi0.irq_o(s_global_int[5]);
i_qspi1.irq_o(s_global_int[6]);
i_qspi2.irq_o(s_global_int[7]);
s_dummy_sck_i[0](i_uart1.tx_o);
i_uart1.rx_i(s_dummy_sck_o[0]);
i_uart1.irq_o(s_global_int[4]);
for(auto& sock:s_dummy_sck_i) sock.error_if_no_callback=false;
}
} /* namespace sysc */

86
platform/src/sysc/mcp3008.cpp
View File

@ -1,86 +0,0 @@
/*
* mcp3008.cpp
*
* Created on: 17.07.2018
* Author: eyck
*/
#include "sysc/top/mcp3008.h"
#include <scc/report.h>
#include <util/ities.h>
namespace sysc {
mcp3008::mcp3008(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(sck_i)
, NAMED(miso_o)
, NAMED(mosi_i)
, NAMED(cs_i)
, NAMED(vref_i)
, NAMED(ch_i, 8)
, last_tx_start(sc_core::SC_ZERO_TIME)
{
sck_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, tlm::tlm_phase& phase, sc_core::sc_time& delay)
-> tlm::tlm_sync_enum{
return tlm::TLM_COMPLETED;
});
mosi_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, tlm::tlm_phase& phase, sc_core::sc_time& delay)
-> tlm::tlm_sync_enum{
if(cs_v==sc_dt::Log_0)
return receive(gp, phase, delay);
});
cs_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, tlm::tlm_phase& phase, sc_core::sc_time& delay)
-> tlm::tlm_sync_enum{
if(cs_v!=sc_dt::Log_0 && gp.get_value()==sc_dt::Log_0){
idx=0; // falling edge
rx_bits=0;
}
cs_v=gp.get_value();
return tlm::TLM_COMPLETED;
});
}
mcp3008::~mcp3008() {
}
tlm::tlm_sync_enum mcp3008::receive(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, tlm::tlm_phase& phase, sc_core::sc_time& delay) {
gp.get_extension(ext);
if(ext){
if( ext->start_time!=last_tx_start){
assert(ext->tx.data_bits==8);
rx_bytes[idx]=bit_sub<0,8>(ext->tx.m2s_data);
if(idx==1)
do_conversion();
ext->tx.s2m_data=tx_bytes[idx];
ext->tx.s2m_data_valid=true;
idx++;
last_tx_start=ext->start_time;
}
}
return tlm::TLM_COMPLETED;
}
void mcp3008::do_conversion() {
if(rx_bytes[0]==0x1){
auto mode = bit_sub<7,1>(rx_bytes[1]);
auto channel = bit_sub<4,3>(rx_bytes[1]);
auto vref=vref_i.read();
if(mode){ // single ended
auto inp = ch_i[channel].read();
auto norm = inp/vref*1024.0;
auto res = static_cast<int>(norm);
CLOG(DEBUG, SystemC)<<"Converting "<<inp<<" to "<<norm<<" as int "<<res;
tx_bytes[1]=bit_sub<8,2>(res);
tx_bytes[2]=bit_sub<0,8>(res);
} else {
tx_bytes[1]=0;
tx_bytes[2]=0;
}
}
}
} /* namespace sysc */

202
platform/src/sysc/mcp_adc.cpp Normal file
View File

@ -0,0 +1,202 @@
/*******************************************************************************
* Copyright (C) 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include <scc/report.h>
#include <sysc/top/mcp_adc.h>
#include <util/ities.h>
namespace sysc {
mcp_3008::mcp_3008(sc_core::sc_module_name nm)
: sysc::mcp_adc(nm, 8)
, last_tx_start(sc_core::SC_ZERO_TIME) {
sck_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum { return tlm::TLM_COMPLETED; });
mosi_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
if (cs_v == sc_dt::Log_0) return receive(gp, phase, delay);
return tlm::TLM_COMPLETED;
});
cs_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
if (cs_v != sc_dt::Log_0 && gp.get_value() == sc_dt::Log_0) {
idx = 0; // falling edge
rx_bits = 0;
}
cs_v = gp.get_value();
return tlm::TLM_COMPLETED;
});
}
tlm::tlm_sync_enum mcp_3008::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) {
gp.get_extension(ext);
if (ext) {
if (ext->start_time != last_tx_start) {
assert(ext->tx.data_bits == 8);
rx_bytes[idx] = bit_sub<0, 8>(ext->tx.m2s_data);
if (idx == 1) do_conversion();
ext->tx.s2m_data = tx_bytes[idx];
ext->tx.s2m_data_valid = true;
idx++;
last_tx_start = ext->start_time;
}
}
return tlm::TLM_COMPLETED;
}
void mcp_3008::do_conversion() {
if (rx_bytes[0] == 0x1) {
auto mode = bit_sub<7, 1>(rx_bytes[1]);
auto channel = bit_sub<4, 3>(rx_bytes[1]);
auto vref = vref_i.read();
if (mode) { // single ended
auto inp = ch_i[channel].read();
auto norm = 1024.0 * inp / vref;
auto res = static_cast<int>(norm);
SCDEBUG(this->name()) << "Converting " << inp << " to " << norm << " as int " << res;
tx_bytes[1] = bit_sub<8, 2>(res);
tx_bytes[2] = bit_sub<0, 8>(res);
} else {
tx_bytes[1] = 0;
tx_bytes[2] = 0;
}
}
}
mcp_3208::mcp_3208(sc_core::sc_module_name nm)
: sysc::mcp_adc(nm, 8)
, ext(nullptr)
, last_tx_start(sc_core::SC_ZERO_TIME) {
sck_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
auto ret = tlm::TLM_COMPLETED;
if (cs_v == sc_dt::Log_0) ret = receive(gp, phase, delay);
sck_v = gp.get_value();
return ret;
});
mosi_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
mosi_v = gp.get_value();
return tlm::TLM_COMPLETED;
});
cs_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
if (cs_v != sc_dt::Log_0 && gp.get_value() == sc_dt::Log_0) { // falling edge of CS
idx = 0;
rx_bits = byte_offs = 0;
bit_offs = 7;
}
cs_v = gp.get_value();
return tlm::TLM_COMPLETED;
});
SC_METHOD(sample_inputs);
sensitive << clk_sample_evt;
}
tlm::tlm_sync_enum mcp_3208::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) {
gp.get_extension(ext);
if (ext) {
if (ext->start_time != last_tx_start) {
assert(ext->tx.data_bits == 8);
if (ext->tx.m2s_data_valid) {
rx_bytes[idx] = bit_sub<0, 8>(ext->tx.m2s_data);
if (idx == 1) do_conversion();
ext->tx.s2m_data = tx_bytes[idx];
ext->tx.s2m_data_valid = true;
last_tx_start = ext->start_time;
idx++;
}
}
} else if (gp.get_value() == sc_dt::SC_LOGIC_1 && sck_v == sc_dt::SC_LOGIC_0) // sample an rising edge
clk_sample_evt.notify(sc_core::SC_ZERO_TIME);
return tlm::TLM_COMPLETED;
}
void mcp_3208::sample_inputs() {
if (byte_offs >= 3) return;
if (bit_offs == 7) {
rx_bytes[byte_offs] = 0;
if (byte_offs == 0) tx_bytes[0] = tx_bytes[1] = tx_bytes[2] = 0;
}
auto mask = 1 << bit_offs;
if (mosi_v == sc_dt::SC_LOGIC_1) rx_bytes[byte_offs] |= mask;
miso_o.write_now(tx_bytes[byte_offs] & mask ? sc_dt::SC_LOGIC_1 : sc_dt::SC_LOGIC_0);
// increment counters
if (bit_offs == 0) {
bit_offs = 7;
byte_offs++;
} else
bit_offs--;
// sample if in the middle of second byte
if (byte_offs == 1 && bit_offs == 4) do_conversion();
}
void mcp_3208::do_conversion() {
if (rx_bytes[0] & 0x4) {
auto mode = bit_sub<1, 1>(rx_bytes[0]);
auto channel = bit_sub<0, 1>(rx_bytes[0]) * 4 + bit_sub<6, 2>(rx_bytes[1]);
auto vref = vref_i.read();
if (mode) { // single ended
auto inp = ch_i[channel].read();
auto norm = 4096.0 * inp / vref;
auto res = static_cast<int>(norm);
SCDEBUG(this->name()) << "Converting channel " << channel << " " << inp << "V to " << norm << " as int "
<< res;
tx_bytes[1] = bit_sub<8, 4>(res);
tx_bytes[2] = bit_sub<0, 8>(res);
} else {
tx_bytes[1] = 0;
tx_bytes[2] = 0;
}
}
}
template <>
std::unique_ptr<mcp_adc> mcp_adc::create<mcp_3008>(sc_core::sc_module_name nm) {
auto *res = new mcp_3008(nm);
return std::unique_ptr<mcp_adc>(res);
}
template <>
std::unique_ptr<mcp_adc> mcp_adc::create<mcp_3208>(sc_core::sc_module_name nm) {
auto *res = new mcp_3208(nm);
return std::unique_ptr<mcp_adc>(res);
}
} /* namespace sysc */

139
platform/src/sysc/plic.cpp
View File

@ -1,43 +1,39 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial implementation
//
//
////////////////////////////////////////////////////////////////////////////////
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include <sysc/SiFive/plic.h>
#include <scc/utilities.h>
#include <scc/report.h>
#include <scc/utilities.h>
#include <sysc/SiFive/gen/plic_regs.h>
namespace sysc {
@ -49,13 +45,18 @@ plic::plic(sc_core::sc_module_name nm)
, NAMED(rst_i)
, NAMED(global_interrupts_i, 256)
, NAMED(core_interrupt_o)
, NAMEDD(plic_regs, regs)
, NAMEDD(regs, plic_regs)
{
regs->registerResources(*this);
// register callbacks
init_callbacks();
regs->claim_complete.set_write_cb(m_claim_complete_write_cb);
regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t> reg, uint32_t v, sc_core::sc_time d) -> bool {
reg.put(v);
reset_pending_int(v);
// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
// todo: reset related interrupt and find next high-prio interrupt
return true;
});
// port callbacks
SC_METHOD(global_int_port_cb);
@ -72,21 +73,9 @@ plic::plic(sc_core::sc_module_name nm)
dont_initialize();
}
plic::~plic() {}
plic::~plic() {}// NOLINT
void plic::init_callbacks() {
m_claim_complete_write_cb = [=](scc::sc_register<uint32_t> reg, uint32_t v) -> bool {
reg.put(v);
reset_pending_int(v);
// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
// todo: reset related interrupt and find next high-prio interrupt
return true;
};
}
void plic::clock_cb() {
this->clk = clk_i.read();
}
void plic::clock_cb() { this->clk = clk_i.read(); }
void plic::reset_cb() {
if (rst_i.read())
@ -112,67 +101,67 @@ void plic::reset_cb() {
// - complete-reg write register content
void plic::global_int_port_cb() {
auto handle_pending = false;
// set related pending bit if enable is set for incoming global_interrupt
for (uint32_t i = 1; i < 256; i++) {
auto reg_idx = i>>5;
auto bit_ofs = i & 0x1F;
auto reg_idx = i >> 5;
auto bit_ofs = i & 0x1F;
bool enable = regs->r_enabled[reg_idx] & (0x1 << bit_ofs); // read enable bit
if (enable && global_interrupts_i[i].read() == 1) {
regs->r_pending[reg_idx] = regs->r_pending[reg_idx] | (0x1 << bit_ofs);
LOG(DEBUG) << "pending interrupt identified: " << i;
handle_pending = true;
SCDEBUG(this->name()) << "pending interrupt identified: " << i;
}
}
handle_pending_int();
if (handle_pending) handle_pending_int();
}
void plic::handle_pending_int() {
// identify high-prio pending interrupt and raise a core-interrupt
uint32_t claim_int = 0; // claim interrupt
uint32_t claim_prio = 0; // related priority (highest prio interrupt wins the race)
bool raise_int = 0;
uint32_t thold = regs->r_threshold.threshold; // threshold value
auto claim_int = 0U; // claim interrupt
auto claim_prio = 0U; // related priority (highest prio interrupt wins the race)
auto raise_int = false;
auto thold = regs->r_threshold.threshold; // threshold value
for (uint32_t i = 1; i < 255; i++) {
auto reg_idx = i>>5;
auto bit_ofs = i & 0x1F;
for (size_t i = 1; i < 255; i++) {
auto reg_idx = i >> 5;
auto bit_ofs = i & 0x1F;
bool pending = (regs->r_pending[reg_idx] & (0x1 << bit_ofs)) ? true : false;
uint32_t prio = regs->r_priority[i - 1].priority; // read priority value
auto prio = regs->r_priority[i].priority; // read priority value
if (pending && thold < prio) {
regs->r_pending[reg_idx] = regs->r_pending[reg_idx] | (0x1 << bit_ofs);
// below condition ensures implicitly that lowest id is selected in case of multiple identical
// priority-interrupts
if (prio > claim_prio) {
claim_prio = prio;
claim_int = i;
raise_int = 1;
LOG(DEBUG) << "pending interrupt activated: " << i;
raise_int = true;
SCDEBUG(this->name()) << "pending interrupt activated: " << i;
}
}
}
if (raise_int) {
regs->r_claim_complete = claim_int;
core_interrupt_o.write(1);
core_interrupt_o.write(true);
// todo: evluate clock period
} else {
regs->r_claim_complete = 0;
LOG(DEBUG) << "no further pending interrupt.";
SCDEBUG(this->name()) << "no further pending interrupt.";
}
}
void plic::reset_pending_int(uint32_t irq) {
// todo: evaluate enable register (see spec)
// todo: make sure that pending is set, otherwise don't reset irq ... read spec.
LOG(TRACE) << "reset pending interrupt: " << irq;
SCTRACE(this->name()) << "reset pending interrupt: " << irq;
// reset related pending bit
auto reg_idx = irq>>5;
auto bit_ofs = irq & 0x1F;
auto reg_idx = irq >> 5;
auto bit_ofs = irq & 0x1F;
regs->r_pending[reg_idx] &= ~(0x1 << bit_ofs);
core_interrupt_o.write(0);
core_interrupt_o.write(false);
// evaluate next pending interrupt
handle_pending_int();

126
platform/src/sysc/prci.cpp
View File

@ -1,38 +1,34 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial implementation
//
//
////////////////////////////////////////////////////////////////////////////////
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/SiFive/prci.h"
@ -40,13 +36,14 @@
#include "sysc/SiFive/gen/prci_regs.h"
namespace sysc {
using namespace sc_core;
prci::prci(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(hfclk)
, NAMED(rst_i)
, NAMED(hfclk_o)
, NAMEDD(prci_regs, regs) {
, NAMEDD(regs, prci_regs) {
regs->registerResources(*this);
SC_METHOD(reset_cb);
sensitive << rst_i;
@ -57,25 +54,25 @@ prci::prci(sc_core::sc_module_name nm)
sensitive << hfrosc_en_evt;
dont_initialize();
regs->hfxosccfg.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->hfxosccfg.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
reg.put(data);
if (this->regs->r_hfxosccfg.hfxoscen==1) { // check rosc_en
if (this->regs->r_hfxosccfg.hfxoscen == 1) { // check rosc_en
this->hfxosc_en_evt.notify(1, sc_core::SC_US);
} else {
this->hfxosc_en_evt.notify(SC_ZERO_TIME);
}
return true;
});
regs->hfrosccfg.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->hfrosccfg.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
reg.put(data);
if (this->regs->r_hfrosccfg.hfroscen==1) { // check rosc_en
if (this->regs->r_hfrosccfg.hfroscen == 1) { // check rosc_en
this->hfrosc_en_evt.notify(1, sc_core::SC_US);
} else {
this->hfrosc_en_evt.notify(SC_ZERO_TIME);
}
return true;
});
regs->pllcfg.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->pllcfg.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
reg.put(data);
auto &pllcfg = this->regs->r_pllcfg;
if (pllcfg.pllbypass == 0 && pllcfg.pllq != 0) { // set pll_lock if pll is selected
@ -84,15 +81,15 @@ prci::prci(sc_core::sc_module_name nm)
update_hfclk();
return true;
});
regs->plloutdiv.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->plloutdiv.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
reg.put(data);
update_hfclk();
return true;
});
hfxosc_clk=62.5_ns;
hfxosc_clk = 62.5_ns;
}
prci::~prci() {}
prci::~prci() = default;
void prci::reset_cb() {
if (rst_i.read())
@ -104,41 +101,42 @@ void prci::reset_cb() {
}
void prci::hfxosc_cb() {
this->regs->r_hfxosccfg.hfxoscrdy=0;
this->regs->r_hfxosccfg.hfxoscrdy = 0;
this->hfxosc_en_evt.notify(1, sc_core::SC_US);
}
void prci::hfxosc_en_cb() {
update_hfclk();
if(regs->r_hfxosccfg.hfxoscen==1)// set rosc_rdy
regs->r_hfxosccfg.hfxoscrdy =1;
if (regs->r_hfxosccfg.hfxoscen == 1) // set rosc_rdy
regs->r_hfxosccfg.hfxoscrdy = 1;
else
regs->r_hfxosccfg.hfxoscrdy =0;
regs->r_hfxosccfg.hfxoscrdy = 0;
}
void prci::hfrosc_en_cb() {
update_hfclk();
auto& hfrosccfg=regs->r_hfrosccfg;
if(regs->r_hfrosccfg.hfroscen==1) {// set rosc_rdy
regs->r_hfrosccfg.hfroscrdy =1;
auto &hfrosccfg = regs->r_hfrosccfg;
if (regs->r_hfrosccfg.hfroscen == 1) { // set rosc_rdy
regs->r_hfrosccfg.hfroscrdy = 1;
} else {
regs->r_hfrosccfg.hfroscrdy =0;
regs->r_hfrosccfg.hfroscrdy = 0;
}
}
void prci::update_hfclk() {
auto& hfrosccfg=regs->r_hfrosccfg;
auto& pllcfg=regs->r_pllcfg;
auto& plldiv=regs->r_plloutdiv;
hfrosc_clk = sc_core::sc_time(((hfrosccfg.hfroscdiv+1)*1.0)/(1125000.0*(hfrosccfg.hfrosctrim+1)), sc_core::SC_SEC);
auto pll_ref = pllcfg.pllrefsel==1?hfxosc_clk:hfrosc_clk;
auto r = pllcfg.pllr+1;
auto f = 2*(pllcfg.pllf+1);
auto q = 1<<pllcfg.pllq;
auto pll_out = pllcfg.pllbypass==1 || pllcfg.plllock==0?pll_ref:((pll_ref*r)/f)*q;
auto pll_res = plldiv&0x100?pll_out:2*pll_out*((plldiv&0x3f)+1);
hfclk = pllcfg.pllsel?pll_res:hfrosc_clk;
auto &hfrosccfg = regs->r_hfrosccfg;
auto &pllcfg = regs->r_pllcfg;
auto &plldiv = regs->r_plloutdiv;
uint32_t trim = hfrosccfg.hfrosctrim;
uint32_t div = hfrosccfg.hfroscdiv;
hfrosc_clk = sc_core::sc_time(((div + 1) * 1.0) / (70000000 + 12000.0 * trim), sc_core::SC_SEC);
auto pll_ref = pllcfg.pllrefsel == 1 ? hfxosc_clk : hfrosc_clk;
auto r = pllcfg.pllr + 1;
auto f = 2 * (pllcfg.pllf + 1);
auto q = 1 << pllcfg.pllq;
auto pll_out = pllcfg.pllbypass == 1 || pllcfg.plllock == 0 ? pll_ref : ((pll_ref * r) / f) * q;
auto pll_res = plldiv & 0x100 ? pll_out : 2 * pll_out * ((plldiv & 0x3f) + 1);
hfclk = pllcfg.pllsel ? pll_res : hfrosc_clk;
hfclk_o.write(hfclk);
}

231
platform/src/sysc/pwm.cpp Normal file
View File

@ -0,0 +1,231 @@
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/SiFive/pwm.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/pwm_regs.h"
using namespace sysc;
using namespace sc_core;
pwm::pwm(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMED(cmpgpio_o, 4)
, NAMED(cmpip_o, 4)
, NAMEDD(regs, pwm_regs)
, current_cnt(0)
, last_cnt_update() {
regs->registerResources(*this);
regs->pwmcfg.set_write_cb(
[this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
if (d.value()) wait(d);
reg.put(data);
update_counter();
return true;
});
regs->pwmcount.set_write_cb(
[this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
if (d.value()) wait(d);
reg.put(data);
update_counter();
current_cnt = data;
clk_remainder = 0.;
return true;
});
regs->pwmcount.set_read_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data,
sc_core::sc_time d) -> bool {
auto offset = regs->r_pwmcfg.pwmenalways || regs->r_pwmcfg.pwmenoneshot ? static_cast<int>(get_pulses(d)) : 0;
data = current_cnt + offset;
regs->r_pwmcount.pwmcount = data;
return true;
});
regs->pwms.set_write_cb(
[this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool { return false; });
regs->pwms.set_read_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
auto offset = regs->r_pwmcfg.pwmenalways || regs->r_pwmcfg.pwmenoneshot ? static_cast<int>(get_pulses(d)) : 0;
auto cnt = current_cnt + offset;
data = (cnt >> regs->r_pwmcfg.pwmscale) & 0xffff;
regs->r_pwms.pwms = static_cast<uint16_t>(data);
return true;
});
regs->pwmcmp0.set_write_cb(
[this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
reg.put(data);
update_counter();
return true;
});
regs->pwmcmp1.set_write_cb(
[this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
reg.put(data);
update_counter();
return true;
});
regs->pwmcmp2.set_write_cb(
[this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
reg.put(data);
update_counter();
return true;
});
regs->pwmcmp3.set_write_cb(
[this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
reg.put(data);
update_counter();
return true;
});
SC_METHOD(clock_cb);
sensitive << clk_i;
SC_METHOD(reset_cb);
sensitive << rst_i;
SC_METHOD(update_counter);
sensitive << update_counter_evt;
dont_initialize();
}
void pwm::clock_cb() {
update_counter();
clk = clk_i.read();
}
pwm::~pwm() = default;
void pwm::reset_cb() {
if (rst_i.read()) {
regs->reset_start();
} else {
regs->reset_stop();
}
}
void pwm::update_counter() {
auto now = sc_time_stamp();
if (now == SC_ZERO_TIME) return;
update_counter_evt.cancel();
if (regs->r_pwmcfg.pwmenalways || regs->r_pwmcfg.pwmenoneshot) {
std::array<bool, 4> pwmcmp_new_ip{false, false, false, false};
auto dpulses = get_pulses(SC_ZERO_TIME);
auto pulses = static_cast<int>(dpulses);
clk_remainder += dpulses - pulses;
if (clk_remainder > 1) {
pulses++;
clk_remainder -= 1.0;
}
if (reset_cnt) {
current_cnt = 0;
reset_cnt = false;
} else if (last_enable)
current_cnt += pulses;
auto pwms = (current_cnt >> regs->r_pwmcfg.pwmscale) & 0xffff;
auto next_trigger_time =
(0xffff - pwms) * (1 << regs->r_pwmcfg.pwmscale) * clk; // next trigger based on wrap around
if (pwms == 0xffff) { // wrap around calculation
reset_cnt = true;
next_trigger_time = clk;
regs->r_pwmcfg.pwmenoneshot = 0;
}
auto pwms0 = (regs->r_pwmcfg.pwmcmp0center && (pwms & 0x8000) == 1) ? pwms ^ 0xffff : pwms;
if (pwms0 >= regs->r_pwmcmp0.pwmcmp0) {
pwmcmp_new_ip[0] = true;
regs->r_pwmcfg.pwmenoneshot = 0;
if (regs->r_pwmcfg.pwmzerocmp) {
reset_cnt = true;
next_trigger_time = clk;
}
} else {
pwmcmp_new_ip[0] = false;
// TODO: add correct calculation for regs->r_pwmcfg.pwmcmpXcenter==1
auto nt = (regs->r_pwmcmp0.pwmcmp0 - pwms0) * (1 << regs->r_pwmcfg.pwmscale) * clk;
next_trigger_time = nt < next_trigger_time ? nt : next_trigger_time;
}
auto pwms1 = (regs->r_pwmcfg.pwmcmp0center && (pwms & 0x8000) == 1) ? pwms ^ 0xffff : pwms;
if (pwms1 >= regs->r_pwmcmp1.pwmcmp0) {
pwmcmp_new_ip[1] = true;
} else {
pwmcmp_new_ip[1] = false;
// TODO: add correct calculation for regs->r_pwmcfg.pwmcmpXcenter==1
auto nt = (regs->r_pwmcmp0.pwmcmp0 - pwms0) * (1 << regs->r_pwmcfg.pwmscale) * clk;
next_trigger_time = nt < next_trigger_time ? nt : next_trigger_time;
}
auto pwms2 = (regs->r_pwmcfg.pwmcmp0center && (pwms & 0x8000) == 1) ? pwms ^ 0xffff : pwms;
if (pwms2 >= regs->r_pwmcmp2.pwmcmp0) {
pwmcmp_new_ip[2] = true;
} else {
pwmcmp_new_ip[2] = false;
// TODO: add correct calculation for regs->r_pwmcfg.pwmcmpXcenter==1
auto nt = (regs->r_pwmcmp0.pwmcmp0 - pwms0) * regs->r_pwmcfg.pwmscale * clk;
next_trigger_time = nt < next_trigger_time ? nt : next_trigger_time;
}
auto pwms3 = (regs->r_pwmcfg.pwmcmp0center && (pwms & 0x8000) == 1) ? pwms ^ 0xffff : pwms;
if (pwms3 >= regs->r_pwmcmp3.pwmcmp0) {
pwmcmp_new_ip[3] = true;
} else {
pwmcmp_new_ip[3] = false;
// TODO: add correct calculation for regs->r_pwmcfg.pwmcmpXcenter==1
auto nt = (regs->r_pwmcmp0.pwmcmp0 - pwms0) * (1 << regs->r_pwmcfg.pwmscale) * clk;
next_trigger_time = nt < next_trigger_time ? nt : next_trigger_time;
}
for (size_t i = 0; i < 4; ++i) {
// write gpio bits depending of gang bit
if (regs->r_pwmcfg & (1 < (24 + i)))
write_cmpgpio(i, pwmcmp_new_ip[i] && !pwmcmp_new_ip[(i + 1) % 4]);
else
write_cmpgpio(i, pwmcmp_new_ip[i]);
// detect rising edge and set ip bit if found
if (!pwmcmp_ip[i] && pwmcmp_new_ip[i]) regs->r_pwmcfg |= 1 << (28 + i);
pwmcmp_ip[i] = pwmcmp_new_ip[i];
}
last_enable = true;
update_counter_evt.notify(next_trigger_time);
} else
last_enable = false;
cmpip_o[0].write(regs->r_pwmcfg.pwmcmp0ip != 0);
cmpip_o[1].write(regs->r_pwmcfg.pwmcmp1ip != 0);
cmpip_o[2].write(regs->r_pwmcfg.pwmcmp2ip != 0);
cmpip_o[3].write(regs->r_pwmcfg.pwmcmp3ip != 0);
last_cnt_update = now;
last_clk = clk;
}
void pwm::write_cmpgpio(size_t index, bool val) {
if (cmpgpio_o[index].get_interface()) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
tlm::tlm_signal_gp<> gp;
sc_core::sc_time delay(SC_ZERO_TIME);
gp.set_value(val);
cmpgpio_o[index]->nb_transport_fw(gp, phase, delay);
}
}

257
platform/src/sysc/sc_comm_singleton.cpp
View File

@ -1,55 +1,51 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial implementation
//
//
////////////////////////////////////////////////////////////////////////////////
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/sc_comm_singleton.h"
#include "seasocks/PrintfLogger.h"
#include "seasocks/ResponseWriter.h"
#include "seasocks/Server.h"
#include "seasocks/StringUtil.h"
#include "seasocks/util/Json.h"
#include "seasocks/ResponseWriter.h"
#include "seasocks/util/RootPageHandler.h"
#include "seasocks/util/CrackedUriPageHandler.h"
#include "seasocks/util/Json.h"
#include "seasocks/util/RootPageHandler.h"
#include "seasocks/util/StaticResponseHandler.h"
#include <cstdio>
#include <csignal>
#include <sys/stat.h>
#include <cerrno>
#include <csignal>
#include <cstdio>
#include <fcntl.h>
#include <sys/stat.h>
#include <unistd.h>
namespace sysc {
@ -58,127 +54,116 @@ using namespace seasocks;
using namespace std;
namespace {
inline void die(){perror(nullptr);exit(errno);}
inline void die() {
perror(nullptr);
exit(errno);
}
}
sc_comm_singleton::sc_comm_singleton(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, m_serv(new Server(std::make_shared<PrintfLogger>(Logger::Level::WARNING)))
, needs_client(false)
, client_started(false){
m_serv->addPageHandler(std::make_shared<DefaultPageHandler>(*this));
, client_started(false) {
m_serv->addPageHandler(std::make_shared<DefaultPageHandler>(*this));
}
sc_comm_singleton::~sc_comm_singleton() {
//Join the thread with the main thread
t.join();
// Join the thread with the main thread
t.join();
}
void sc_comm_singleton::start_of_simulation() {
//Launch a thread
t=std::thread(&sc_comm_singleton::thread_func, this);
if(needs_client) start_client();
// Launch a thread
t = std::thread(&sc_comm_singleton::thread_func, this);
if (needs_client) start_client();
}
void sc_comm_singleton::end_of_simulation() {
get_server().terminate();
}
void sc_comm_singleton::end_of_simulation() { get_server().terminate(); }
void sc_comm_singleton::start_client() {
if(client_started) return;
std::stringstream ss;
if (client_started) return;
std::stringstream ss;
#ifndef WIN32
if(fork()==0){
// daemonizing, see http://www.microhowto.info/howto/cause_a_process_to_become_a_daemon_in_c.html#id2407077
// Fork, allowing the parent process to terminate.
pid_t pid = fork();
if (pid == -1) {
die();
} else if (pid != 0) {
_exit(0);
}
// Start a new session for the daemon.
if (setsid()==-1) die();
// Fork again, allowing the parent process to terminate.
signal(SIGHUP,SIG_IGN);
pid=fork();
if (pid == -1) {
die();
} else if (pid != 0) {
_exit(0);
}
// Set the current working directory to the root directory.
if (chdir("/") == -1) die();
// Set the user file creation mask to zero.
umask(0);
if (fork() == 0) {
// daemonizing, see http://www.microhowto.info/howto/cause_a_process_to_become_a_daemon_in_c.html#id2407077
// Fork, allowing the parent process to terminate.
pid_t pid = fork();
if (pid == -1) {
die();
} else if (pid != 0) {
_exit(0);
}
// Start a new session for the daemon.
if (setsid() == -1) die();
// Fork again, allowing the parent process to terminate.
signal(SIGHUP, SIG_IGN);
pid = fork();
if (pid == -1) {
die();
} else if (pid != 0) {
_exit(0);
}
// Set the current working directory to the root directory.
if (chdir("/") == -1) die();
// Set the user file creation mask to zero.
umask(0);
// Close then reopen standard file descriptors.
close(STDIN_FILENO);
close(STDOUT_FILENO);
close(STDERR_FILENO);
if (open("/dev/null",O_RDONLY) == -1) die();
if (open("/dev/null",O_WRONLY) == -1) die();
if (open("/dev/null",O_RDWR) == -1) die();
// now do what is needed
ss<<"x-www-browser http://localhost:9090/ws.html"; //Linux
auto res = system (ss.str().c_str());
if(res==0) exit(0);
ss.str("");
ss<<"xdg-open http://localhost:9090/ws.html"; // Linux
res=system (ss.str().c_str());
if(res==0) exit(0);
ss.str("");
ss<<"open http://localhost:9090/ws.html"; // MacOS
res=system (ss.str().c_str());
exit(0);
}
// #else
// on windows should be open, see https://www.experts-exchange.com/articles/1595/Execute-a-Program-with-C.html
// Close then reopen standard file descriptors.
close(STDIN_FILENO);
close(STDOUT_FILENO);
close(STDERR_FILENO);
if (open("/dev/null", O_RDONLY) == -1) die();
if (open("/dev/null", O_WRONLY) == -1) die();
if (open("/dev/null", O_RDWR) == -1) die();
// now do what is needed
ss << "x-www-browser http://localhost:9090/ws.html"; // Linux
auto res = system(ss.str().c_str());
if (res == 0) exit(0);
ss.str("");
ss << "xdg-open http://localhost:9090/ws.html"; // Linux
res = system(ss.str().c_str());
if (res == 0) exit(0);
ss.str("");
ss << "open http://localhost:9090/ws.html"; // MacOS
res = system(ss.str().c_str());
exit(0);
}
// #else
// on windows should be open, see https://www.experts-exchange.com/articles/1595/Execute-a-Program-with-C.html
#endif
client_started=true;
client_started = true;
}
void sc_comm_singleton::registerWebSocketHandler(const char* endpoint,
std::shared_ptr<WebSocket::Handler> handler,
bool allowCrossOriginRequests) {
get_server().addWebSocketHandler(endpoint, handler, allowCrossOriginRequests);
endpoints.push_back(endpoint);
needs_client=true;
void sc_comm_singleton::registerWebSocketHandler(const char *endpoint, std::shared_ptr<WebSocket::Handler> handler,
bool allowCrossOriginRequests) {
get_server().addWebSocketHandler(endpoint, handler, allowCrossOriginRequests);
endpoints.emplace_back(endpoint);
needs_client = true;
}
void sc_comm_singleton::execute(std::function<void()> f) {
get_server().execute(f);
void sc_comm_singleton::execute(std::function<void()> f) { get_server().execute(f); }
void sc_comm_singleton::thread_func() { get_server().serve("./html", 9090); }
Server &sc_comm_singleton::get_server() { return *m_serv.get(); }
std::shared_ptr<Response> sc_comm_singleton::DefaultPageHandler::handle(const Request &request) {
if (request.verb() == Request::Verb::Get && request.getRequestUri() == "conf.json") {
return Response::htmlResponse("{}");
}
return Response::unhandled();
}
void sc_comm_singleton::thread_func() {
get_server().serve("./html", 9090);
void WsHandler::onConnect(WebSocket *connection) { _connections.insert(connection); }
void WsHandler::onData(WebSocket *connection, const char *data) {
if (0 == strcmp("close", data)) {
connection->close();
} else if (callback)
callback(data);
}
Server& sc_comm_singleton::get_server() {
return *m_serv.get();
}
std::shared_ptr<Response> sc_comm_singleton::DefaultPageHandler::handle(const Request& request) {
if(request.verb() == Request::Verb::Get && request.getRequestUri()=="conf.json"){
return Response::htmlResponse("{}");
}
return Response::unhandled();
}
void WsHandler::onConnect(WebSocket* connection) {
_connections.insert(connection);
}
void WsHandler::onData(WebSocket* connection, const char* data) {
if (0 == strcmp("close", data)) {
connection->close();
} else if(callback)
callback(data);
}
void WsHandler::onDisconnect(WebSocket* connection) {
_connections.erase(connection);
}
void WsHandler::onDisconnect(WebSocket *connection) { _connections.erase(connection); }
} /* namespace sysc */

326
platform/src/sysc/spi.cpp
View File

@ -1,60 +1,93 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial implementation
//
//
////////////////////////////////////////////////////////////////////////////////
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/SiFive/spi.h"
#include "cci_configuration"
#include "scc/signal_initiator_mixin.h"
#include "scc/signal_target_mixin.h"
#include "scc/tlm_target.h"
#include "sysc/tlm_extensions.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/spi_regs.h"
#include "sysc/tlm_extensions.h"
#include <util/ities.h>
namespace sysc {
namespace spi_impl {
using namespace sc_core;
spi::spi(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
class beh : public sysc::spi, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(beh); // NOLINT
cci::cci_param<bool> bit_true_transfer;
beh(sc_core::sc_module_name nm);
~beh() override;
protected:
scc::tlm_signal_bool_opt_out _sck_o;
scc::tlm_signal_bool_opt_out _mosi_o;
scc::tlm_signal_bool_opt_in _miso_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> _scs_o;
void clock_cb();
void reset_cb();
void transmit_data();
void receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
void update_irq();
sc_core::sc_event update_irq_evt;
sc_core::sc_time clk;
std::unique_ptr<spi_regs> regs;
sc_core::sc_fifo<uint8_t> rx_fifo, tx_fifo;
};
beh::beh(sc_core::sc_module_name nm)
: sysc::spi(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMED(sck_o)
, NAMED(mosi_o)
, NAMED(miso_i)
, NAMED(scs_o, 4)
, NAMED(irq_o)
, NAMED(_sck_o)
, NAMED(_mosi_o)
, NAMED(_miso_i)
, NAMED(_scs_o, 4)
, NAMED(bit_true_transfer, false)
, NAMEDD(spi_regs, regs) {
, NAMEDD(regs, spi_regs)
, rx_fifo(8)
, tx_fifo(8) {
spi::socket(scc::tlm_target<>::socket);
_sck_o(sck_o);
_mosi_o(mosi_o);
miso_i(_miso_i);
_scs_o(scs_o);
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive << clk_i;
@ -62,158 +95,177 @@ spi::spi(sc_core::sc_module_name nm)
sensitive << rst_i;
dont_initialize();
SC_THREAD(transmit_data);
miso_i.register_nb_transport([this](tlm::tlm_signal_gp<bool>& gp,
tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
this->receive_data(gp, delay);
return tlm::TLM_COMPLETED;
});
regs->txdata.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
_miso_i.register_nb_transport(
[this](tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->receive_data(gp, delay);
return tlm::TLM_COMPLETED;
});
regs->txdata.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
if (!this->regs->in_reset()) {
reg.put(data);
tx_fifo.nb_write(static_cast<uint8_t>(regs->r_txdata.data));
regs->r_txdata.full=tx_fifo.num_free()==0;
update_irq();
}
return true;
});
regs->rxdata.set_read_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t& data) -> bool {
regs->rxdata.set_read_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
if (!this->regs->in_reset()) {
uint8_t val;
if(rx_fifo.nb_read(val)){
regs->r_rxdata.empty=0;
regs->r_rxdata.data=val;
if(regs->r_rxmark.rxmark<=rx_fifo.num_available()){
regs->r_ip.rxwm=1;
if (rx_fifo.nb_read(val)) {
regs->r_rxdata.empty = 0;
regs->r_rxdata.data = val;
if (regs->r_rxmark.rxmark <= rx_fifo.num_available()) {
regs->r_ip.rxwm = 1;
update_irq();
}
} else
regs->r_rxdata.empty=1;
data = reg.get()&reg.rdmask;
regs->r_rxdata.empty = 1;
data = reg.get() & reg.rdmask;
}
return true;
});
regs->csmode.set_write_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t& data) -> bool {
if(regs->r_csmode.mode==2 && regs->r_csmode.mode != bit_sub<0, 2>(data) && regs->r_csid<4){
regs->csmode.set_write_cb(
[this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
if (regs->r_csmode.mode == 2 && regs->r_csmode.mode != bit_sub<0, 2>(data) && regs->r_csid < 4) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
sc_core::sc_time delay(SC_ZERO_TIME);
tlm::tlm_signal_gp<> gp;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(true);
_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
}
reg.put(data);
return true;
});
regs->csid.set_write_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
if (regs->r_csmode.mode == 2 && regs->csid != data && regs->r_csid < 4) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
sc_core::sc_time delay(SC_ZERO_TIME);
tlm::tlm_signal_gp<> gp;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(true);
scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
}
reg.put(data);
return true;
});
regs->csid.set_write_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t& data) -> bool {
if(regs->r_csmode.mode==2 && regs->csid != data && regs->r_csid<4){
tlm::tlm_phase phase(tlm::BEGIN_REQ);
sc_core::sc_time delay(SC_ZERO_TIME);
tlm::tlm_signal_gp<> gp;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(true);
scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
}
reg.put(data);
return true;
});
regs->csdef.set_write_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t& data) -> bool {
regs->csdef.set_write_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
auto diff = regs->csdef ^ data;
if(regs->r_csmode.mode==2 && diff!=0 && (regs->r_csid<4) && (diff & (1<<regs->r_csid))!=0){
if (regs->r_csmode.mode == 2 && diff != 0 && (regs->r_csid < 4) && (diff & (1 << regs->r_csid)) != 0) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
sc_core::sc_time delay(SC_ZERO_TIME);
tlm::tlm_signal_gp<> gp;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(true);
scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
}
reg.put(data);
return true;
});
regs->ie.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
update_irq();
regs->ie.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
reg.put(data);
update_irq_evt.notify();
return true;
});
regs->ip.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
update_irq();
regs->ip.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
reg.put(data);
update_irq_evt.notify();
return true;
});
SC_METHOD(update_irq);
sensitive << update_irq_evt << rx_fifo.data_written_event() << rx_fifo.data_read_event()
<< tx_fifo.data_written_event() << tx_fifo.data_read_event();
}
spi::~spi() {}
beh::~beh() = default;
void spi::clock_cb() {
this->clk = clk_i.read();
}
void beh::clock_cb() { this->clk = clk_i.read(); }
void spi::reset_cb() {
void beh::reset_cb() {
if (rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
void spi::transmit_data() {
void beh::transmit_data() {
uint8_t txdata;
sysc::tlm_signal_spi_extension ext;
tlm::tlm_phase phase(tlm::BEGIN_REQ);
tlm::tlm_signal_gp<> gp;
sc_core::sc_time delay(SC_ZERO_TIME);
sc_core::sc_time bit_duration(SC_ZERO_TIME);
sc_core::sc_time start_time;
gp.set_extension(&ext);
ext.tx.data_bits=8;
auto set_bit = [&](bool val, scc::tlm_signal_bool_opt_out& socket){
if(socket.get_interface()==nullptr) return;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(val);
auto set_bit = [&](bool val, scc::tlm_signal_bool_opt_out &socket,
bool data_valid = false) -> std::pair<bool, uint32_t> {
if (socket.get_interface() == nullptr) return std::pair<bool, uint32_t>{false, 0};
auto *gp = tlm::tlm_signal_gp<>::create();
auto *ext = new sysc::tlm_signal_spi_extension();
ext->tx.data_bits = 8;
ext->start_time = start_time;
ext->tx.m2s_data = txdata;
ext->tx.m2s_data_valid = data_valid;
ext->tx.s2m_data_valid = false;
gp->set_extension(ext);
gp->set_command(tlm::TLM_WRITE_COMMAND);
gp->set_value(val);
tlm::tlm_phase phase(tlm::BEGIN_REQ);
socket->nb_transport_fw(gp, phase, delay);
gp->acquire();
phase = tlm::BEGIN_REQ;
delay = SC_ZERO_TIME;
socket->nb_transport_fw(*gp, phase, delay);
std::pair<bool, uint32_t> ret{ext->tx.s2m_data_valid != 0, ext->tx.s2m_data};
gp->release();
return ret;
};
wait(delay); //intentionally 0ns;
while(true){
wait(delay); // intentionally 0ns;
while (true) {
wait(tx_fifo.data_written_event());
if(regs->r_csmode.mode != 3 && regs->r_csid<4) // not in OFF mode
set_bit(false, scs_o[regs->r_csid]);
set_bit(regs->r_sckmode.pol, sck_o);
while(tx_fifo.nb_read(txdata)){
regs->r_txdata.full=tx_fifo.num_free()==0;
regs->r_ip.txwm=regs->r_txmark.txmark<=(7-tx_fifo.num_free())?1:0;
bit_duration = 2*(regs->r_sckdiv.div+1)*clk;
ext.start_time = sc_core::sc_time_stamp();
ext.tx.m2s_data=txdata;
ext.tx.s2m_data_valid=false;
set_bit(txdata&0x80, mosi_o); // 8 data bits, MSB first
set_bit(1-regs->r_sckmode.pol, sck_o);
wait(bit_duration/2);
set_bit(regs->r_sckmode.pol, sck_o);
wait(bit_duration/2);
if(bit_true_transfer.get_value()){
for(size_t i = 0, mask=0x40; i<7; ++i, mask>=1){
set_bit(txdata&mask, mosi_o); // 8 data bits, MSB first
set_bit(1-regs->r_sckmode.pol, sck_o);
wait(bit_duration/2);
set_bit(regs->r_sckmode.pol, sck_o);
wait(bit_duration/2);
if (regs->r_csmode.mode != 3 && regs->r_csid < 4) // not in OFF mode
set_bit(false, _scs_o[regs->r_csid]);
set_bit(regs->r_sckmode.pol, _sck_o);
while (tx_fifo.nb_read(txdata)) {
regs->r_txdata.full = tx_fifo.num_free() == 0;
regs->r_ip.txwm = regs->r_txmark.txmark <= (7 - tx_fifo.num_free()) ? 1 : 0;
update_irq_evt.notify();
bit_duration = 2 * (regs->r_sckdiv.div + 1) * clk;
start_time = sc_core::sc_time_stamp();
set_bit(txdata & 0x80, _mosi_o); // 8 data bits, MSB first
auto s2m = set_bit(1 - regs->r_sckmode.pol, _sck_o, true);
wait(bit_duration / 2);
set_bit(regs->r_sckmode.pol, _sck_o, true);
wait(bit_duration / 2);
if (bit_true_transfer.get_value()) {
for (size_t i = 0, mask = 0x40; i < 7; ++i, mask >= 1) {
set_bit(txdata & mask, _mosi_o); // 8 data bits, MSB first
set_bit(1 - regs->r_sckmode.pol, _sck_o);
wait(bit_duration / 2);
set_bit(regs->r_sckmode.pol, _sck_o);
wait(bit_duration / 2);
}
} else
wait(7*bit_duration);
rx_fifo.nb_write(ext.tx.s2m_data&0xff);
if(regs->r_rxmark.rxmark<=rx_fifo.num_available()){
regs->r_ip.rxwm=1;
update_irq();
}
wait(7 * bit_duration);
if (s2m.first) rx_fifo.nb_write(s2m.second & 0xff);
update_irq_evt.notify();
}
if(regs->r_csmode.mode == 0 && regs->r_csid<4) // in AUTO mode
set_bit(false, scs_o[regs->r_csid]);
if (regs->r_csmode.mode == 0 && regs->r_csid < 4) // in AUTO mode
set_bit(false, _scs_o[regs->r_csid]);
}
}
void spi::receive_data(tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay) {
}
void beh::receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {}
void spi::update_irq() {
void beh::update_irq() {
regs->r_ip.rxwm = regs->r_rxmark.rxmark < rx_fifo.num_available();
regs->r_ip.txwm = regs->r_txmark.txmark <= tx_fifo.num_available();
regs->r_txdata.full = tx_fifo.num_free() == 0;
irq_o.write((regs->r_ie.rxwm > 0 && regs->r_ip.rxwm > 0) || (regs->r_ie.txwm > 0 && regs->r_ip.txwm > 0));
}
} /* namespace spi:impl */
template <> std::unique_ptr<spi> spi::create<sysc::spi_impl::beh>(sc_core::sc_module_name nm) {
auto *res = new sysc::spi_impl::beh(nm);
return std::unique_ptr<spi>(res);
}
} /* namespace sysc */

135
platform/src/sysc/system.cpp
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@ -1,88 +1,115 @@
/*
* system.cpp
/*******************************************************************************
* Copyright (C) 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Created on: 11.07.2018
* Author: eyck
*/
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/top/system.h"
using namespace sysc;
using namespace sc_core;
system::system(sc_core::sc_module_name nm)
system::system(sc_module_name nm)
: sc_module(nm)
, NAMED(s_gpio, 32)
, NAMED(s_ha)
, NAMED(s_la)
, NAMED(s_hb)
, NAMED(s_lb)
, NAMED(s_hc)
, NAMED(s_lc)
, NAMED(s_rst_n)
, NAMED(s_vref)
, NAMED(s_va)
, NAMED(s_vb)
, NAMED(s_vc)
, NAMED(s_ana, 5)
, NAMED(i_platform)
, NAMED(i_terminal)
, NAMED(i_adc)
, NAMED(s_vasens)
, NAMED(s_vbsens)
, NAMED(s_vcsens)
, NAMED(s_vcentersens)
, NAMED(s_ana, 4)
, NAMED(i_hifive1)
, NAMED(i_h_bridge)
, NAMED(i_motor)
{
, NAMED(i_motor) {
// connect platform
i_platform.erst_n(s_rst_n);
for(auto i=0U; i<s_gpio.size(); ++i){
s_gpio[i].in(i_platform.pins_o[i]);
i_platform.pins_i[i](s_gpio[i].out);
}
// connect other units
// terminal
i_terminal.tx_o(s_gpio[16].in);
s_gpio[17].out(i_terminal.rx_i);
// adc digital io
s_gpio[2].out(i_adc.cs_i);
s_gpio[3].out(i_adc.mosi_i);
i_adc.miso_o(s_gpio[4].in);
s_gpio[5].out(i_adc.sck_i);
// adc analog inputs
i_adc.vref_i(s_vref);
i_adc.ch_i[0](s_vasens);
i_adc.ch_i[1](s_vbsens);
i_adc.ch_i[2](s_vcsens);
i_adc.ch_i[3](s_ana[0]);
i_adc.ch_i[4](s_ana[1]);
i_adc.ch_i[5](s_ana[2]);
i_adc.ch_i[6](s_ana[3]);
i_adc.ch_i[7](s_ana[4]);
i_h_bridge.ha_i(s_gpio[0]);
i_h_bridge.la_i(s_gpio[1]);
i_h_bridge.hb_i(s_gpio[10]);
i_h_bridge.lb_i(s_gpio[11]);
i_h_bridge.hc_i(s_gpio[19]);
i_h_bridge.lc_i(s_gpio[20]);
i_hifive1.erst_n(s_rst_n);
// HiFive1 digital out
i_hifive1.ha_o(s_ha);
i_hifive1.la_o(s_la);
i_hifive1.hb_o(s_hb);
i_hifive1.lb_o(s_lb);
i_hifive1.hc_o(s_hc);
i_hifive1.lc_o(s_lc);
// HiFive1 analog in
i_hifive1.vref_i(s_vref);
i_hifive1.adc_ch0_i(s_vasens);
i_hifive1.adc_ch1_i(s_vbsens);
i_hifive1.adc_ch2_i(s_vcsens);
i_hifive1.adc_ch3_i(s_vcentersens);
i_hifive1.adc_ch4_i(s_ana[0]);
i_hifive1.adc_ch5_i(s_ana[1]);
i_hifive1.adc_ch6_i(s_ana[2]);
i_hifive1.adc_ch7_i(s_ana[3]);
// H-bridge digital in
i_h_bridge.ha_i(s_ha);
i_h_bridge.la_i(s_la);
i_h_bridge.hb_i(s_hb);
i_h_bridge.lb_i(s_lb);
i_h_bridge.hc_i(s_hc);
i_h_bridge.lc_i(s_lc);
// H-bridge analog out
i_h_bridge.va_o(s_va);
i_h_bridge.vb_o(s_vb);
i_h_bridge.vc_o(s_vc);
// motor analog in
i_motor.va_i(s_va);
i_motor.vb_i(s_vb);
i_motor.vc_i(s_vc);
// motor analog out
i_motor.va_o(s_vasens);
i_motor.vb_o(s_vbsens);
i_motor.vc_o(s_vcsens);
i_motor.vcenter_o(s_vcentersens);
SC_THREAD(gen_por);
}
system::~system() {
}
system::~system() = default;
void sysc::system::gen_por() {
// single shot
s_rst_n = false;
wait(10_ns);
wait(1_us);
s_rst_n = true;
s_vref=1.024;
double val=0.1;
for(auto& sig:s_ana){
sig=val;
val+=0.12;
s_vref = 4.8;
double val = 0.1;
for (auto &sig : s_ana) {
sig = val;
val += 0.12;
}
}

84
platform/src/sysc/terminal.cpp
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@ -1,68 +1,86 @@
/*
* terminal.cpp
/*******************************************************************************
* Copyright (C) 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Created on: 07.07.2018
* Author: eyck
*/
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/top/terminal.h"
#include "scc/report.h"
#include "sysc/sc_comm_singleton.h"
#include "sysc/tlm_extensions.h"
#include "scc/report.h"
using namespace sysc;
terminal::terminal()
: terminal(sc_core::sc_gen_unique_name("terminal"))
{
}
: terminal(sc_core::sc_gen_unique_name("terminal")) {}
terminal::terminal(const sc_core::sc_module_name& nm)
terminal::terminal(const sc_core::sc_module_name &nm)
: sc_core::sc_module(nm)
, NAMED(tx_o)
, NAMED(rx_i)
, NAMED(write_to_ws, false)
{
rx_i.register_nb_transport([this](
tlm::tlm_signal_gp<sc_dt::sc_logic>& gp,
tlm::tlm_phase& phase,
sc_core::sc_time& delay)->tlm::tlm_sync_enum{
, NAMED(write_to_ws, false) {
rx_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->receive(gp, delay);
return tlm::TLM_COMPLETED;
});
}
terminal::~terminal() {
}
terminal::~terminal() = default;
void terminal::before_end_of_elaboration() {
if(write_to_ws.get_value()) {
LOG(TRACE)<<"Adding WS handler for "<<(std::string{"/ws/"}+name());
handler=std::make_shared<WsHandler>();
sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"}+name()).c_str(), handler);
if (write_to_ws.get_value()) {
SCTRACE() << "Adding WS handler for " << (std::string{"/ws/"} + name());
handler = std::make_shared<WsHandler>();
sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"} + name()).c_str(), handler);
}
}
void terminal::receive(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, sc_core::sc_time& delay) {
sysc::tlm_signal_uart_extension* ext;
void terminal::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time &delay) {
sysc::tlm_signal_uart_extension *ext;
gp.get_extension(ext);
if(ext && ext->start_time!=last_tx_start){
uint8_t txdata = static_cast<uint8_t>(ext->tx.data);
if (ext && ext->start_time != last_tx_start) {
auto txdata = static_cast<uint8_t>(ext->tx.data);
last_tx_start = ext->start_time;
if(txdata != '\r') queue.push_back(txdata);
if (txdata != '\r') queue.push_back(txdata);
if (queue.size() >> 0 && (txdata == '\n' || txdata == 0)) {
std::string msg(queue.begin(), queue.end()-1);
std::string msg(queue.begin(), queue.end() - 1);
sc_core::sc_time now = sc_core::sc_time_stamp();
if(handler)
sysc::sc_comm_singleton::inst().execute([this, msg, now](){
if (handler)
sysc::sc_comm_singleton::inst().execute([this, msg, now]() {
std::stringstream os;
os << "{\"time\":\"" << now << "\",\"message\":\""<<msg<<"\"}";
os << R"({"time":")" << now << R"(","message":")" << msg << R"("})";
this->handler->send(os.str());
});
else
LOG(INFO) << this->name() << " receive: '" << msg << "'";
SCINFO(this->name()) << " receive: '" << msg << "'";
queue.clear();
}
}

187
platform/src/sysc/uart.cpp
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@ -1,50 +1,46 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial implementation
//
//
////////////////////////////////////////////////////////////////////////////////
/*******************************************************************************
* Copyright (C) 2017, 2018 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
#include "sysc/SiFive/uart.h"
#include "sysc/tlm_extensions.h"
#include "scc/report.h"
#include "scc/utilities.h"
#include "sysc/SiFive/gen/uart_regs.h"
#include "sysc/tlm_extensions.h"
using namespace std;
namespace sysc {
using namespace sc_core;
uart::uart(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
@ -55,10 +51,9 @@ uart::uart(sc_core::sc_module_name nm)
, NAMED(rx_i)
, NAMED(irq_o)
, NAMED(bit_true_transfer, false)
, NAMEDD(uart_regs, regs)
, NAMEDD(regs, uart_regs)
, NAMED(rx_fifo, 8)
, NAMED(tx_fifo, 8)
{
, NAMED(tx_fifo, 8) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive << clk_i;
@ -66,52 +61,52 @@ uart::uart(sc_core::sc_module_name nm)
sensitive << rst_i;
dont_initialize();
SC_THREAD(transmit_data);
rx_i.register_nb_transport([this](tlm::tlm_signal_gp<bool>& gp,
tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
this->receive_data(gp, delay);
return tlm::TLM_COMPLETED;
});
regs->txdata.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
rx_i.register_nb_transport(
[this](tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->receive_data(gp, delay);
return tlm::TLM_COMPLETED;
});
regs->txdata.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
if (!this->regs->in_reset()) {
reg.put(data);
tx_fifo.nb_write(static_cast<uint8_t>(regs->r_txdata.data));
regs->r_txdata.full=tx_fifo.num_free()==0;
regs->r_ip.txwm=regs->r_txctrl.txcnt<=(7-tx_fifo.num_free())?1:0;
regs->r_txdata.full = tx_fifo.num_free() == 0;
regs->r_ip.txwm = regs->r_txctrl.txcnt <= (7 - tx_fifo.num_free()) ? 1 : 0;
update_irq();
}
return true;
});
regs->rxdata.set_read_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t& data) -> bool {
regs->rxdata.set_read_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
if (!this->regs->in_reset()) {
uint8_t val;
if(rx_fifo.nb_read(val)){
regs->r_rxdata.data=val;
if(regs->r_rxctrl.rxcnt<=rx_fifo.num_available()){
regs->r_ip.rxwm=1;
if (rx_fifo.nb_read(val)) {
regs->r_rxdata.data = val;
if (regs->r_rxctrl.rxcnt <= rx_fifo.num_available()) {
regs->r_ip.rxwm = 1;
update_irq();
}
}
data = reg.get()&reg.rdmask;
data = reg.get() & reg.rdmask;
}
return true;
});
regs->ie.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->ie.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
update_irq();
return true;
});
regs->ip.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data) -> bool {
regs->ip.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
update_irq();
return true;
});
}
uart::~uart() {}
uart::~uart() = default;
void uart::update_irq() {
irq_o=(regs->r_ip.rxwm==1 && regs->r_ie.rxwm==1) || (regs->r_ip.txwm==1 && regs->r_ie.txwm==1);
irq_o = (regs->r_ip.rxwm == 1 && regs->r_ie.rxwm == 1) || (regs->r_ip.txwm == 1 && regs->r_ie.txwm == 1);
}
void uart::clock_cb() {
this->clk = clk_i.read();
}
void uart::clock_cb() { this->clk = clk_i.read(); }
void uart::reset_cb() {
if (rst_i.read())
@ -122,62 +117,64 @@ void uart::reset_cb() {
void uart::transmit_data() {
uint8_t txdata;
sysc::tlm_signal_uart_extension ext;
tlm::tlm_phase phase(tlm::BEGIN_REQ);
tlm::tlm_signal_gp<> gp;
sc_core::sc_time delay(SC_ZERO_TIME);
sc_core::sc_time bit_duration(SC_ZERO_TIME);
sc_core::sc_time start_time;
gp.set_extension(&ext);
ext.tx.data_bits=8;
ext.tx.parity=false;
auto set_bit = [&](bool val){
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(val);
tlm::tlm_phase phase(tlm::BEGIN_REQ);
tx_o->nb_transport_fw(gp, phase, delay);
if(delay<bit_duration) wait(bit_duration-delay);
auto set_bit = [&](bool val) {
auto *gp = tlm::tlm_signal_gp<>::create();
auto *ext = new sysc::tlm_signal_uart_extension();
ext->tx.data_bits = 8;
ext->tx.parity = false;
ext->start_time = start_time;
ext->tx.baud_rate = static_cast<unsigned>(1 / bit_duration.to_seconds());
ext->tx.stop_bits = 1 + regs->r_txctrl.nstop;
ext->tx.data = txdata;
gp->set_extension(ext);
gp->set_command(tlm::TLM_WRITE_COMMAND);
gp->set_value(val);
gp->acquire();
phase = tlm::BEGIN_REQ;
delay = SC_ZERO_TIME;
tx_o->nb_transport_fw(*gp, phase, delay);
gp->release();
if (delay < bit_duration) wait(bit_duration - delay);
};
wait(delay);
while(true){
while (true) {
set_bit(true);
wait(tx_fifo.data_written_event());
while(tx_fifo.nb_read(txdata)){
regs->r_txdata.full=tx_fifo.num_free()==0;
regs->r_ip.txwm=regs->r_txctrl.txcnt<=(7-tx_fifo.num_free())?1:0;
bit_duration = (regs->r_div.div+1)*clk;
ext.start_time = sc_core::sc_time_stamp();
ext.tx.stop_bits=1+regs->r_txctrl.nstop;
ext.tx.baud_rate=static_cast<unsigned>(1/bit_duration.to_seconds());
ext.tx.data=txdata;
while (tx_fifo.nb_read(txdata)) {
regs->r_txdata.full = tx_fifo.num_free() == 0;
regs->r_ip.txwm = regs->r_txctrl.txcnt <= (7 - tx_fifo.num_free()) ? 1 : 0;
bit_duration = (regs->r_div.div + 1) * clk;
start_time = sc_core::sc_time_stamp();
set_bit(false); // start bit
if(bit_true_transfer.get_value()){
for(int i = 8; i>0; --i)
set_bit(txdata&(1<<(i-1))); // 8 data bits, MSB first
if(regs->r_txctrl.nstop) set_bit(true); // stop bit 1
if (bit_true_transfer.get_value()) {
for (int i = 8; i > 0; --i) set_bit(txdata & (1 << (i - 1))); // 8 data bits, MSB first
if (regs->r_txctrl.nstop) set_bit(true); // stop bit 1
} else
wait(8*bit_duration);
wait(8 * bit_duration);
set_bit(true); // stop bit 1/2
}
}
}
void uart::receive_data(tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay) {
sysc::tlm_signal_uart_extension* ext{nullptr};
void uart::receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
sysc::tlm_signal_uart_extension *ext{nullptr};
gp.get_extension(ext);
if(ext && ext->start_time != rx_last_start){
if (ext && ext->start_time != rx_last_start) {
auto data = static_cast<uint8_t>(ext->tx.data);
if(ext->tx.parity || ext->tx.data_bits!=8) data = rand(); // random value if wrong config
if (ext->tx.parity || ext->tx.data_bits != 8) data = rand(); // random value if wrong config
rx_fifo.write(data);
if(regs->r_rxctrl.rxcnt<=rx_fifo.num_available()){
regs->r_ip.rxwm=1;
if (regs->r_rxctrl.rxcnt <= rx_fifo.num_available()) {
regs->r_ip.rxwm = 1;
update_irq();
}
rx_last_start=ext->start_time; // omit repeated handling of signal changes
rx_last_start = ext->start_time; // omit repeated handling of signal changes
}
gp.set_response_status(tlm::TLM_OK_RESPONSE);
}
} /* namespace sysc */