112 lines
4.2 KiB
C++
112 lines
4.2 KiB
C++
/*******************************************************************************
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* Copyright (C) 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#include <sysc/top/hifive1.h>
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using namespace sc_core;
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using namespace sc_dt;
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using namespace sysc;
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hifive1::hifive1(sc_module_name nm)
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: sc_module(nm)
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, NAMED(erst_n)
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, NAMED(vref_i)
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#define PORT_NAMING(z, n, _) , NAMED(adc_ch##n##_i)
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BOOST_PP_REPEAT(8, PORT_NAMING, _)
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#undef PORT_NAMING
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, NAMED(ha_o)
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, NAMED(la_o)
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, NAMED(hb_o)
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, NAMED(lb_o)
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, NAMED(hc_o)
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, NAMED(lc_o)
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, NAMED(s_gpio, 32)
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, NAMED(h_bridge, 6)
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, NAMED(i_fe310)
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, NAMED(i_terminal)
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, NAMED(i_adc)
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{
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i_fe310.erst_n(erst_n);
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for (auto i = 0U; i < s_gpio.size(); ++i) {
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s_gpio[i].in(i_fe310.pins_o[i]);
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i_fe310.pins_i[i](s_gpio[i].out);
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}
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// connect other units
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// terminal
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i_terminal.tx_o(s_gpio[16].in);
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s_gpio[17].out(i_terminal.rx_i);
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// adc digital io
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s_gpio[2].out(i_adc.cs_i);
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s_gpio[3].out(i_adc.mosi_i);
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i_adc.miso_o(s_gpio[4].in);
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s_gpio[5].out(i_adc.sck_i);
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// adc analog inputs
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i_adc.vref_i(vref_i);
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i_adc.ch_i[0](adc_ch0_i);
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i_adc.ch_i[1](adc_ch1_i);
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i_adc.ch_i[2](adc_ch2_i);
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i_adc.ch_i[3](adc_ch3_i);
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i_adc.ch_i[4](adc_ch4_i);
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i_adc.ch_i[5](adc_ch5_i);
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i_adc.ch_i[6](adc_ch6_i);
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i_adc.ch_i[7](adc_ch7_i);
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// H-Bridge signal proxies
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s_gpio[0].out(h_bridge[0]);
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s_gpio[1].out(h_bridge[1]);
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s_gpio[10].out(h_bridge[2]);
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s_gpio[11].out(h_bridge[3]);
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s_gpio[20].out(h_bridge[4]);
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s_gpio[19].out(h_bridge[5]);
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// proxy callbacks
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h_bridge[0].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
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ha_o.write(gp.get_value());
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});
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h_bridge[1].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
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la_o.write(gp.get_value());
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});
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h_bridge[2].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
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hb_o.write(gp.get_value());
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});
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h_bridge[3].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
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lb_o.write(gp.get_value());
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});
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h_bridge[4].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
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hc_o.write(gp.get_value());
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});
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h_bridge[5].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
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lc_o.write(gp.get_value());
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});
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}
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