Firmware/MNRS-BM-BSP
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Firmware:develop Firmware:flexki Firmware:cmake_flow Firmware:main

3 Commits
c8ea882b3e ... develop

Author SHA1 Message Date
Eyck Jentzsch
499468b819 fixes ACLINT register interface definition 2025-12-14 17:13:09 +01:00
Eyck Jentzsch
925f08e0b9 implements halt using WFI if hartid!=0 and multicore 2025-12-14 17:12:42 +01:00
Eyck Jentzsch
be32d2467c adds all defined aclint regs 2025-12-14 13:37:07 +01:00
3 changed files with 56 additions and 28 deletions
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5
env/riscv_vp/init.c vendored
View File

@@ -103,7 +103,10 @@ void __attribute__((weak)) _init() {
while(i < NUM_INTERRUPTS) { while(i < NUM_INTERRUPTS) {
localISR[i++] = default_handler; localISR[i++] = default_handler;
} }
#endif
#if defined(NUM_HARTS) && NUM_HARTS > 1
for(int i = 1; i < NUM_HARTS; ++i)
set_aclint_msip(aclint, i, 1);
#endif #endif
} }

5
env/start.S vendored
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@@ -30,11 +30,14 @@ _start:
2: 2:
la t0, trap_entry la t0, trap_entry
csrw mtvec, t0 csrw mtvec, t0
#ifdef HARTX_WAIT4WFI #if defined(NUM_HARTS) && NUM_HARTS>1
/* block other cores until hart 0 has finished initialization */ /* block other cores until hart 0 has finished initialization */
csrr t0, mhartid csrr t0, mhartid
beqz t0, hart0_init beqz t0, hart0_init
/* enable MSI locally */
csrwi mie, 0x8
wfi wfi
csrw mie, zero
j hartx_start j hartx_start
hart0_init: hart0_init:
#endif #endif

74
include/minres/devices/gen/aclint.h
View File

@@ -13,26 +13,26 @@
#include <stdint.h> #include <stdint.h>
typedef struct { typedef struct {
volatile uint32_t MSIP0; volatile uint32_t MSIP[4096];
uint8_t fill0[16380]; struct {
volatile uint32_t MTIMECMP0LO; volatile uint32_t LO;
volatile uint32_t MTIMECMP0HI; volatile uint32_t HI;
uint8_t fill1[32752]; } MTIMECMP[4095];
volatile uint32_t MTIME_LO; volatile uint32_t MTIME_LO;
volatile uint32_t MTIME_HI; volatile uint32_t MTIME_HI;
} aclint_t; } aclint_t;
#define ACLINT_MSIP0_OFFS 0 #define ACLINT_MSIP_OFFS 0
#define ACLINT_MSIP0_MASK 0x1 #define ACLINT_MSIP_MASK 0x1
#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS) #define ACLINT_MSIP(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
#define ACLINT_MTIMECMP0LO_OFFS 0 #define ACLINT_MTIMECMPLO_OFFS 0
#define ACLINT_MTIMECMP0LO_MASK 0xffffffff #define ACLINT_MTIMECMPLO_MASK 0xffffffff
#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS) #define ACLINT_MTIMECMPLO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
#define ACLINT_MTIMECMP0HI_OFFS 0 #define ACLINT_MTIMECMPHI_OFFS 0
#define ACLINT_MTIMECMP0HI_MASK 0xffffffff #define ACLINT_MTIMECMPHI_MASK 0xffffffff
#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS) #define ACLINT_MTIMECMPHI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
#define ACLINT_MTIME_LO_OFFS 0 #define ACLINT_MTIME_LO_OFFS 0
#define ACLINT_MTIME_LO_MASK 0xffffffff #define ACLINT_MTIME_LO_MASK 0xffffffff
@@ -43,33 +43,55 @@ typedef struct {
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS) #define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
// ACLINT_MSIP0 // ACLINT_MSIP0
static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP0; } static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP[0]; }
static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP0 = value; } static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP[0] = value; }
static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP0 >> 0) & 0x1; } static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP[0] >> 0) & 0x1; }
static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) { reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); } static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) {
reg->MSIP[0] = (reg->MSIP[0] & ~(0x1U << 0)) | (value << 0);
}
// ACLINT_MSIP
static inline uint32_t get_aclint_msip(volatile aclint_t* reg, unsigned idx) { return reg->MSIP[idx]; }
static inline void set_aclint_msip(volatile aclint_t* reg, unsigned idx, uint32_t value) { reg->MSIP[idx] = value; }
static inline uint32_t get_aclint_msip_msip(volatile aclint_t* reg, unsigned idx) { return (reg->MSIP[idx] >> 0) & 0x1; }
static inline void set_aclint_msip_msip(volatile aclint_t* reg, unsigned idx, uint8_t value) {
reg->MSIP[idx] = (reg->MSIP[idx] & ~(0x1U << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0LO // ACLINT_MTIMECMP0LO
static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff; } static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP[0].LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) { static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0); reg->MTIMECMP[0].LO = (reg->MTIMECMP[0].LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMPxLO
static inline uint32_t get_aclint_mtimecmplo(volatile aclint_t* reg, unsigned idx) { return (reg->MTIMECMP[idx].LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmplo(volatile aclint_t* reg, unsigned idx, uint32_t value) {
reg->MTIMECMP[idx].LO = (reg->MTIMECMP[idx].LO & ~(0xffffffffU << 0)) | (value << 0);
} }
// ACLINT_MTIMECMP0HI // ACLINT_MTIMECMP0HI
static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff; } static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP[0].HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) { static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0); reg->MTIMECMP[0].HI = (reg->MTIMECMP[0].HI & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMPxHI
static inline uint32_t get_aclint_mtimecmphi(volatile aclint_t* reg, unsigned idx) { return (reg->MTIMECMP[idx].HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmphi(volatile aclint_t* reg, unsigned idx, uint32_t value) {
reg->MTIMECMP[idx].HI = (reg->MTIMECMP[idx].HI & ~(0xffffffffU << 0)) | (value << 0);
} }
// ACLINT_MTIME_LO // ACLINT_MTIME_LO
static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; } static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) { static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0); reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
} }
// ACLINT_MTIME_HI // ACLINT_MTIME_HI
static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; } static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) { static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0); reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
} }
#endif /* _BSP_ACLINT_H */ #endif /* _BSP_ACLINT_H */