adds ethmac device file

env/riscv_vp/init.c

@@ -103,7 +103,10 @@ void __attribute__((weak)) _init() {
     while(i < NUM_INTERRUPTS) {
         localISR[i++] = default_handler;
     }
-
+#endif
+#if defined(NUM_HARTS) && NUM_HARTS > 1
+    for(int i = 1; i < NUM_HARTS; ++i)
+        set_aclint_msip(aclint, i, 1);
 #endif
 }
 

env/start.S

@@ -30,11 +30,14 @@ _start:
 2:
     la t0, trap_entry
     csrw mtvec, t0
-#ifdef HARTX_WAIT4WFI
+#if defined(NUM_HARTS)
 	/* block other cores until hart 0 has finished initialization */
 	csrr  t0, mhartid 
 	beqz t0, hart0_init
+	/* enable MSI locally */
+	csrwi mie, 0x8 
 	wfi
+	csrw mie, zero
 	j hartx_start
 hart0_init:
 #endif

include/minres/devices/gen/aclint.h

@@ -13,26 +13,26 @@
 #include <stdint.h>
 
 typedef struct {
-  volatile uint32_t MSIP0;
-  uint8_t fill0[16380];
-  volatile uint32_t MTIMECMP0LO;
-  volatile uint32_t MTIMECMP0HI;
-  uint8_t fill1[32752];
-  volatile uint32_t MTIME_LO;
-  volatile uint32_t MTIME_HI;
+    volatile uint32_t MSIP[4096];
+    struct {
+        volatile uint32_t LO;
+        volatile uint32_t HI;
+    } MTIMECMP[4095];
+    volatile uint32_t MTIME_LO;
+    volatile uint32_t MTIME_HI;
 } aclint_t;
 
-#define ACLINT_MSIP0_OFFS 0
-#define ACLINT_MSIP0_MASK 0x1
-#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
+#define ACLINT_MSIP_OFFS 0
+#define ACLINT_MSIP_MASK 0x1
+#define ACLINT_MSIP(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
 
-#define ACLINT_MTIMECMP0LO_OFFS 0
-#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
-#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
+#define ACLINT_MTIMECMPLO_OFFS 0
+#define ACLINT_MTIMECMPLO_MASK 0xffffffff
+#define ACLINT_MTIMECMPLO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
 
-#define ACLINT_MTIMECMP0HI_OFFS 0
-#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
-#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
+#define ACLINT_MTIMECMPHI_OFFS 0
+#define ACLINT_MTIMECMPHI_MASK 0xffffffff
+#define ACLINT_MTIMECMPHI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
 
 #define ACLINT_MTIME_LO_OFFS 0
 #define ACLINT_MTIME_LO_MASK 0xffffffff
@@ -43,33 +43,55 @@ typedef struct {
 #define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
 
 // ACLINT_MSIP0
-static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP0; }
-static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP0 = value; }
-static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP0 >> 0) & 0x1; }
-static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) { reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); }
+static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP[0]; }
+static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP[0] = value; }
+static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP[0] >> 0) & 0x1; }
+static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) {
+    reg->MSIP[0] = (reg->MSIP[0] & ~(0x1U << 0)) | (value << 0);
+}
+
+// ACLINT_MSIP
+static inline uint32_t get_aclint_msip(volatile aclint_t* reg, unsigned idx) { return reg->MSIP[idx]; }
+static inline void set_aclint_msip(volatile aclint_t* reg, unsigned idx, uint32_t value) { reg->MSIP[idx] = value; }
+static inline uint32_t get_aclint_msip_msip(volatile aclint_t* reg, unsigned idx) { return (reg->MSIP[idx] >> 0) & 0x1; }
+static inline void set_aclint_msip_msip(volatile aclint_t* reg, unsigned idx, uint8_t value) {
+    reg->MSIP[idx] = (reg->MSIP[idx] & ~(0x1U << 0)) | (value << 0);
+}
 
 // ACLINT_MTIMECMP0LO
-static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff; }
+static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP[0].LO >> 0) & 0xffffffff; }
 static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
-  reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
+    reg->MTIMECMP[0].LO = (reg->MTIMECMP[0].LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// ACLINT_MTIMECMPxLO
+static inline uint32_t get_aclint_mtimecmplo(volatile aclint_t* reg, unsigned idx) { return (reg->MTIMECMP[idx].LO >> 0) & 0xffffffff; }
+static inline void set_aclint_mtimecmplo(volatile aclint_t* reg, unsigned idx, uint32_t value) {
+    reg->MTIMECMP[idx].LO = (reg->MTIMECMP[idx].LO & ~(0xffffffffU << 0)) | (value << 0);
 }
 
 // ACLINT_MTIMECMP0HI
-static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff; }
+static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP[0].HI >> 0) & 0xffffffff; }
 static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
-  reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
+    reg->MTIMECMP[0].HI = (reg->MTIMECMP[0].HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+// ACLINT_MTIMECMPxHI
+static inline uint32_t get_aclint_mtimecmphi(volatile aclint_t* reg, unsigned idx) { return (reg->MTIMECMP[idx].HI >> 0) & 0xffffffff; }
+static inline void set_aclint_mtimecmphi(volatile aclint_t* reg, unsigned idx, uint32_t value) {
+    reg->MTIMECMP[idx].HI = (reg->MTIMECMP[idx].HI & ~(0xffffffffU << 0)) | (value << 0);
 }
 
 // ACLINT_MTIME_LO
 static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
 static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
-  reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
+    reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
 }
 
 // ACLINT_MTIME_HI
 static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
 static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
-  reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
+    reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
 }
 
 #endif /* _BSP_ACLINT_H */

include/minres/devices/gen/ethmac.h

@@ -0,0 +1,169 @@
+/*
+* Copyright (c) 2023 - 2026 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2026-01-10 12:50:16 UTC 
+* by peakrdl_mnrs version 1.2.10
+*/
+
+#ifndef _BSP_ETHMAC_H
+#define _BSP_ETHMAC_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t MAC_CTRL;
+    uint8_t fill0[12];
+    volatile uint32_t TX_DATA_REG;
+    volatile uint32_t TX_AVAIL_REG;
+    uint8_t fill1[8];
+    volatile uint32_t RX_DATA_REG;
+    uint8_t fill2[8];
+    volatile uint32_t RX_STAT_REG;
+    volatile uint32_t INT_CTRL_REG;
+}ethmac_t;
+
+#define ETHMAC_MAC_CTRL_TX_FLUSH_OFFS 0
+#define ETHMAC_MAC_CTRL_TX_FLUSH_MASK 0x1
+#define ETHMAC_MAC_CTRL_TX_FLUSH(V) ((V & ETHMAC_MAC_CTRL_TX_FLUSH_MASK) << ETHMAC_MAC_CTRL_TX_FLUSH_OFFS)
+
+#define ETHMAC_MAC_CTRL_TX_SPACE_AVAIL_OFFS 1
+#define ETHMAC_MAC_CTRL_TX_SPACE_AVAIL_MASK 0x1
+#define ETHMAC_MAC_CTRL_TX_SPACE_AVAIL(V) ((V & ETHMAC_MAC_CTRL_TX_SPACE_AVAIL_MASK) << ETHMAC_MAC_CTRL_TX_SPACE_AVAIL_OFFS)
+
+#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_OFFS 2
+#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_MASK 0x1
+#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE(V) ((V & ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_MASK) << ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_OFFS)
+
+#define ETHMAC_MAC_CTRL_RX_FLUSH_OFFS 4
+#define ETHMAC_MAC_CTRL_RX_FLUSH_MASK 0x1
+#define ETHMAC_MAC_CTRL_RX_FLUSH(V) ((V & ETHMAC_MAC_CTRL_RX_FLUSH_MASK) << ETHMAC_MAC_CTRL_RX_FLUSH_OFFS)
+
+#define ETHMAC_MAC_CTRL_RX_DATA_AVAIL_OFFS 5
+#define ETHMAC_MAC_CTRL_RX_DATA_AVAIL_MASK 0x1
+#define ETHMAC_MAC_CTRL_RX_DATA_AVAIL(V) ((V & ETHMAC_MAC_CTRL_RX_DATA_AVAIL_MASK) << ETHMAC_MAC_CTRL_RX_DATA_AVAIL_OFFS)
+
+#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_OFFS 6
+#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_MASK 0x1
+#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE(V) ((V & ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_MASK) << ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_OFFS)
+
+#define ETHMAC_TX_DATA_REG_OFFS 0
+#define ETHMAC_TX_DATA_REG_MASK 0xffffffff
+#define ETHMAC_TX_DATA_REG(V) ((V & ETHMAC_TX_DATA_REG_MASK) << ETHMAC_TX_DATA_REG_OFFS)
+
+#define ETHMAC_TX_AVAIL_REG_OFFS 0
+#define ETHMAC_TX_AVAIL_REG_MASK 0x1ff
+#define ETHMAC_TX_AVAIL_REG(V) ((V & ETHMAC_TX_AVAIL_REG_MASK) << ETHMAC_TX_AVAIL_REG_OFFS)
+
+#define ETHMAC_RX_DATA_REG_OFFS 0
+#define ETHMAC_RX_DATA_REG_MASK 0xffffffff
+#define ETHMAC_RX_DATA_REG(V) ((V & ETHMAC_RX_DATA_REG_MASK) << ETHMAC_RX_DATA_REG_OFFS)
+
+#define ETHMAC_RX_STAT_REG_RX_ERRORS_OFFS 0
+#define ETHMAC_RX_STAT_REG_RX_ERRORS_MASK 0xff
+#define ETHMAC_RX_STAT_REG_RX_ERRORS(V) ((V & ETHMAC_RX_STAT_REG_RX_ERRORS_MASK) << ETHMAC_RX_STAT_REG_RX_ERRORS_OFFS)
+
+#define ETHMAC_RX_STAT_REG_RX_DROPS_OFFS 8
+#define ETHMAC_RX_STAT_REG_RX_DROPS_MASK 0xff
+#define ETHMAC_RX_STAT_REG_RX_DROPS(V) ((V & ETHMAC_RX_STAT_REG_RX_DROPS_MASK) << ETHMAC_RX_STAT_REG_RX_DROPS_OFFS)
+
+#define ETHMAC_INT_CTRL_REG_TX_FREE_INTR_ENABLE_OFFS 0
+#define ETHMAC_INT_CTRL_REG_TX_FREE_INTR_ENABLE_MASK 0x1
+#define ETHMAC_INT_CTRL_REG_TX_FREE_INTR_ENABLE(V) ((V & ETHMAC_INT_CTRL_REG_TX_FREE_INTR_ENABLE_MASK) << ETHMAC_INT_CTRL_REG_TX_FREE_INTR_ENABLE_OFFS)
+
+#define ETHMAC_INT_CTRL_REG_RX_DATA_AVAIL_INTR_ENABLE_OFFS 1
+#define ETHMAC_INT_CTRL_REG_RX_DATA_AVAIL_INTR_ENABLE_MASK 0x1
+#define ETHMAC_INT_CTRL_REG_RX_DATA_AVAIL_INTR_ENABLE(V) ((V & ETHMAC_INT_CTRL_REG_RX_DATA_AVAIL_INTR_ENABLE_MASK) << ETHMAC_INT_CTRL_REG_RX_DATA_AVAIL_INTR_ENABLE_OFFS)
+
+//ETHMAC_MAC_CTRL
+static inline uint32_t get_ethmac_mac_ctrl(volatile ethmac_t* reg){
+     return reg->MAC_CTRL;
+}
+static inline void set_ethmac_mac_ctrl(volatile ethmac_t* reg, uint32_t value){
+     reg->MAC_CTRL = value;
+}
+static inline uint32_t get_ethmac_mac_ctrl_tx_flush(volatile ethmac_t* reg){
+    return (reg->MAC_CTRL >> 0) & 0x1;
+}
+static inline void set_ethmac_mac_ctrl_tx_flush(volatile ethmac_t* reg, uint8_t value){
+    reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_ethmac_mac_ctrl_tx_space_avail(volatile ethmac_t* reg){
+    return (reg->MAC_CTRL >> 1) & 0x1;
+}
+static inline uint32_t get_ethmac_mac_ctrl_tx_aligner_enable(volatile ethmac_t* reg){
+    return (reg->MAC_CTRL >> 2) & 0x1;
+}
+static inline void set_ethmac_mac_ctrl_tx_aligner_enable(volatile ethmac_t* reg, uint8_t value){
+    reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 2)) | (value << 2);
+}
+static inline uint32_t get_ethmac_mac_ctrl_rx_flush(volatile ethmac_t* reg){
+    return (reg->MAC_CTRL >> 4) & 0x1;
+}
+static inline void set_ethmac_mac_ctrl_rx_flush(volatile ethmac_t* reg, uint8_t value){
+    reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 4)) | (value << 4);
+}
+static inline uint32_t get_ethmac_mac_ctrl_rx_data_avail(volatile ethmac_t* reg){
+    return (reg->MAC_CTRL >> 5) & 0x1;
+}
+static inline uint32_t get_ethmac_mac_ctrl_rx_aligner_enable(volatile ethmac_t* reg){
+    return (reg->MAC_CTRL >> 6) & 0x1;
+}
+static inline void set_ethmac_mac_ctrl_rx_aligner_enable(volatile ethmac_t* reg, uint8_t value){
+    reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 6)) | (value << 6);
+}
+
+//ETHMAC_TX_DATA_REG
+static inline uint32_t get_ethmac_tx_data_reg(volatile ethmac_t* reg){
+    return (reg->TX_DATA_REG >> 0) & 0xffffffff;
+}
+static inline void set_ethmac_tx_data_reg(volatile ethmac_t* reg, uint32_t value){
+    reg->TX_DATA_REG = (reg->TX_DATA_REG & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//ETHMAC_TX_AVAIL_REG
+static inline uint32_t get_ethmac_tx_avail_reg(volatile ethmac_t* reg){
+     return reg->TX_AVAIL_REG;
+}
+static inline uint32_t get_ethmac_tx_avail_reg_tx_availibility(volatile ethmac_t* reg){
+    return (reg->TX_AVAIL_REG >> 0) & 0x1ff;
+}
+
+//ETHMAC_RX_DATA_REG
+static inline uint32_t get_ethmac_rx_data_reg(volatile ethmac_t* reg){
+    return (reg->RX_DATA_REG >> 0) & 0xffffffff;
+}
+
+//ETHMAC_RX_STAT_REG
+static inline uint32_t get_ethmac_rx_stat_reg(volatile ethmac_t* reg){
+     return reg->RX_STAT_REG;
+}
+static inline uint32_t get_ethmac_rx_stat_reg_rx_errors(volatile ethmac_t* reg){
+    return (reg->RX_STAT_REG >> 0) & 0xff;
+}
+static inline uint32_t get_ethmac_rx_stat_reg_rx_drops(volatile ethmac_t* reg){
+    return (reg->RX_STAT_REG >> 8) & 0xff;
+}
+
+//ETHMAC_INT_CTRL_REG
+static inline uint32_t get_ethmac_int_ctrl_reg(volatile ethmac_t* reg){
+     return reg->INT_CTRL_REG;
+}
+static inline void set_ethmac_int_ctrl_reg(volatile ethmac_t* reg, uint32_t value){
+     reg->INT_CTRL_REG = value;
+}
+static inline uint32_t get_ethmac_int_ctrl_reg_tx_free_intr_enable(volatile ethmac_t* reg){
+    return (reg->INT_CTRL_REG >> 0) & 0x1;
+}
+static inline void set_ethmac_int_ctrl_reg_tx_free_intr_enable(volatile ethmac_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
+}
+static inline uint32_t get_ethmac_int_ctrl_reg_rx_data_avail_intr_enable(volatile ethmac_t* reg){
+    return (reg->INT_CTRL_REG >> 1) & 0x1;
+}
+static inline void set_ethmac_int_ctrl_reg_rx_data_avail_intr_enable(volatile ethmac_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
+}
+
+#endif /* _BSP_ETHMAC_H */